Schottky diode and buck converter including same

Abstract

Various embodiments of the utility model relate to a Schottky diode and a buck converter comprising the same. The Schottky diode comprises an n-type region, an anode located on the n-type region, a buried p-type region and a shallow p-type region. An interface between the anode and the n-type region forms a Schottky barrier. The n-type channel portion of the n-type region is located between the buried p-type region and the shallow p-type region. The anode may also contact the annular shallow p-type region. In the annular architecture, the buried p-type region and the shallow p-type region are annular regions, and the n-type region includes a central portion surrounded by the annular shallow p-type region and an annular peripheral portion of the n-type region surrounding the annular shallow p-type region. In one application, the buck converter comprises the Schottky diode.

Description

Technical Field

[0001] This utility model relates to a Schottky diode and a buck converter including the same. Background Technology

[0002] The following discussion relates to Schottky diodes and integrated circuit (IC) devices that employ Schottky diodes, such as buck converters and other types of DC-DC power converters. Utility Model Content

[0003] This invention provides a method for manufacturing a Schottky diode. The method includes forming an n-type region in a p-type substrate by ion implantation. The method further includes forming an annular buried p-type region in the n-type region by ion implantation. The method also includes forming an annular shallow p-type region in the n-type region at a depth shallower than the annular buried p-type region by ion implantation, wherein the annular n-type channel portion of the n-type region is located between the annular buried p-type region and the annular shallow p-type region. The method further includes forming the anode of the Schottky diode on the central portion of the n-type region, wherein the interface between the anode and the central portion of the n-type region includes a Schottky barrier.

[0004] Another aspect of this utility model provides a Schottky diode. The Schottky diode includes an n-type region. The Schottky diode also includes an anode located on the n-type region, and the interface between the anode and the n-type region includes a Schottky barrier. The Schottky diode further includes a buried p-type region and a shallow p-type region. An n-type channel portion of the n-type region is located between the buried p-type region and the shallow p-type region.

[0005] Another aspect of this utility model provides a buck converter. The buck converter includes an LC circuit, which includes a sensor, a capacitor, a transistor, and at least one diode connected via a channel across the transistor. The at least one diode includes a Schottky diode, comprising an n-type region, an anode of the Schottky diode disposed on the n-type region, a buried p-type region, and a shallow p-type region, wherein the interface between the anode and the n-type region includes a Schottky barrier. The n-type channel portion of the n-type region is located between the buried p-type region and the shallow p-type region.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 A schematic side cross-sectional view of a Schottky barrier diode is shown.

[0008] Figure 2 and Figure 3 A schematic side cross-sectional view of a Schottky barrier diode is shown. Figure 2) and top view ( Figure 3 ),in Figure 2 The side view section is along Figure 3 The section line SS shown is the cut-off point.

[0009] Figure 4 schematically shown Figure 2 and Figure 3 A side view cross-section of a Schottky barrier diode under forward bias.

[0010] Figure 5 schematically shown Figure 2 and Figure 3 A side view cross-section of a Schottky barrier diode under reverse bias.

[0011] Figure 6 schematically shown Figure 2 and Figure 3 Simulation of the forward bias total current magnitude of a Schottky barrier diode.

[0012] Figure 7 schematically shown Figure 2 and Figure 3 Simulation of reverse bias impact ionization of a Schottky barrier diode.

[0013] Figure 8 A circuit diagram of a buck converter employing a Schottky diode as described herein is shown. Detailed Implementation

[0014] This utility model provides numerous different embodiments or examples of various features for implementing this utility model. Specific examples of components and arrangements are described below to simplify the utility model. These are, of course, merely examples and are not intended to be limiting. For instance, the following description of a first component being formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby potentially preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various instances of this utility model. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions may be used herein to describe the relationship between one component or feature and another shown in the figures. In addition to the orientations depicted in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0016] A Schottky barrier diode (sometimes also called a Schottky diode or hot carrier diode) comprises a rectifier metal / semiconductor junction. Compared to a rectifier p / n junction, the metal / semiconductor junction of a Schottky barrier diode offers advantages such as lower forward voltage drop and faster switching speed. In non-limiting illustrative applications, Schottky barrier diodes can be incorporated into buck converters (a type of DC-DC converter). Some typical performance indicators of a Schottky barrier diode include forward current (If). on The current flowing when a Schottky barrier diode is forward biased, and the reverse current (I0). off The current flowing when the Schottky barrier diode is reverse biased, I on / I off R (resistance in the on state) on The Schottky barrier diode exhibits resistance when forward biased and breakdown voltage (BV). For applications such as buck converters, a large Ig is ideal. on Value, small I off Value, therefore large I on / I off The ratio, and the large breakdown voltage value.

[0017] For a given Schottky barrier diode design, the forward current I on Typically, the area increases with the area of ​​the metal / semiconductor junction (also referred to in this paper as the Schottky barrier diode area or SBD area). A larger Schottky barrier diode area also reduces the forward bias resistance R. onTherefore, high-current applications require a large Schottky barrier diode area. On the other hand, to improve breakdown voltage, the semiconductor beneath the metal / semiconductor junction can have scattered regions with opposite doping polarities (e.g., if the metal / semiconductor junction is a metal / n-type semiconductor junction, p-type doped scattered regions can be provided). Under reverse bias, these regions with opposite doping types can operate to laterally pinch off the reverse current, thereby improving (i.e., increasing) the breakdown voltage. However, these regions with opposite doping types reduce the effective Schottky barrier diode area, thus reducing the forward current IB. on And increase the forward bias resistor R on .

[0018] This design challenge is further amplified when high-current Schottky barrier diodes are fabricated as components of integrated circuits (ICs). For example, buck converters or other DC-DC converters can be fabricated as ICs (or part of an IC), including Schottky barrier diodes as components of the buck converter. Typically, the goal of IC design is the miniaturization of electronic components, including Schottky barrier diodes. This miniaturization drive can be achieved by reducing the area of ​​the Schottky barrier diode, but as mentioned earlier, reducing the Schottky barrier area typically accompanies a forward current If. on Reduce and forward bias resistor R on The increased cost.

[0019] The Schottky barrier diode embodiments disclosed herein advantageously overcome these and other disadvantages. The Schottky barrier diode embodiments disclosed herein provide (or maintain) a high forward current I... on and low-value forward bias resistor R on This simultaneously achieves a small (or reduced) Schottky barrier diode area while maintaining a high breakdown voltage. In some non-limiting illustrative embodiments, a vertical depletion region is formed between the deep p-well (DPW) and the n-type channel region to provide for conducting forward current I under forward bias conditions. on The disclosed Schottky barrier diode provides an improved (i.e., higher) forward current Ib. on and improved (i.e., lower) forward resistance R onThis allows for the application of Schottky barrier diodes without sacrificing their breakdown voltage performance. The Schottky barrier diode embodiments disclosed herein are also advantageously compatible with standard bipolar-CMOS-DMOS (BCD) fabrication workflows and can typically be implemented without adding any additional ion implantation or masking steps to the BCD workflow.

[0020] refer to Figure 1 The diagram schematically shows a side cross-sectional view of a Schottky barrier diode 1. The illustrated Schottky barrier diode 1 includes an n-type region 2, an anode 3 disposed on the n-type region 2, a cathode 4 disposed on the n-type region 2 (and a cathode connection C schematically indicated), a buried p-type region 10, and a shallow p-type region 12. Figure 1 The anode connection A to anode 3 is also schematically shown, and the cathode connection C to cathode 4 is schematically indicated. Interface 13 between anode 3 and n-type region 2 forms or includes a Schottky barrier. In some non-limiting illustrative embodiments, n-type region 2 is n-type silicon and anode 3 is a silicide layer, such as cobalt disilicide (CoSi2) or NiSi (a type of nickel silicide), which provides a Schottky barrier height of approximately 0.6 eV to 0.7 eV. In other embodiments, other silicides are contemplated for use with anode 3, such as erbium disilicide (ErSi). 2-x Examples of suitable silicides include titanium disilicide (TiSi2), platinum silicide (PtSi), and iridium silicide (IrSi). Depending on the choice of silicide, the Schottky barrier height of the Schottky barrier 13 can be designed within a wide range (e.g., about 0.25 eV to 0.95 eV for the aforementioned non-limiting illustrative silicide examples). In other embodiments, the anode is expected to be a metal or metal alloy layer, such as molybdenum, platinum, chromium, tungsten, etc. In some embodiments, the buried p-type region 10 is p-type silicon, and in some embodiments, the shallow p-type region 12 is p-type silicon. Figure 1 As shown, the n-type region 2 includes a central portion 20, a peripheral portion 21, and an n-type channel portion 22. The n-type channel portion 22 is disposed between the buried p-type region 10 and the shallow p-type region 12, and connects the central portion 20 and the peripheral portion 21 of the n-type region 2 to provide a conductive path under forward bias between the anode 3 disposed on the central portion 20 and the cathode 4 disposed on the peripheral portion 21. Therefore, the current flowing between the anode 3 and the cathode 4 flows through the n-type channel portion 22 of the n-type region 2.

[0021] The n-type channel portion 22 of the n-type region 2 achieves the advantages of the previously disclosed Schottky barrier diode. Under forward bias, the n-type channel portion 22 of the n-type region 2 provides a high-conductivity path for forward current flow, thereby achieving a high forward current I. on and low forward resistance R on On the other hand, under reverse bias, a depletion region is formed between the n-type channel portion 22 of the n-type region 2 and the adjacent buried p-type region 10 and shallow p-type region 12. Its function is to pinch off the reverse current, thereby maintaining a low reverse current (I0). off And thus obtain high I on / I off Moreover, it maintains the required high breakdown voltage. Therefore, the n-type channel portion 22 of the n-type region 2 is configured to conduct current between the anode 3 and the cathode 4 when the Schottky diode 1 is forward biased, and to pinch off the current between the anode 3 and the cathode 4 when the Schottky diode 1 is reverse biased. The current pinch-off under reverse bias is achieved by the n-type channel portion 22 of the n-type region 2 being vertically pinched off by the adjacent buried p-type region 10 and shallow p-type region 12.

[0022] In some embodiments, the anode 3 also contacts the shallow p-type region 12, such as Figure 1 As shown. In such an embodiment, when the Schottky barrier diode 1 is forward biased, the p / n junction between the shallow p-type region 12 and the n-type channel portion 22 is forward biased. This forward biased p / n junction further enhances the forward current, thereby advantageously enhancing the forward current I. on And reduced the forward resistance R on Conversely, when the Schottky barrier diode 1 is reverse-biased, this also applies a reverse bias to the p / n junction between the shallow p-type region 12 and the n-type channel portion 22. This further enhances the current pinch-off during reverse bias, thereby reducing Ig. off And improve I on / I off This is also beneficial for maintaining a large breakdown voltage.

[0023] In some embodiments, the Schottky barrier diode 1 has a ring-shaped arrangement. In this ring-shaped arrangement, the buried p-type region 10 is a ring-shaped buried p-type region disposed in the lower part of the n-type region 2. Similarly, the shallow p-type region 12 is a ring-shaped shallow p-type region disposed in the upper part of the n-type region 2. The n-type channel portion 22 of the n-type region 2 is a ring-shaped n-type channel portion 22 disposed between the ring-shaped buried p-type region 10 and the ring-shaped shallow p-type region 12.

[0024] In some embodiments, the Schottky diode 1 is fabricated in a p-type substrate. In such embodiments, the n-type region 2, the buried p-type region 10, and the shallow p-type region 12 are each implantation regions formed in the p-type substrate by ion implantation and include a corresponding dopant distribution generated by ion implantation. The dopant distribution of each region is controlled by ion implantation parameters, such as ion species, ion energy (e.g., higher energy provides deeper implantation), ion beam energy distribution, and implantation dose (e.g., measured in atoms per cubic centimeter, i.e., atoms / cm³). 2 Furthermore, some regions can be selectively formed by two (or more) ion implantations. For example, an n-type region 2 can be formed by two implantations: one ion implantation forms the central portion 20 of the n-type region 2, and another ion implantation forms the peripheral portion 21 and the n-type channel portion 22 of the n-type region 2. In this way, for example, in some embodiments, the central portion 20 can have a higher doping level than the peripheral portion 21 and the channel portion 22.

[0025] refer to Figure 2 and Figure 3 A schematic side cross-sectional view of the Schottky barrier diode 11 is shown. Figure 2 ) and top view ( Figure 3 ). Figure 2 The side view section is along Figure 3 The section line SS shown is the cut-off point. Figure 2 and Figure 3 The Schottky barrier diode 11 is advantageously compatible with standard bipolar-CMOS-DMOS (BCD) fabrication workflows and can typically be implemented without adding any additional ion implantation or masking steps to the BCD workflow. Structurally, Figure 2 and Figure 3 The Schottky barrier diode 11 is similar to Figure 1 The Schottky barrier diode 1 includes an n-type region 2, an anode 3 disposed on the n-type region 2 (and schematically indicated anode connection A), a cathode 4 disposed on the n-type region 2 (and schematically indicated cathode connection C), a buried p-type region 10, and a shallow p-type region 12. For example... Figure 1 In some embodiments, the interface 13 between the anode 3 and the n-type region 2 forms or includes a Schottky barrier. In some non-limiting illustrative embodiments, the n-type region 2 is n-type silicon, and the anode 3 is a silicide layer, such as CoSi2, NiSi, or ErSi. 2-x TiSi2, PtSi, IrSi, etc.; or metal or metal alloy layers, such as molybdenum, platinum, chromium, tungsten, etc. In Figure 2 and Figure 3 In one embodiment, the cathode 4 includes n+ district.

[0026] However, it includes some additional zones and specifies them more specifically. Figure 1 An embodiment of the n-type region 2 of a Schottky barrier diode 1. Figure 2 and Figure 3 In the example, the central portion 20 of the n-type region 2 is formed by ion implantation different from that used to form the peripheral portion 21 and the channel portion 22 of the n-type region 2. In the BCD manufacturing process, the Schottky barrier diode 11 is fabricated on a p-type silicon substrate 30 (its lower portion as shown in the image). Figure 2 As shown), the Schottky barrier diode 11 also includes a containment structure formed in a p-type substrate (or, in another view, the Schottky barrier diode 11 is formed in a containment structure formed in a p-type substrate). The containment structure includes an n-type buried layer (NBL) 32 suitably formed in the p-type substrate by ion implantation, and an annular p-type region (PDD) 34 surrounding the annular buried p-type region 10. The n-type buried layer 32 contacts the n-type buried layer 2 (more specifically, contacts the central portion 20 of the n-type region 2) to prevent the n-type buried layer 2 from being electrically floating. Similarly, the annular p-type region 34 functions as a protective ring and contacts the buried p-type region 10 to prevent the annular p-type region 34 from being electrically floating. The p-type region 34 can selectively be formed as a p-type region 10. + The substrate contact 36 implemented in the region is connected to the substrate terminal Sub. Note that the buried p-type region 10 may also be referred to herein as a deep p-well (DPW) 10, the shallow p-type region 12 may be referred to as a shallow p-well (SPW) 12, the combination of the peripheral portion 21 and the n-type channel portion 22 of the n-type region 2 may also be referred to as an n-type double-diffused (NDD) region, and the central portion 20 of the n-type region 2 may be referred to as a BCD n-type well (BCDNW) 20.

[0027] In a non-limiting manufacturing process compatible with BCD manufacturing workflows, the annular p-type region 34 can be formed by ion implantation, the buried n-type layer 32 can be formed by ion implantation, the buried p-type region 10 can be formed by ion implantation, the central portion 20 of the n-type region 2 can be formed by a first ion implantation, while the peripheral portion 21 and the n-type channel portion 22 of the n-type region 2 can be formed by a second ion implantation, and the shallow p-type region 12 can be formed by ion implantation. In some embodiments, double diffusion or anti-doping can be used for certain regions. For example, in a contemplated workflow, the buried p-type region 10 can be formed by p-type ion implantation, followed by anti-doping of the peripheral portion 21 and the channel portion 22 of the n-type region 2 by double diffusion or by n-type ion implantation, and then the shallow p-type region 12 can be anti-doped using p-type ion implantation. In some embodiments, the ion implantation forming the shallow p-type region 12 can also selectively form the shallow p-type region 12' in the annular p-type region 34. This optional shallow p-type region 12' can improve the connection between the substrate junction 36 and the annular p-type region 34 (e.g., if the p-type doping level of the shallow p-type region 12' is higher than that of the annular p-type region 34) without increasing processing complexity (e.g., without adding additional ion implantation or masking steps). These are merely non-limiting illustrative examples, and many other workflows can be envisioned. Similarly, it is contemplated to use dopant diffusion instead of ion implantation to form one or more of these doped regions.

[0028] In some non-limiting illustrative embodiments, the central portion 20 of the n-type region 2 may have a vertical height of approximately 2.7 micrometers to 3.0 micrometers, the buried p-type region 10 may have a vertical height of approximately 1.2 micrometers, and the vertical height (also referred to as the pinch-off height) of the n-type channel portion 22 located between the buried p-type region 10 and the shallow p-type region 12 is approximately 0.4 micrometers. Again, these are merely non-limiting illustrative ranges applicable to some silicon Schottky diode designs.

[0029] In some non-limiting illustrative examples, the following ion implantation doses are used to form Figure 2 and Figure 3 The Schottky barrier diode 11. The central portion 20 of the n-type region 2 is n-type doped, with an ion implantation dose of 1.5 × 10⁻⁶. 12 atoms / cm 2 Up to 1×10 13 atoms / cm 2 The peripheral portion 21 and channel portion 22 of the n-type region 2 are n-type doped, with an ion implantation dose of 1×10⁻⁶. 12 atoms / cm 2 Up to 5×10 12 atoms / cm 2The buried p-type region 10 is p-type doped, and the ion implantation dose is 5 × 10⁻⁶. 12 atoms / cm 2 Up to 2×10 13 atoms / cm 2 The shallow p-type region 12 (and optionally the corresponding region 12') is p-type doped with an ion implantation dose of 5 × 10⁻⁶. 12 atoms / cm 2 Up to 1×10 13 atoms / cm 2 The annular p-type region 34 is p-type doped, with an ion implantation dose of 1×10⁻⁶. 12 atoms / cm 2 Up to 5×10 12 atoms / cm 2 The buried n-type layer 32 is n-type doped, and the ion implantation dose is approximately 1 × 10⁻⁶. 14 atoms / cm 2 Again, these are merely non-limiting illustrative ranges applicable to some silicon Schottky diode designs.

[0030] Continue to refer to Figure 2 and Figure 3 The illustrative Schottky barrier diode 11 also includes a shallow trench isolation (STI) region 40, which provides electrical isolation between the anode 3 and the cathode 4, and between the cathode 4 and the annular p-type region (PDD) 34. The STI region 40 is suitably silicon dioxide, but other dielectric materials may also be considered for the STI region 40. Special Reference Figure 3 As shown in the top view, the Schottky barrier diode 11 has a ring-shaped arrangement, wherein the buried p-type region 10 is a ring-shaped buried p-type region disposed in the lower part of the n-type region 2, the shallow p-type region 12 is a ring-shaped shallow p-type region disposed in the upper part of the n-type region 2, and the n-type channel portion 22 of the n-type region 2 is a ring-shaped n-type channel portion 22 disposed between the ring-shaped buried p-type region 10 and the ring-shaped shallow p-type region 12. Figure 3 In the examples, these annular areas have rectangular outer and inner circumferences, but other shapes (circles, ellipses, squares, hexagons, etc.) can also be considered as alternative designs.

[0031] In other words, the Schottky diode 11 includes an n-type region 2, an anode 3 disposed on the n-type region 2, a buried p-type region 10, and a shallow p-type region 12. An interface 13 between the anode 3 and the n-type region 2 forms a Schottky barrier. An n-type channel portion 22 of the n-type region 2 is disposed between the buried p-type region 10 and the shallow p-type region 12. In some embodiments, the anode 3 also contacts the annular shallow p-type region 12. In some such embodiments, the buried p-type region 10 is an annular buried p-type region disposed in the lower part of the n-type region 2, and the shallow p-type region 12 is an annular shallow p-type region disposed in the upper part of the n-type region 2, with the n-type channel portion 22 connecting the central portion 20 of the n-type region 2 and the annular peripheral portion 21 of the n-type region 2. In this annular structure, the central portion 20 is surrounded by the annular shallow p-type region 12, and the annular peripheral portion 21 of the n-type region 2 surrounds the annular shallow p-type region 12.

[0032] as Figure 1 Schottky barrier diode 1, Figure 2 and Figure 3 In some embodiments, the Schottky barrier diode 11 is a silicon device, wherein the n-type region 2 (including the central portion 20, the peripheral portion 21, and the channel portion 22) and the buried n-type layer 32 are n-type silicon, the p-type regions 10, 12, and 34 are p-type silicon, and the substrate 30 is p-type silicon. However, it is contemplated that the Schottky barrier diode 11 can be fabricated using other material systems (e.g., silicon carbide).

[0033] refer to Figure 4 Schematic illustration Figure 2 and Figure 3 The Schottky barrier diode 11 operates under forward bias. Under forward bias, a forward current 44 flows from the anode 3, through the central portion 20 of the n-type region 2, through the n-type channel portion 22, and into the peripheral portion 21, reaching the cathode 4. Under forward bias, the n-type channel portion 22 provides a low-resistance path for the forward current 44, thereby providing a high forward current I. on and low forward resistance R on In some embodiments, such as the illustrative example, the illustrative anode 3 is also disposed above and electrically contacts the shallow p-type doped region 12, thereby forming a forward-biased p / n junction between the shallow p-type doped region 12 and the n-type channel portion 22 during forward biasing of the Schottky diode 11. This forward-biased p / n junction further enhances the forward current I. on And reduce the forward resistance R on .

[0034] refer to Figure 5 Schematic illustration Figure 2 and Figure 3The Schottky barrier diode 11 operates under reverse bias. Under reverse bias, the channel portion 22 of the n-type region 2 is pinched off (e.g., ...). Figure 5 (Indicated by barrier 46), thereby suppressing the reverse bias current I. off And maintain a high breakdown voltage (BV). In some embodiments, such as the illustrative example, the illustrative anode 3 also covers and electrically contacts the shallow p-type doped region 12, thereby forming a reverse-biased p / n junction between the shallow p-type doped region 12 and the n-type channel portion 22 during reverse bias of the Schottky diode 11. This reverse-biased p / n junction further enhances current pinch-off during reverse bias, thereby reducing IV. off And improve I on / I off Compared to other methods, this is beneficial for maintaining a large breakdown voltage.

[0035] Now for reference Figure 6 and Figure 7 The reference was displayed. Figures 2 to 5 The technology computer-aided design (TCAD) simulation of the Schottky barrier diode 11 is described. Figure 6 and Figure 7 By along Figure 3 The side view section cut from segment line SS shown is illustrated in the TCAD simulation. Figure 6 and Figure 7 In the middle: the buried p-type layer 10 is represented by the abbreviation "DPW"; the shallow p-type layer 12 is represented by the abbreviation "SHP"; the anode 3 is marked with the letter "A" and the cathode 4 is marked with the letter "C". As mentioned above, the n-type channel portion 22 of the n-type region 2 is located between the buried p-type layer (DPW) 10 and the shallow p-type layer (SHP) 12.

[0036] Figure 6 The TCAD simulation plot of the total current density of the Schottky barrier diode 11 during forward bias is shown. Figure 6 As shown, approximately 5 × 10⁻⁶ was observed. 4 A-cm -2 Up to 6×10 4 A-cm -2 A peak current density of 50 flows through the n-type channel portion 22 of the n-type region 2. (Return to reference) Figure 3 From the top view, it should be understood that this high peak current density exists in the annular region of the Schottky barrier diode 11, which corresponds to... Figure 3The annular region of the shallow p-type layer 12 is shown. Furthermore, the Schottky barrier diode region corresponds to the lateral region of the central portion 20 of the n-type region 2. This region is completely open (i.e., no STI region is located in this region), thus maximizing the Schottky barrier diode area for a given lateral area of ​​the central portion 20 of the n-type region 2. Therefore, according to... Figure 6 TCAD simulations are expected to achieve a high total forward current I0. on .

[0037] Figure 7 The TCAD simulation plot of the impact ionization (log I×I) of the Schottky barrier diode 11 during reverse bias is shown. Figure 7 As observed, the n-type channel portion 22 of the n-type region 2 is effectively pinched off during reverse bias. The contribution of the p / n junction at the interface between the shallow p-type region (SHP) 12 and the n-type channel portion 22 is also significant. Therefore, according to Figure 7 TCAD simulations are expected to achieve low reverse current I off And high breakdown voltage.

[0038] According to Figure 2 and Figure 3 An illustrative embodiment of a Schottky barrier diode was fabricated, and experimental measurements of its forward and reverse bias current-voltage (IV) curves were performed. A high I value was observed at a forward bias of 0.45 volts. on =2.16 microamperes / micrometer and low R on =0.021 ohms-mm 2 This confirms the favorable high-current performance. For reverse bias, a low reverse current I was observed at a reverse bias of 10 volts. off =8.00×10 -14 The measured amperes / micrometers, along with a high breakdown voltage of BV = 26.2 volts, confirm the favorable low reverse bias leakage current and high breakdown voltage. The corresponding ratio I... on / I off =2.7×10 7 .

[0039] The Schottky barrier diode embodiments disclosed herein are suitable for manufacturing as components of integrated circuits (ICs), such as Schottky diodes in standard bipolar-CMOS-DMOS (BCD) manufacturing processes.

[0040] refer to Figure 8In a non-limiting illustrative example, an illustrative Schottky barrier diode 11 is incorporated into a buck converter 60. A buck converter (also known as a step-down converter) is a switching DC-DC converter that converts an input voltage Vi into a lower voltage, higher current signal at the output voltage Vo. Using the Schottky barrier diode 11 in the buck converter reduces switching losses due to the dead time during recovery from the reverse bias state. Figure 8 The illustrative buck converter includes an n-type metal-oxide-semiconductor (NMOS) transistor T1, an NMOS transistor T2, and an LC circuit. This LC circuit includes a sensor L1 and a capacitor C1 connected in series across the channel of the NMOS transistor T2. A Schottky barrier diode 11 also crosses the channel of the NMOS transistor T2, and a p / n junction diode D is optionally connected in parallel with the Schottky barrier diode 11 (and therefore also crosses the channel of the NMOS transistor T2). The body terminal of each NMOS transistor T1 and T2 is connected to its source terminal. An input voltage Vi is applied to the drain terminal of the NMOS transistor T1, and an output voltage Vo is transmitted at the node connecting the sensor L1 and capacitor C1 in series. A driver IC 62 applies a drive signal to the bases of the NMOS transistors T1 and T2. Advantageously, Figure 8 The buck converter 60 can be manufactured as an integrated circuit, for example, using BCD technology.

[0041] The buck converter is based on Figure 8 The circuit was constructed as follows. The experimental efficiency was measured as a function of input power. Efficiency exceeded 90% at test input power of 100 watts or higher, and reached approximately 95% at the highest test input power of approximately 270 watts.

[0042] Some further embodiments are described below.

[0043] In a non-limiting illustrative embodiment, a method for manufacturing a Schottky diode is disclosed. The method includes: forming an n-type region in a p-type substrate by ion implantation; forming an annular buried p-type region in the n-type region by ion implantation; forming an annular shallow p-type region in the n-type region at a depth shallower than the annular buried p-type region by ion implantation, wherein an annular n-type channel portion of the n-type region is located between the annular buried p-type region and the annular shallow p-type region; and forming an anode of the Schottky diode on a central portion of the n-type region, wherein the interface between the anode and the central portion of the n-type region includes a Schottky barrier.

[0044] In some embodiments, the n-type region further includes an annular peripheral portion surrounding the annular shallow p-type region, and an annular n-type channel portion of the n-type region connects the central portion of the n-type region and the annular peripheral portion of the n-type region. The method further includes forming a cathode of a Schottky diode, the cathode electrically contacting the annular peripheral portion of the n-type region. In some embodiments, the anode also contacts the annular shallow p-type region. In some embodiments, forming the n-type region includes: forming the central portion of the n-type region by a first ion implantation; and forming the remaining portion of the n-type region by a second ion implantation, the remaining portion including the annular n-type channel portion and the annular peripheral portion. In some embodiments, the method further includes forming an n-type buried layer at a depth deeper than the n-type region by ion implantation, wherein the n-type region contacts the n-type buried layer. In some embodiments, the method further includes forming an annular p-type region by ion implantation, the annular p-type region surrounding and contacting the annular buried p-type region. In some embodiments, the anode of the Schottky diode formed on the central portion of the n-type region includes forming an anode including a silicide layer on the central portion of the n-type region.

[0045] In a non-limiting illustrative embodiment, a Schottky diode includes: an n-type region; an anode of the Schottky diode located on the n-type region, with an interface between the anode and the n-type region including a Schottky barrier; a buried p-type region; and a shallow p-type region. An n-type channel portion of the n-type region is located between the buried p-type region and the shallow p-type region.

[0046] In some embodiments, the anode also contacts the annular shallow p-type region. In some embodiments, the Schottky diode further includes a cathode of the Schottky diode electrically in contact with the n-type region, wherein the n-type channel portion of the n-type region is configured to conduct current between the anode and cathode when the Schottky diode is forward biased, and to pinch off the current between the anode and cathode when the Schottky diode is reverse biased. In some embodiments, the buried p-type region is an annular buried p-type region disposed in the lower part of the n-type region; the shallow p-type region is an annular shallow p-type region disposed in the upper part of the n-type region; and the n-type channel portion of the n-type region connects the central portion of the n-type region and the annular peripheral portion of the n-type region, wherein the central portion is surrounded by the annular shallow p-type region, and the annular peripheral portion surrounds the annular shallow p-type region. In some embodiments, the Schottky diode further includes a cathode of the Schottky diode electrically in contact with the annular peripheral portion of the n-type region. In some embodiments, the Schottky diode further includes: an n-type buried layer located below the n-type region and below the annular buried p-type region, the n-type region being in contact with the n-type buried layer; and an annular p-type region surrounding and in contact with the annular buried p-type region. In some embodiments, the Schottky diode further includes a p-type substrate, wherein the n-type region, the buried p-type region, and the shallow p-type region are each implantation regions formed in the p-type substrate by ion implantation and include corresponding dopant distributions generated by ion implantation. In some embodiments, the anode of the Schottky diode includes a silicide layer disposed on the n-type region.

[0047] In a non-limiting illustrative embodiment, a buck converter includes an LC circuit comprising a sensor, a capacitor, a transistor, and at least one diode connected via a channel across the transistor. The at least one diode includes a Schottky diode comprising an n-type region, an anode of the Schottky diode disposed on the n-type region, a buried p-type region, and a shallow p-type region, wherein the interface between the anode and the n-type region includes a Schottky barrier. An n-type channel portion of the n-type region is located between the buried p-type region and the shallow p-type region.

[0048] In some embodiments, the buried p-type region of the Schottky diode is an annular buried p-type region disposed in the lower part of the n-type region; the shallow p-type region of the Schottky diode is an annular shallow p-type region disposed in the upper part of the n-type region; the n-type channel portion of the n-type region of the Schottky diode is located between the annular buried p-type region and the annular shallow p-type region; and the Schottky diode also includes a cathode of the Schottky diode, the cathode being electrically contacted with the annular peripheral portion of the n-type region. In some embodiments, the buck converter further includes: an n-type buried layer located below the n-type region and below the annular buried p-type region, and the n-type region contacting the n-type buried layer; and an annular p-type region surrounding and contacting the annular buried p-type region. In some embodiments, at least one diode connected across the channel of the transistor further includes a p / n junction diode connected in parallel with the Schottky diode. In some embodiments, the buck converter is an integrated circuit (IC).

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A Schottky diode, characterized in that, include: n-type region; The anode of the Schottky diode is located on the n-type region, and the interface between the anode and the n-type region includes a Schottky barrier; Burying the p-type area; and Shallow p-type region, The n-type channel portion of the n-type region is located between the buried p-type region and the shallow p-type region.

2. The Schottky diode according to claim 1, characterized in that, The anode also contacts the shallow p-type region.

3. The Schottky diode according to claim 1, characterized in that, Also includes: The cathode of the Schottky diode is in electrical contact with the n-type region. The n-type channel portion of the n-type region is configured to conduct current between the anode and the cathode when the Schottky diode is forward biased, and to cut off the current between the anode and the cathode when the Schottky diode is reverse biased.

4. The Schottky diode according to claim 1, characterized in that: The embedded p-type area is an annular embedded p-type area located in the lower part of the n-type area; The shallow p-type region is an annular shallow p-type region disposed in the upper part of the n-type region; and The n-shaped channel portion of the n-shaped region connects the central portion of the n-shaped region with the annular peripheral portion of the n-shaped region, wherein the central portion is surrounded by the annular shallow p-shaped region, and the annular peripheral portion surrounds the annular shallow p-shaped region.

5. The Schottky diode according to claim 4, characterized in that, Also includes: The cathode of the Schottky diode is in electrical contact with the annular peripheral portion of the n-type region.

6. The Schottky diode according to claim 4, characterized in that, Also includes: An n-type embedded layer is located below the n-type region and below the annular embedded p-type region, and the n-type region is in contact with the n-type embedded layer; as well as An annular p-shaped region surrounds and contacts the annular buried p-shaped region.

7. A buck converter, characterized in that, include: An LC circuit includes a sensor, a capacitor, a transistor, and at least one diode connected across a channel of the transistor. The at least one of the diodes includes a Schottky diode, the Schottky diode including an n-type region, an anode of the Schottky diode disposed on the n-type region, a buried p-type region, and a shallow p-type region, wherein the interface between the anode and the n-type region includes a Schottky barrier, and wherein the n-type channel portion of the n-type region is located between the buried p-type region and the shallow p-type region.

8. The buck converter according to claim 7, characterized in that: The embedded p-type region of the Schottky diode is an annular embedded p-type region disposed in the lower part of the n-type region; The shallow p-type region of the Schottky diode is an annular shallow p-type region disposed in the upper part of the n-type region; The n-type channel portion of the n-type region of the Schottky diode is located between the annular buried p-type region and the annular shallow p-type region; and The Schottky diode also includes a cathode, which is in electrical contact with the annular peripheral portion of the n-type region.

9. The buck converter according to claim 8, characterized in that, Also includes: An n-type embedded layer is located below the n-type region and below the annular embedded p-type region, and the n-type region is in contact with the n-type embedded layer; as well as An annular p-shaped region surrounds and contacts the annular buried p-shaped region.

10. The buck converter according to claim 8, characterized in that, The at least one diode connected across the channel of the transistor also includes a p / n junction diode connected in parallel with the Schottky diode.

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