Display substrate and display panel

Abstract

The embodiment of the utility model provides a display substrate and a display panel. The display substrate comprises a display area and a non-display area located outside the display area. The display substrate comprises a substrate; the plurality of thin film transistors are located in the non-display area and located on one side of the substrate; the first passivation layer is at least located in the non-display area and located on the side, away from the substrate, of the thin film transistor; the block-shaped structure is located in the non-display area and located on the side, away from the substrate, of the first passivation layer, the material of the block-shaped structure comprises a conductive material, and the orthographic projection of the block-shaped structure on the substrate comprises the orthographic projection of at least one thin film transistor on the substrate. According to the invention, when the first passivation layer has a crack, the block-shaped structure can cover the crack and protect the crack, so that bad conditions caused by invasion of water vapor or other gases are avoided.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display panel. Background Technology

[0002] In the field of display technology, a substrate is made by accumulating layers of film. An insulating layer is usually provided between two adjacent metal layers. In addition, a passivation layer is provided above the metal layers to protect the substrate and prevent moisture from penetrating into the substrate.

[0003] In related technologies, there is a problem of moisture or other gases penetrating into the substrate, causing product defects. Utility Model Content

[0004] This disclosure provides a display substrate and a display panel to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of the present disclosure, an embodiment of the present disclosure provides a display substrate, including a display area and a non-display area located outside the display area, the display substrate comprising:

[0006] Substrate;

[0007] Multiple thin-film transistors are located in the non-display area and on one side of the substrate;

[0008] The first passivation layer is located at least in the non-display area and on the side of the thin-film transistor away from the substrate;

[0009] A block structure is located in the non-display area and on the side of the first passivation layer away from the substrate. The block structure is made of a conductive material, and the orthogonal projection of the block structure onto the substrate includes the orthogonal projection of at least one thin-film transistor onto the substrate.

[0010] In some embodiments, the thin-film transistor includes a first thin-film transistor, the non-display area includes a plurality of driving unit areas, the driving unit areas are provided with a shift register, and the shift register includes a plurality of first thin-film transistors;

[0011] The bulk structure includes a first bulk pattern, and the orthographic projection of the first bulk pattern onto the substrate includes the orthographic projection of at least one first thin-film transistor onto the substrate.

[0012] In some embodiments, the drive unit area is provided with a plurality of first block patterns, and the plurality of first block patterns located in the same drive unit area are interconnected.

[0013] In some embodiments, the first block pattern is located in the driving unit region, and the orthographic projection of the first block pattern on the substrate includes the orthographic projection of the shift register on the substrate.

[0014] In some embodiments, each drive unit area is provided with a first block pattern, and the first block patterns of adjacent drive unit areas are spaced apart from each other.

[0015] In some embodiments, the orthographic projection of the first block pattern onto the substrate includes at least two adjacent drive unit regions.

[0016] In some embodiments, the thin-film transistor includes an electrostatic short-circuit ring, the block structure includes a second block pattern, and the orthographic projection of the second block pattern onto the substrate includes the orthographic projection of the electrostatic short-circuit ring onto the substrate.

[0017] In some embodiments, the display substrate further includes a first metal layer, a first insulating layer and a second metal layer disposed sequentially between the substrate and the first passivation layer. The display substrate includes a first metal pattern located on the first metal layer and a second metal pattern located on the second metal layer. The first insulating layer is provided with a first via located in a non-display area, and the second metal pattern is coupled to the first metal pattern through the first via.

[0018] The orthographic projection of the bulk structure onto the substrate also includes the orthographic projection of the first via onto the substrate.

[0019] In some embodiments, a first transparent conductive layer is further included on the side of the first passivation layer away from the substrate, and the block structure includes a first conductive block located on the first transparent conductive layer.

[0020] In some embodiments, the display substrate further includes a second passivation layer and a second transparent conductive layer, wherein the second passivation layer is located on the side of the first transparent conductive layer away from the substrate, and the second transparent conductive layer is located on the side of the second passivation layer away from the substrate. The block structure further includes a second conductive block located on the second transparent conductive layer.

[0021] In some embodiments, a third metal layer is further included, which is located on the side of the first transparent conductive layer away from the substrate, and the block structure further includes a third conductive block located on the third metal layer.

[0022] In some embodiments, the display substrate includes a first metal layer, a first insulating layer, a second metal layer, a first passivation layer, a first transparent conductive layer, a second passivation layer, and a second transparent conductive layer stacked sequentially, and the block structure includes a first conductive block located in the first transparent conductive layer;

[0023] The first metal layer includes a first metal pattern located in the non-display area, the second metal layer includes a second metal pattern located in the non-display area, and the second transparent conductive layer includes a transition line located in the non-display area.

[0024] The first conductive block has a cutout, and the non-display area has a second via and a third via. The second via penetrates the second passivation layer, the first passivation layer, and the first insulating layer. The orthographic projection of the second via on the substrate is located within the orthographic projection of the cutout on the substrate. The third via penetrates the second passivation layer and the first passivation layer. The orthographic projection of the third via on the substrate is located within the orthographic projection of the second cutout on the substrate. The adapter cable is coupled to the first metal pattern through the second via and to the second metal pattern through the third via.

[0025] In some embodiments,

[0026] The display substrate also includes common electrode lines located in the non-display area, with the block structure coupled to the common electrode lines; or...

[0027] The display substrate also includes a common ground trace located in the non-display area, and the block structure is coupled to the common ground trace.

[0028] As a second aspect of the present disclosure, the present disclosure provides a display panel including a display substrate according to any embodiment of the present disclosure.

[0029] The technical solution of this disclosure embodiment includes a block structure disposed above the first passivation layer. The block structure is made of conductive material, and its moisture protection performance is superior to that of the first passivation layer. It is understood that a thin-film transistor includes a source and a drain. When cracks appear in the first passivation layer above the source and drain, the block structure located above the first passivation layer can cover the cracks, protecting them and preventing moisture or other gases from entering the display substrate through the cracks and causing defects, thereby improving the performance of the display substrate.

[0030] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0031] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0032] Figure 1 This is a planar schematic diagram of a display substrate in the related art;

[0033] Figure 2 for Figure 1 A schematic diagram of section A1-A1 in the diagram;

[0034] Figure 3for Figure 1 Schematic diagram of section B1-B1 in the diagram;

[0035] Figure 4 This is a plan view of a display substrate according to an embodiment of the present disclosure;

[0036] Figure 5 for Figure 4 A schematic cross-sectional view of the display substrate along line A2-A2 in one embodiment;

[0037] Figure 6 This is a plan view of the display substrate in yet another embodiment of the present disclosure;

[0038] Figure 7 This is a plan view of the display substrate in yet another embodiment of the present disclosure;

[0039] Figure 8 for Figure 7 A schematic diagram of the B2-B2 cross section of the display substrate in one embodiment;

[0040] Figure 9 This is a schematic diagram of an electrostatic ring circuit;

[0041] Figure 10 This is a plan view of the display substrate in yet another embodiment of the present disclosure;

[0042] Figure 11 for Figure 4 A schematic cross-sectional view of the display substrate along line A2-A2 in another embodiment;

[0043] Figure 12 for Figure 7 A schematic diagram of the B2-B2 cross section of the display substrate in another embodiment;

[0044] Figure 13 for Figure 4 A schematic cross-sectional view of the display substrate along line A2-A2 in another embodiment;

[0045] Figure 14 for Figure 7 A schematic diagram of the B2-B2 cross section of the display substrate in another embodiment;

[0046] Figure 15 This is a schematic diagram of the manufacturing process of the display substrate in one embodiment;

[0047] Figure 16 This is a schematic diagram of the manufacturing process of the display substrate in another embodiment;

[0048] Figure 17 This is a schematic diagram of the manufacturing process of the display substrate in yet another embodiment;

[0049] Figure 18This is a schematic diagram of the manufacturing process of the display substrate in another embodiment;

[0050] Figure 19 This is a plan view of the display substrate in yet another embodiment of the present disclosure;

[0051] Figure 20 This is a plan view of the display substrate in another embodiment of the present disclosure;

[0052] Figure 21 for Figure 19 or Figure 20 An enlarged schematic diagram of part C in the diagram;

[0053] Figure 22 for Figure 21 A schematic diagram of the DD section.

[0054] Explanation of reference numerals in the attached figures:

[0055] 1. Display substrate; 2. Common electrode area; 3. Driving unit area; 4. Display area; 7. Block structure; 71. First block pattern; 711. Hollowed-out; 72. Second block pattern;

[0056] 11. Substrate; 12. First metal layer; 121. Gate; 122. First metal pattern; 153. Second metal pattern; 13. First insulating layer; 14. Active layer; 15. Second metal layer; 154. Common ground line; 16. First passivation layer; 17. Organic layer; 18. Second passivation layer;

[0057] 191. First transparent conductive layer; 1911. First conductive block; 192. Second transparent conductive layer; 1921. Second conductive block; 1922. Adapter line; 193. Third metal layer; 1931. Third conductive block. Detailed Implementation

[0058] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure, and different embodiments can be combined arbitrarily without conflict. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0059] It should be noted that, for example, 153-15 in the accompanying drawings of this disclosure indicates that component 153 belongs to component 15, and that the second metal pattern 153 belongs to the second metal layer 15. Other similar reference numerals in the drawings also follow the above description. For example, 71 / 72 in the accompanying drawings of this disclosure indicates component 71 or component 72. For example, 71 / 72 in the drawings indicates the first block pattern 71 or the first block pattern 72. Therefore, 1911-71 / 72 in the drawings indicate that the first conductive block 1911 belongs to the first block pattern 71, or that the first conductive block 1911 belongs to the second block pattern 72.

[0060] Figure 1 This is a planar schematic diagram of a display substrate in related technologies. Figure 2 for Figure 1 A schematic diagram of section A1-A1 in the diagram. Figure 3 for Figure 1 A schematic diagram of section B1-B1 in the diagram. (See diagram below.) Figures 1-3 As shown, the display substrate 1 includes a display area 4 and a non-display area located outside the display area 4. The non-display area includes a common electrode area 2 and a driving unit area 3. Typically, the common electrode area 2 surrounds the display area 4, and the driving unit area 3 is located outside the common electrode area 2. The common electrode area 2 is provided with common electrode lines. The driving unit area 3 can be called the GOA area, and it is provided with multiple thin-film transistors and may also have vias. Figure 1 The two GOA areas are indicated by dashed boxes. It can be understood that the non-display area includes multiple driver unit areas 3, which can be located to the left and / or right of the display area 4. The non-display area also includes a bonding area 6, used for bonding and connecting the driver chip.

[0061] In related technologies, such as Figure 2As shown, in the driving unit region 3, the display substrate 1 includes a first metal layer 12, a first insulating layer 13, an active layer 14, a second metal layer 15, a first passivation layer 16, an organic layer 17, and a second passivation layer 18, which are sequentially stacked on a substrate 11. The first metal layer 12 includes a gate 121, and the second metal layer 15 includes a source 151 and a drain 152. The source 151 and drain 152 are typically arranged in the form of a metal pattern, and the side edge 151a of the metal pattern has a certain slope angle relative to the surface of the underlying film layer (i.e., the angle between the side edge of the metal pattern and the surface of the substrate 11). Through actual testing, the inventors discovered that after the first passivation layer 16 is formed above the second metal layer 15, due to the slope angle of the side edge 151a, especially when the slope angle is relatively large or the slope angle is a chamfered angle, the first passivation layer 16 has poor coverage of the second metal layer 15, and even cracks F1 appear above the side edge 151a, causing water vapor or other gases to enter the substrate through the cracks, contaminating the thin film transistor, affecting the characteristics of the thin film transistor, and causing defects.

[0062] like Figure 3 As shown, the drive unit area 3 is also provided with a first via K1. The second metal layer 15 includes a second metal pattern 153, and the first metal layer 12 includes a first metal pattern 122. The second metal pattern 153 is coupled to the first metal pattern 122 through the first via K1 penetrating the first insulating layer 13. The upper surface of the second metal pattern 153 forms an inclined sidewall 153a with a slope angle at the edge of the first via K1. After the first passivation layer 16 is formed, cracks F2 are prone to appear above the inclined sidewall 153a in the first passivation layer 16, causing water vapor or other gases to contaminate the film layer at the via location through the cracks, affecting the connectivity of the metal pattern at the location of the first via K1, resulting in defects.

[0063] It should be noted that the aspect ratio of the metal pattern can be set as needed. When the aspect ratio of the metal pattern is similar or the same, the metal pattern can be called a metal block. When the aspect ratio of the metal pattern is large, the metal pattern is long and narrow, and the metal pattern can be called a metal trace. The shape of the metal trace can be straight, broken, or curved.

[0064] To address the issue of defects caused by cracks in the first passivation layer, this disclosure provides a display substrate.

[0065] Figure 4 This is a plan view of a display substrate according to an embodiment of the present disclosure. Figure 5 for Figure 4 A schematic cross-sectional view of the display substrate along line A2-A2 in one embodiment. (See diagram below.) Figure 4 and Figure 5As shown, the display substrate 1 includes a display area 4 and a non-display area located outside the display area 4. The display substrate 1 includes a substrate 11 and a plurality of thin-film transistors, which are located in the non-display area and on one side of the substrate 11. The thin-film transistors may include a gate 121, an active layer 14, a source 151, and a drain 152.

[0066] The display substrate 1 also includes a first passivation layer 16 and a bulk structure 7. The first passivation layer 16 is located at least in the non-display area and on the side of the thin-film transistor facing away from the substrate 11. Figure 5 In this structure, multiple thin-film transistors are located on the upper side of the substrate 11, and a first passivation layer 16 is located on the upper side of the thin-film transistors. A block structure 7 is located in the non-display area and on the side of the first passivation layer 16 facing away from the substrate 11, i.e., the block structure 7 is located on the upper side of the first passivation layer 16. The block structure 7 is made of a conductive material, and its orthographic projection onto the substrate 11 includes the orthographic projection of at least one thin-film transistor onto the substrate 11; that is, the block structure 7 covers the first passivation layer 16 above at least one thin-film transistor.

[0067] It is understandable that the material of the first passivation layer 16 typically includes at least one of silicon nitride, silicon oxide, and silicon oxynitride. The moisture protection performance of this first passivation layer 16 is weaker than that of conductive materials such as metals or indium tin oxide (ITO) and indium zinc oxide (IZO). In other words, the moisture protection performance of conductive materials is superior to that of the first passivation layer 16. That is, the moisture protection performance of the bulk structure 7 is superior to that of the first passivation layer 16.

[0068] The technical solution disclosed herein includes a block structure 7 disposed above the first passivation layer 16. The block structure 7 is made of conductive material, and its moisture protection performance is superior to that of the first passivation layer 16. It is understood that a thin-film transistor includes a source and a drain. When cracks appear in the first passivation layer 16 above the source and drain, the block structure 7 located above the first passivation layer 16 can cover the cracks, protecting them and preventing moisture or other gases from entering the display substrate 1 through the cracks and causing defects, thereby improving the performance of the display substrate 1.

[0069] In one embodiment, such as Figure 4 and Figure 5 As shown, the thin-film transistor may include a first thin-film transistor. The non-display area includes multiple driving unit areas 3, and each driving unit area 3 is equipped with a shift register, which includes multiple first thin-film transistors. Here, the type of each first thin-film transistor in the shift register is not limited; its type can be set as needed. Each thin-film transistor in the shift register is referred to as a first thin-film transistor.

[0070] The block structure 7 includes a first block pattern 71, the orthographic projection of the first block pattern 71 onto the substrate 11 including the orthographic projection of at least one first thin-film transistor onto the substrate 11. That is, the first block pattern 71 is located above the first passivation layer 16 and covers the first passivation layer 16 above at least one first thin-film transistor.

[0071] The shift register is used to provide drive signals to the display area 4. If the first thin-film transistor in the shift register is contaminated by moisture or gas, it will affect the performance of the first thin-film transistor, and thus affect the performance of the shift register. By setting a first block pattern 71, and the first block pattern 71 covering the first passivation layer 16 above at least one first thin-film transistor, the first block pattern 71 can protect the first passivation layer 16 above the first thin-film transistor from cracks, preventing moisture or other gases from entering the first thin-film transistor through the cracks, thereby improving the performance of the shift register and thus improving the performance of the display substrate 1.

[0072] Viewed from a direction perpendicular to substrate 11, as Figure 4 As shown, the first block pattern 71 can be a continuous pattern, so that the first block pattern 71 can completely cover the first passivation layer 16 above at least one first thin film transistor, ensuring that the first block pattern 71 can cover the cracks that appear in the first passivation layer 16 and protect the cracks.

[0073] The driving unit region 3 is provided with multiple first thin-film transistors. The material of the first block pattern 71 includes conductive materials. If the area of ​​the first block pattern 71 is too large, it is easy to cause electrostatic discharge (ESD) risk. Figure 4 In this embodiment, the driving unit region 3 may be provided with a plurality of first block patterns 71, each first block pattern 71 may cover the first passivation layer 16 above at least one first thin film transistor. This reduces the area of ​​the first block patterns 71 in the driving unit region 3 and avoids the ESD risk introduced by the accumulation of large-area conductors.

[0074] Furthermore, multiple first block patterns 71 located in the same driving unit region 3 are interconnected, for example, every two adjacent first block patterns 71 are connected by a first connecting line 711. This connects the multiple first block patterns 71 in the same driving unit region 3 into a single unit, ensuring that the potentials of the multiple first block patterns 71 in the same driving unit region 3 are the same, thus preventing electrical coupling caused by different potentials between adjacent first block patterns 71. The first connecting line 711 can be disposed on the same layer as the first block pattern 71, thereby forming a single structure with the connected first block pattern 71.

[0075] Figure 6This is a plan view of a display substrate according to yet another embodiment of the present disclosure. In another embodiment, as... Figure 6 As shown, the first block pattern 71 is located in the driving unit region 3, and the orthographic projection of the first block pattern 71 on the substrate 11 includes the orthographic projection of the shift register on the substrate 11. That is, the orthographic projection of the first block pattern 71 on the substrate 11 includes the orthographic projection of all the first thin-film transistors in the shift register on the substrate 11. For example, each driving unit region 3 is provided with a first block pattern 71, and the first block pattern 71 can cover the first passivation layer 16 above all the first thin-film transistors in the corresponding shift register. Figure 6 Compared to the example Figure 4 In this embodiment, the area of ​​the first block pattern 71 is increased, and such a first block pattern 71 can protect all the first thin-film transistors in the shift register. Figure 6 The schematic diagram of section A3-A3 can be referenced. Figure 5 .

[0076] To protect each shift register, each drive unit can be configured with a first block pattern 71, such as... Figure 6 As shown, the first block patterns 71 of adjacent drive unit areas 3 can be spaced apart from each other, that is, the first block patterns 71 of adjacent drive unit areas 3 are not connected. Alternatively, in another embodiment, the first block patterns 71 of adjacent drive unit areas 3 can be connected by a second connecting line.

[0077] Figure 7 This is a plan view of the display substrate in another embodiment of the present disclosure. In another embodiment, such as... Figure 7 As shown, the orthographic projection of the first block pattern 71 onto the substrate 11 may include at least two adjacent driving unit regions 3. Figure 7 Compared to the example Figure 6 In this embodiment, the area of ​​the first block pattern 71 is increased. The display substrate 1 typically has multiple driving unit regions 3 on both the left and right sides of the display area 4. Therefore, a first block pattern 71a and a first block pattern 71b can be respectively provided on the left and right sides of the display area 4. The orthographic projection of the first block pattern 71a on the left side onto the substrate 11 can include the multiple driving unit regions 3 on the left, and the orthographic projection of the first block pattern 71b on the right side onto the substrate 11 can include the multiple driving unit regions 3 on the right. Figure 7 As shown.

[0078] Figure 8 for Figure 7 A schematic diagram of the B2-B2 cross-section of the display substrate in one embodiment, as shown below. Figure 8As shown, the display substrate 1 includes a first metal layer 12, a first insulating layer 13, and a second metal layer 15 sequentially disposed between a substrate 11 and a first passivation layer 16. The display substrate 1 also includes a first metal pattern 122 located on the first metal layer 12 and a second metal pattern 153 located on the second metal layer 15. Both the first metal pattern 122 and the second metal pattern 153 are located in the non-display area. The first insulating layer 13 is provided with a first via K1 located in the non-display area, and the second metal pattern 153 is coupled to the first metal pattern 122 through the first via K1. The orthogonal projection of the block structure 7 onto the substrate 11 also includes the orthogonal projection of the first via K1 onto the substrate 11; that is, the block structure 7 covers the first passivation layer 16 above the first via K1. To improve the conductivity of the first metal pattern 122 and the second metal pattern 153, multiple consecutive first vias K1 are typically provided. When the number of first vias K1 is multiple, the first block pattern 71 can cover the first passivation layer 16 above the multiple consecutive first vias K1.

[0079] Through the Figure 3 Analysis shows that the first passivation layer 16 above the first via K1 is also prone to cracks. The first block pattern 71 covers the first passivation layer 16 above the first via K1, which can protect the cracks that appear in the first passivation layer 16 above the first via K1 and prevent moisture and other gases from entering the display substrate 1 through the cracks.

[0080] According to the circuit diagram of the shift register in the prior art, there is a thin-film transistor in the shift register whose gate is connected to the source or drain. Therefore, the first via can be set in the driving unit area.

[0081] In the display substrate, an electrostatic discharge ring circuit can be set in the non-display area for electrostatic discharge. Figure 9 This is a schematic diagram of an electrostatic ring circuit, which includes an electrostatic short-circuit ring 200. Figure 9 The electrostatic ring circuit in the diagram includes electrostatic short-circuit ring 200a and electrostatic short-circuit ring 200b. From... Figure 9 As can be seen, the electrostatic short-circuit ring 200 uses a thin-film transistor, and in the thin-film transistor of the electrostatic short-circuit ring 200, the source or drain is connected to the gate 121. Each film layer in the electrostatic short-circuit ring 200 is disposed in the same layer as each film layer in the first thin-film transistor. Therefore, the first passivation layer 16 above the electrostatic short-circuit ring is also prone to cracks.

[0082] Figure 10 This is a plan view of the display substrate in another embodiment of the present disclosure, as shown below. Figure 10As shown, the block structure 7 includes a second block pattern 72. The orthographic projection of the second block pattern 72 onto the substrate 11 includes the orthographic projection of the electrostatic short-circuit ring onto the substrate 11. That is, the second block pattern 72 covers the first passivation layer 16 above the electrostatic short-circuit ring. Thus, when a crack appears in the first passivation layer 16 above the electrostatic short-circuit ring, the second block pattern 72 can protect the crack, preventing moisture and other gases from entering the display substrate 1 through the crack.

[0083] Typically, electrostatic short-circuit rings are provided on the left, right, top, and bottom sides of display area 4. Second block patterns 72a, 72b, 72c, and 72d can be respectively provided on the left, right, top, and bottom sides of display area 4. Figure 10 As shown. The second block pattern 72a can be connected with the first block pattern 71a to form a whole, and the second block pattern 72b can be connected with the first block pattern 71b to form a whole.

[0084] from Figure 9 As can be seen, in the thin-film transistor with the electrostatic short-circuit ring, the source or drain is connected to the gate. Therefore, the first via can also be set in the area where the electrostatic short-circuit ring is located. The specific location of the first via can be set in the non-display area as needed.

[0085] The block structure 7 is composed of membrane layers. In one embodiment, such as... Figure 5 and Figure 8 As shown, the display substrate 1 further includes a first transparent conductive layer 191, which is located on the side of the first passivation layer 16 facing away from the substrate 11. For example, the display substrate 1 may also include an organic layer 17, which is located on the side of the first passivation layer 16 facing away from the substrate 11, and the first transparent conductive layer 191 may be located on the side of the organic layer 17 facing away from the substrate 11. The block structure 7 includes a first conductive block 1911 located in the first transparent conductive layer 191; that is, the first conductive block 1911 is a block pattern in the first transparent conductive layer 191. The material of the first transparent conductive layer 191 may include a transparent conductive material, such as at least one of ITO, IZO, etc.

[0086] Figure 11 for Figure 4 A schematic diagram of the A2-A2 cross section of the display substrate in another embodiment. Figure 12 for Figure 7 A schematic diagram of the B2-B2 cross-section of the display substrate in another embodiment, as shown below. Figure 11 and Figure 12As shown, the display substrate 1 may further include a second passivation layer 18 and a second transparent conductive layer 192. The second passivation layer 18 is located on the side of the first transparent conductive layer 191 facing away from the substrate 11. The second transparent conductive layer 192 is located on the side of the second passivation layer 18 facing away from the substrate 11. The block structure 7 may further include a second conductive block 1921 located on the second transparent conductive layer 192. Thus, the first conductive block 1911 and the second conductive block 1921, which are stacked, simultaneously cover the first passivation layer 16 above at least one thin-film transistor. When a crack appears in the first passivation layer 16, the first conductive block 1911 and the second conductive block 1921 simultaneously protect the crack, which can better prevent moisture or other gases from entering the display substrate 1 through the crack.

[0087] The material of the second transparent conductive layer 192 may include a transparent conductive material, such as at least one of ITO, IZO, etc.

[0088] Figure 13 for Figure 4 A schematic diagram of the A2-A2 cross section of the display substrate in another embodiment. Figure 14 for Figure 7 A schematic diagram of the B2-B2 cross-section of the display substrate in another embodiment, as shown below. Figure 13 and Figure 14 As shown, the display substrate 1 may further include a third metal layer 193, which is located on the side of the first transparent conductive layer 191 facing away from the substrate 11. Exemplarily, the third metal layer 193 may be located between the first transparent conductive layer 191 and the second passivation layer 18. The block structure 7 may further include a third conductive block 1931 located within the third metal layer 193. In this structure, the first conductive block 1911 and the third conductive block 1931, arranged in a stack, simultaneously cover the first passivation layer 16 above at least one thin-film transistor. When a crack appears in the first passivation layer 16, the first conductive block 1911 and the third conductive block 1931 simultaneously protect the crack, better preventing moisture or other gases from entering the display substrate 1 through the crack.

[0089] In one embodiment, the block structure 7 may include a first conductive block 1911, a third conductive block 1931, and a second conductive block 1921.

[0090] For example, the block structure 7 may include a first block pattern 71 and a second block pattern 72, the first conductive block 1911 may include a first sub-block and a second sub-block, the second conductive block 1921 may include a third sub-block and a fourth sub-block, and the third conductive block 1931 may include a fifth sub-block and a sixth sub-block. Correspondingly, the first block pattern 71 may include a first sub-block, a fifth sub-block, and a third sub-block, and the second block pattern 72 may include a second sub-block, a sixth sub-block, and a fourth sub-block.

[0091] Figure 15 This is a schematic diagram of the manufacturing process of the display substrate in one embodiment. Figure 16 This is a schematic diagram of the manufacturing process of the display substrate in another embodiment. (Reference) Figure 11 and Figure 12 The display substrate may include a first metal layer (M1), a first insulating layer (GI), an active layer, a second metal layer (M2), a first passivation layer (PVX1), an organic layer (Resin), a first transparent conductive layer (1st ITO), a second passivation layer (PVX2), and a second transparent conductive layer (2nd ITO), stacked sequentially. Each of the first metal layer, first insulating layer, active layer, second metal layer, organic layer, first transparent conductive layer, and second transparent conductive layer uses a mask, while the first passivation layer and second passivation layer use a single mask and are etched simultaneously. In other words, the display substrate uses eight masks to form the patterns of each film layer, such as... Figure 15 As shown. When a third metal layer (M3) is disposed between the first transparent conductive layer and the second passivation layer, the third metal layer uses a mask. That is, the display substrate uses 9 masks to form the pattern of each film layer, as shown. Figure 16 As shown.

[0092] Figure 17 This is a schematic diagram of the manufacturing process of the display substrate in yet another embodiment. Figure 18 This is a schematic diagram of the manufacturing process of the display substrate in another embodiment. Figure 17 Compared to Figure 15 The first insulating layer no longer uses a separate mask; instead, the first insulating layer, the first passivation layer, and the second passivation layer all use the same mask and are etched simultaneously. Therefore... Figure 17 In this process, the display substrate uses 7 masks to form the pattern of each film layer. Figure 17 The manufacturing process shown is compared to Figure 15 Reducing the number of masks lowers the cost.

[0093] Figure 18 Compared to Figure 16 The first insulating layer no longer uses a separate mask; instead, the first insulating layer, the first passivation layer, and the second passivation layer all use the same mask and are etched simultaneously. Therefore... Figure 18 In this process, the display substrate uses 8 masks to form the pattern of each film layer. Figure 18 The manufacturing process shown is compared to Figure 16 Reducing the number of masks lowers the cost.

[0094] When using Figure 17 or Figure 18 When referring to the manufacturing process shown, please refer to... Figure 12 and Figure 14Since the first via cannot be formed independently, the second metal pattern cannot be connected to the first metal pattern through the first via.

[0095] Figure 19 This is a plan view of the display substrate according to yet another embodiment of the present disclosure. Figure 20 This is a plan view of the display substrate in another embodiment of the present disclosure. Figure 21 for Figure 19 or Figure 20 An enlarged diagram of part C in the diagram. Figure 22 for Figure 21 A schematic diagram of the DD section in the figure, as shown below. Figures 19-22 As shown, the display substrate 1 includes a first metal layer 12, a first insulating layer 13, a second metal layer 15, a first passivation layer 16, a first transparent conductive layer 191, a second passivation layer 18, and a second transparent conductive layer 192, which are stacked sequentially. These layers are all located in the non-display area, but may also be located in the display area 4. The block structure 7 includes a first conductive block 1911 located in the first transparent conductive layer 191.

[0096] The first metal layer 12 includes a first metal pattern 122 located in the non-display area, the second metal layer 15 includes a second metal pattern 153 located in the non-display area, and the second transparent conductive layer 192 includes a transition line 1922 located in the non-display area.

[0097] The first conductive block 1911 can be configured with a cutout LK. The non-display area has a second via K2 and a third via K3. The second via K2 penetrates the second passivation layer 18, the first passivation layer 16, and the first insulating layer 13. The orthographic projection of the second via K2 on the substrate 11 lies within the orthographic projection of the cutout LK on the substrate 11. The third via K3 penetrates the second passivation layer 18 and the first passivation layer 16. The orthographic projection of the third via K3 on the substrate 11 lies within the orthographic projection of the second cutout LK on the substrate 11. The adapter cable 1922 is coupled to the first metal pattern 122 through the second via K2 and to the second metal pattern 153 through the third via K3.

[0098] exist Figure 22In this embodiment, to achieve the connection between the second metal patterns 153, the first insulating layer 13, the first passivation layer 16, and the second passivation layer 18 are etched simultaneously to form the second via K2 and the third via K3, respectively. Then, when forming the second transparent conductive layer 192, a transition line 1922 is formed, so that the transition line 1922 is coupled to the first metal pattern 122 through the second via K2 and to the second metal pattern 153 through the third via K3. To avoid the first conductive block 1911 affecting the etching of the second via K2 and the third via K3, the first conductive block 1911 is provided with a cutout LK. The orthographic projections of the second via K2 and the third via K3 on the substrate 11 are both located within the orthographic projection of the cutout LK on the substrate 11, so that the first conductive block 1911 avoids the second via K2 and the third via K3.

[0099] Since the block structure 7 is made of a conductive material, when the block structure 7 is in a floating state, adjacent block structures 7 may have different voltages, potentially causing coupling voltage between them and affecting the performance of the display substrate 1. In one embodiment, the non-display area includes a common electrode area 2, which can be arranged around the display area 4, with the driving unit area 3 located outside the common electrode area 2. The common electrode area 2 is provided with a common electrode line, and the block structure 7 is coupled to the common electrode line. Thus, the common electrode line can provide a common voltage to the block structure 7, ensuring a stable common voltage and preventing the block structure 7 from accumulating other charges due to its floating state, which could cause malfunctions. As can be seen from the above schematic diagram of the display substrate 1, as... Figure 6 and Figure 7 As shown, the first block pattern 71 is coupled to the common electrode line through the fourth via K4 located in the common electrode region 2.

[0100] For example, the common electrode line can be located in the second metal layer 15, the fourth via K4 can penetrate the first passivation layer 16 and the organic layer 17, and the first conductive block 1911 in the first block pattern 71 can be coupled to the common electrode line through the fourth via K4. The second conductive block 1921 can be coupled to the first conductive block 1911 through a via (not shown in the figure) penetrating the second passivation layer 18.

[0101] In another embodiment, such as Figure 10As shown, the display substrate 1 may include a common ground trace 154 located in the non-display area, and the block structure 7 may be coupled to the common ground trace 154. For example, the display substrate 1 includes a bonding area 6 located in the non-display area, which is used to bond and connect a driver chip. The bonding area 6 is provided with a GND solder pad, and the common ground trace 154 is coupled to the GND solder pad through a metal interconnect 9. The block structure 7 is coupled to the common ground trace 154 through a fifth via K5. Exemplarily, the common ground trace 154 may be located in the second metal layer 15, and the fifth via K5 may penetrate the first passivation layer 16 and the organic layer 17. The first conductive block 1911 in the first block pattern 71 may be coupled to the common ground trace 154 through the fifth via K5. The second block pattern 72 may be coupled to the first block pattern 71.

[0102] In one embodiment, the display substrate can be an array substrate in a liquid crystal display panel. The array substrate includes a pixel electrode layer and a common electrode layer in the display area. The common electrode layer can be located on a first transparent conductive layer; that is, the first conductive block is disposed on the same layer as the common electrode layer. Therefore, the placement of the first conductive block does not increase the number of masks on the array substrate, nor does it increase cost. The pixel electrode layer can be located on a second transparent conductive layer; that is, the second conductive block is disposed on the same layer as the pixel electrode layer. Therefore, the placement of the second conductive block does not increase the number of masks on the array substrate, nor does it increase cost. The third metal layer can also include a pattern located in the display area; therefore, the placement of the third conductive block does not increase the number of masks on the display substrate, nor does it increase cost. Thus, this disclosure provides a block structure in the non-display area, which can protect against cracks generated by the first passivation layer, preventing moisture or other gases from intruding into the display substrate and causing defects, without increasing cost.

[0103] In an exemplary embodiment, the first insulating layer, the first passivation layer, and the second passivation layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. The first metal layer, the second metal layer, and the third metal layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0104] Based on the inventive concept of the foregoing embodiments, this disclosure also provides a display panel, which includes a display substrate using the foregoing embodiments. The display panel may include a liquid crystal display panel. When the display panel is a liquid crystal display panel, it further includes a color filter substrate, which is disposed opposite to the display substrate, with a liquid crystal layer located between the display substrate and the color filter substrate. The display panel is not limited to a liquid crystal display panel, but may also be other types of display panels, such as an OLED (organic light-emitting diode) display panel.

[0105] The display panel can be any product or component with a display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0106] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0107] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0108] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0109] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0110] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0111] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure. Different parts of different embodiments can be combined with each other without conflict, and these should all be covered within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, The display substrate includes a display area and a non-display area located outside the display area. Substrate; Multiple thin-film transistors are located in the non-display area and on one side of the substrate; A first passivation layer is located at least in the non-display area and on the side of the thin-film transistor facing away from the substrate; A block structure is located in the non-display area and on the side of the first passivation layer opposite to the substrate. The block structure is made of a conductive material, and the orthogonal projection of the block structure onto the substrate includes the orthogonal projection of at least one of the thin-film transistors onto the substrate.

2. The display substrate according to claim 1, characterized in that, The thin-film transistor includes a first thin-film transistor, the non-display area includes multiple driving unit areas, the driving unit areas are provided with a shift register, and the shift register includes multiple first thin-film transistors; The block structure includes a first block pattern, and the orthographic projection of the first block pattern onto the substrate includes the orthographic projection of at least one of the first thin-film transistors onto the substrate.

3. The display substrate according to claim 2, characterized in that, The driving unit area is provided with a plurality of the first block patterns, and the plurality of the first block patterns located in the same driving unit area are connected to each other.

4. The display substrate according to claim 2, characterized in that, The first block pattern is located in the driving unit area, and the orthographic projection of the first block pattern on the substrate includes the orthographic projection of the shift register on the substrate.

5. The display substrate according to claim 4, characterized in that, Each of the driving unit areas is provided with the first block pattern, and the first block patterns of adjacent driving unit areas are spaced apart from each other.

6. The display substrate according to claim 2, characterized in that, The orthographic projection of the first block pattern onto the substrate includes at least two adjacent drive unit regions.

7. The display substrate according to claim 1, characterized in that, The thin-film transistor includes an electrostatic short-circuit ring, and the block structure includes a second block pattern, the orthographic projection of the second block pattern on the substrate including the orthographic projection of the electrostatic short-circuit ring on the substrate.

8. The display substrate according to claim 1, characterized in that, The display substrate further includes a first metal layer, a first insulating layer and a second metal layer sequentially disposed between the substrate and the first passivation layer. The display substrate includes a first metal pattern located on the first metal layer and a second metal pattern located on the second metal layer. The first insulating layer is provided with a first via located in the non-display area, and the second metal pattern is coupled to the first metal pattern through the first via. The orthogonal projection of the block structure onto the substrate also includes the orthogonal projection of the first via onto the substrate.

9. The display substrate according to any one of claims 1-8, characterized in that, It also includes a first transparent conductive layer located on the side of the first passivation layer opposite to the substrate, and the block structure includes a first conductive block located on the first transparent conductive layer.

10. The display substrate according to claim 9, characterized in that, The display substrate further includes a second passivation layer and a second transparent conductive layer. The second passivation layer is located on the side of the first transparent conductive layer that is away from the substrate, and the second transparent conductive layer is located on the side of the second passivation layer that is away from the substrate. The block structure also includes a second conductive block located on the second transparent conductive layer.

11. The display substrate according to claim 9, characterized in that, It also includes a third metal layer located on the side of the first transparent conductive layer away from the substrate, and the block structure also includes a third conductive block located on the third metal layer.

12. The display substrate according to any one of claims 1-7, characterized in that, The display substrate includes a first metal layer, a first insulating layer, a second metal layer, a first passivation layer, a first transparent conductive layer, a second passivation layer, and a second transparent conductive layer stacked sequentially, and the block structure includes a first conductive block located in the first transparent conductive layer; The first metal layer includes a first metal pattern located in the non-display area, the second metal layer includes a second metal pattern located in the non-display area, and the second transparent conductive layer includes a transition line located in the non-display area; The first conductive block has a cutout, and the non-display area has a second via and a third via. The second via penetrates the second passivation layer, the first passivation layer, and the first insulating layer. The orthographic projection of the second via on the substrate is located within the orthographic projection of the cutout on the substrate. The third via penetrates the second passivation layer and the first passivation layer. The orthographic projection of the third via on the substrate is located within the orthographic projection of the cutout on the substrate. The adapter cable is coupled to the first metal pattern through the second via and to the second metal pattern through the third via.

13. The display substrate according to any one of claims 1-8, characterized in that, The display substrate further includes a common electrode line located in the non-display area, and the block structure is coupled to the common electrode line; or... The display substrate also includes a common ground trace located in the non-display area, and the block structure is coupled to the common ground trace.

14. A display panel, characterized in that, The display substrate includes any one of claims 1-13.

Images