Control circuit of APF (Active Power Filter) device based on dual-frequency inversion driving

Abstract

The utility model provides an APF active filtering device control circuit based on double-frequency inversion driving, which comprises a double-frequency inversion driving module, a pulse width modulation module and a control interface module, and is characterized in that the double-frequency inversion driving module comprises a plurality of groups of inversion units and is used for generating double-frequency inversion driving signals; and the pulse width modulation module inputs the filtered driving signal into a PWM control chip through an RC filter network circuit, and after modulation, the driving signal is connected with a signal port IOIGBTA of the control interface module through an OUT pin and then is output to the dual-frequency inversion driving module, so that accurate control of the APF main circuit is completed. According to the utility model, the multi-channel PWM control chip in the pulse width modulation module is matched with the protection design of the RC filter network circuit and the BAV99 diode, so that the accurate pulse width modulation of the driving signal is realized, the tracking and compensation precision of the APF device on the harmonic current is improved, the harmonic wave of the power grid is effectively inhibited, and the stable operation of the power system is ensured.

Description

Technical Field

[0001] This utility model relates to the field of dual-frequency inverter drive circuit control technology, specifically to the control circuit of APF active filter device based on dual-frequency inverter drive. Background Technology

[0002] With the widespread application of industrial automation and nonlinear loads, harmonic pollution in power grids has intensified. Active power filters (APFs), as key equipment for power quality compensation, urgently require breakthroughs in their control circuit technology.

[0003] Traditional APF control circuits have multiple drawbacks:

[0004] First, the control precision and stability are insufficient. Based on the existing technology, it is difficult to accurately control the output pulse width and frequency of the inverter, resulting in harmonic compensation error. It is unable to effectively track rapidly changing harmonic components, and the anti-interference performance is poor. It is susceptible to electromagnetic interference from the power grid, which causes the control signal to be distorted, leading to unstable output or even equipment damage.

[0005] Secondly, the integration and modularity are low. Using existing discrete components makes the circuit structure complex and bulky. At the same time, the electrical connections are complex when multiple modules are running in tandem, the signals are easily interfered with, the power distribution and synchronous control are affected, and the performance of large-capacity expansion and multi-machine parallel connection is restricted.

[0006] Third, the dynamic response speed is lagging. Traditional control circuits have response delays and overshoots when there are grid faults and sudden load changes. They cannot adjust the inverter output in time to compensate for harmonic currents, which leads to problems such as voltage dips and rises in the grid, affecting the continuity of power supply.

[0007] Fourth, the isolation and protection of the control and drive circuits are defective. The lack of effective electrical isolation leads to significant interference, which not only affects the accuracy of the signal but also makes the control chip susceptible to damage from high voltage surges, posing a risk of signal transmission distortion and false triggering.

[0008] In summary, existing APF control circuits have significant shortcomings in terms of control accuracy, anti-interference capability, integration, dynamic response, and isolation protection, making it difficult to meet the high-performance requirements of modern power systems for power quality management. There is an urgent need to develop control circuits for APF active filter devices based on dual-frequency inverter drive to improve the overall performance and reliability of APF devices and promote the development of power quality management technology. Utility Model Content

[0009] In view of the shortcomings of the existing technology, the purpose of this utility model is to provide a control circuit for an APF active filter device based on dual-frequency inverter drive, so as to solve the problems mentioned in the background technology.

[0010] To achieve the above objectives, this utility model employs the following technical solution: an APF active filter control circuit based on dual-frequency inverter drive, comprising a dual-frequency inverter drive module, a pulse width modulation module, and a control interface module. The dual-frequency inverter drive module includes multiple sets of inverter units, each set including a G-series drive interface and multiple sockets E. The pins of the drive interface are directly connected to the pins of the corresponding sockets, and the ground terminal GND of each set of inverter units is connected to the main ground plane to generate dual-frequency inverter drive signals. The pulse width modulation module includes an initial stage circuit and a main circuit providing a clean 24V power supply to the control circuit. The main circuit includes a PWM control chip and an RC filter. The system includes a PWM control circuit and a reverse protection circuit. The output of the initial stage circuit is connected to the input of the RC filter network circuit via a 24V power supply node, providing a stable DC power supply to the PWM control chip. Simultaneously, the ground terminal of the initial stage circuit and the GND pin of the main circuit are connected to the main ground plane to ensure consistency between the power supply and signal ground. The filtered drive signal is input to the PWM control chip through the RC filter network circuit. After modulation, the signal is output to the dual-frequency inverter drive module via the OUT pin connected to the signal port IO_IGBTA of the control interface module, completing precise control of the APF main circuit. The reverse protection circuit is connected in parallel between the OUT pin of the PWM control chip and the G-series drive interface to ensure that the drive signal is transmitted within a safe voltage range.

[0011] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0012] 1. To address the insufficient control accuracy and stability of existing APF control circuits, this invention employs dual-frequency inverter drive technology. Through the coordinated operation of inverter units XO11-XO18 in the dual-frequency inverter drive module, the drive interfaces G1-G8 of each inverter unit are connected to the corresponding 2.54mm sockets E1-E8, ensuring the stable generation and transmission of the dual-frequency inverter drive signal. Simultaneously, through the multi-channel PWM control chip in the pulse width modulation module, combined with the RC filter network circuit and the protection design of the BAV99 diode, precise pulse width modulation of the drive signal is achieved, improving the APF device's tracking and compensation accuracy for harmonic currents, effectively suppressing grid harmonics, and ensuring the stable operation of the power system.

[0013] 2. To address the issues of low integration, weak anti-interference capability, and slow dynamic response in existing APF control circuits, this invention optimizes the overall circuit architecture by tightly integrating various functional modules, simplifying electrical connections, and reducing signal interference paths. The control interface module employs opto-isolation and a 47μF / 10V electrolytic capacitor filter design to block common-mode noise interference and enhance anti-interference capability. Simultaneously, a dual-frequency inverter drive module, combined with transistors Q31 and Q41 and a multi-channel PWM control chip from a pulse width modulation module, rapidly adjusts the inverter unit switching sequence based on the clock signal, accelerating dynamic response. This enables the APF device to quickly adapt to grid changes, promptly compensate for harmonic currents, and improve power quality management.

[0014] 3. To overcome the shortcomings of existing APF control circuit isolation protection and heat dissipation design, this utility model uses a CKX472-300V-Y2 high-voltage capacitor between the dual-frequency inverter drive module and the pulse width modulation module to block high-frequency harmonic back propagation. It also utilizes a layered grounding structure to eliminate ground loop interference and enhance circuit reliability. At the same time, by setting opto-isolation devices between the power interface and signal port of the control interface module, the isolation protection level can be further improved to ensure the long-term stable operation of the APF device. Attached Figure Description

[0015] The disclosure of this utility model is illustrated with reference to the accompanying drawings. It should be understood that the drawings are for illustrative purposes only and are not intended to limit the scope of protection of this utility model. In the drawings, the same reference numerals are used to refer to the same parts. Wherein:

[0016] Figure 1 This is a schematic diagram of the principle structure of the transistor driving circuit and signal conditioning circuit proposed in one embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the inverter unit layout and interface connection structure of the dual-frequency inverter drive module proposed in one embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of the initial stage circuit structure of the pulse width modulation module proposed in one embodiment of the present invention;

[0019] Figure 4A This is a schematic diagram of the principle structure of the first filter circuit proposed in one embodiment of the present invention;

[0020] Figure 4B This is a schematic diagram of the principle structure of the second filter circuit proposed in one embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of the circuit principle structure of the control interface module proposed in one embodiment of the present invention;

[0022] Figure 6 This is a schematic diagram of the power interface, signal port, and hierarchical grounding design principle of the control interface module proposed in one embodiment of this utility model. Detailed Implementation

[0023] It is readily understood that, based on the technical solution of this utility model, those skilled in the art can propose various interchangeable structural methods and implementations without altering the essential spirit of this utility model. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative descriptions of the technical solution of this utility model and should not be considered as the entirety of this utility model or as limitations or restrictions on the technical solution of this utility model.

[0024] As one embodiment of this utility model, the present utility model provides a technical solution: an APF active power filter control circuit based on dual-frequency inverter drive, including a dual-frequency inverter drive module for generating dual-frequency drive signals; a pulse width modulation module for modulating the dual-frequency drive signals; and a control interface module for realizing external control signal access and power distribution. It is understood that the above modules work together through electrical connections to drive the APF main circuit to eliminate grid harmonics.

[0025] like Figure 1 , Figure 2 As shown, in one embodiment of this utility model, the dual-frequency inverter drive module (reference) Figure 1 The inverter unit consists of inverter units XO11, XO12, XO13, XO15, XO16, XO17, and XO18. Each inverter unit includes G-series drive interfaces G1 to G8 and 2.54mm sockets E1 to E8. Pins 1-6 of the G-series drive interfaces are directly connected to pins 1-6 of the corresponding sockets via wires. The 24VGND ground terminal of each inverter unit is connected to the main ground plane via an independent wire to generate dual-frequency inverter drive signals.

[0026] Understandably, the dual-frequency inverter drive module generates two different frequency drive signals (e.g., 20kHz and 40kHz) through multiple sets of inverter units, used to suppress low-frequency and high-order harmonics respectively. Each set of inverter units includes a drive interface (G1-G8) and a 2.54mm socket (E1-E8). Pins 1-6 of the drive interface are directly connected to the corresponding pins of the socket to ensure lossless signal transmission. Taking inverter unit XO11 as an example, pin 1 of its drive interface G1 is connected to pin 1 of socket E1, and the drive signal is output to the APF main circuit through the socket. Each set of inverter units is independently grounded (24VGND) to avoid signal crosstalk. In practical implementation, dual-frequency drive can cover a wider harmonic spectrum, and combined with the independent grounding design, it can achieve the advantages of reducing inter-module interference and improving harmonic suppression efficiency.

[0027] In one embodiment of this utility model, the dual-frequency inverter drive module further includes a transistor drive circuit, the purpose of which is to precisely control the switching timing of the inverter unit through a clock signal.

[0028] The transistor drive circuit includes: PBSS4350Z type NPN transistor Q31 and PBSS5350Z type NPN transistor Q41. The bases of transistors Q31 and Q41 are connected in parallel through a current-limiting resistor R32 and are connected to the clock signal source clk03. The current-limiting resistor R32 limits the base current to ensure that the clock signal stably drives the transistors. The collectors of transistors Q31 and Q41 are independently connected to pin 5 of the G-series drive interface of the dual-frequency inverter drive module to output switching control signals to the inverter unit. The emitters of transistors Q31 and Q41 are directly connected to the main ground plane 24VGND to form a closed loop.

[0029] At this point, when the clock signal source clk03 is high, transistors Q31 and Q41 are turned on, and their collectors output a low level to pin 5 of the G-series drive interface, triggering the inverter unit to turn off. When the clock signal source clk03 is low, transistors Q31 and Q41 are turned off, and their collectors are restored to a high level through external pull-up resistors, driving the inverter unit to turn on. It can be understood that the periodic switching of the clock signal achieves precise synchronization of the inverter unit's switching timing, while the high-frequency characteristics of the PBSS4350Z / PBSS5350Z (low saturation voltage drop, fast switching) ensure drive efficiency and response speed.

[0030] In one embodiment of this invention, the pulse width modulation module is electrically connected to the G-series drive interface of the dual-frequency inverter drive module. The pulse width modulation module modulates the pulse width of the dual-frequency inverter drive signal and includes an initial stage circuit and a main circuit that provide a clean 24V power supply to the control circuit. The main circuit includes a PWM control chip, an RC filter network circuit, and a reverse protection circuit.

[0031] The principle is as follows: the output of the initial stage circuit is directly connected to the input of the RC filter network circuit of the main circuit through the 24V power supply node, providing a stable DC power supply for the PWM control chip; at the same time, the ground terminal (24VGND) of the initial stage circuit and the GND pin of the main circuit are connected to the main ground plane to ensure the consistency of power supply and signal ground. The filtered drive signal is input to the PWM control chip through the RC filter network circuit. After modulation, it is output to the dual-frequency inverter drive module through the OUT pin and the BAV99 diode connected to the signal port IO_IGBTA of the control interface module, thus completing the precise control of the APF main circuit; the reverse protection circuit is connected in parallel between the OUT pin of the PWM control chip and the G series drive interface to ensure that the drive signal is transmitted within a safe voltage range, improving the system's anti-interference capability and long-term reliability.

[0032] like Figure 3 As shown, based on the above technical concept, the initial stage circuit includes: resistors RY1 and RY2 and a high-voltage capacitor CY1. The 24V power supply node is connected to one end of the high-voltage capacitor CY1 through the parallel resistors RY1 and RY2, while the other end of the capacitor is connected to the 24V GND ground terminal. It can be understood that the high-voltage capacitor CY1 forms the main filter path across the power supply node and the ground terminal to form a high-frequency filter network and ensure power supply stability.

[0033] like Figure 4A and Figure 4B As shown, the proposed RC filter network circuit includes a first filter circuit and a second filter circuit with the same circuit structure. The principle is that both receive signals from the G-series drive interface, perform frequency division processing (first branch feedback stability, second branch feedback frequency / duty cycle modulation), and after filtering, input the signals to different pins of the PWM control chip to achieve the stabilization of the feedback signal and the precise modulation of the output signal.

[0034] The custom circuit, including resistors R51 and R54 and capacitors C141 and C142, is the first filter circuit. In specific implementation, resistors R51 and C141, and resistors R54 and C142, respectively form two independent RC filter branches. Both branches are filtered from the same input signal (pin 1 of the G-series drive interface). One branch filters out high-frequency noise and inputs it to the VFB pin (voltage feedback terminal) of the PWM control chip, while the other branch inputs it to the COMP pin (error amplifier compensation terminal) of the PWM control chip. This stabilizes the feedback signal of the PWM control chip and suppresses high-frequency interference. One end of resistor R51 is connected to one end of capacitor C141 and then to pin 1 of the G-series drive interface; the other end is connected to the VFB pin of the PWM control chip. Similarly, one end of R54 is connected to one end of capacitor C142 and then to pin 1 of the G-series drive interface (sharing the same input terminal as R51). C142 is connected to the COMP pin of the PWM control chip.

[0035] The custom circuit, including resistors R81 and R82 and capacitors C121 and C123, serves as the second filter circuit. In practice, resistors R81 and C121, and resistors R82 and C123, respectively form two independent RC filter networks. These networks are filtered from the same input signal (pin 3 of the G-series drive interface): one branch (R81 / C121) sets the frequency of the PWM signal by adjusting the time constant (R81 resistance × C121 capacitance); the other branch (R82 / C123) controls the duty cycle through resistor-capacitor parameter matching, while simultaneously suppressing high-frequency noise in the input signal. Finally, the two filtered signals are input to the RT / CT pin (frequency adjustment terminal) and the ISNS pin (current sensing power supply terminal) of the PWM control chip, respectively, to achieve precise modulation of the PWM output signal. One end of resistor R81 and one end of capacitor C121 are connected to pin 3 of the G-series drive interface, and the other end of resistor R81 and the other end of C121 are connected to the RT / CT pin of the PWM control chip. One end of resistor R82 and one end of capacitor C123 are connected to pin 3 of the same G-series drive interface, and the other end of resistor R82 and the other end of C123 are connected to the ISNS pin of the PWM control chip.

[0036] The reverse protection circuit includes: BAV99 diodes D51 and D52, current-limiting resistors R85 and R86, and filter capacitors C151 and C152. BAV99 diodes D51 and D52 are connected in reverse parallel between the OUT pin of the PWM control chip and the G-series drive interface. The anodes of BAV99 diodes D51 and D52 are connected to the OUT pin, and the cathodes are connected to the G-series drive interface. When a negative transient voltage (such as the back electromotive force of an inductive load) occurs at the G-series drive interface, the BAV99 diodes D51 and D52... 52 conducts and clamps the voltage to a safe range to prevent reverse current from impacting the PWM control chip; current-limiting resistors R85 and R86 are connected between the OUT pin and BAV99 diodes D51 and D52, respectively, to limit the peak output current and prevent overcurrent damage to the PWM control chip or diodes; filter capacitors C151 and C152 are connected in parallel across the current-limiting resistors R85 and R86 (one end of the filter capacitor is connected to the OUT pin, and the other end is grounded or a common node) to filter out high-frequency noise in the drive signal and improve signal quality.

[0037] Based on the above technical concept, the overall circuit topology of the pulse width modulation module is as follows: Power input path: 24V power node - resistor RY1 / RY2 - high-voltage capacitor CY1 / CY2 - resistor RY3 / RY4 - 24VGND ground terminal. Filtering path: The filtering path is formed by high-voltage capacitors CY1 and CY2. Protection design path: The parallel structure of RY1 to RY4 improves power redundancy and prevents overload of a single resistor. The high-voltage characteristics (300V) of high-voltage capacitors CY1 / CY2 ensure the reliability of the circuit under abnormal voltage conditions.

[0038] like Figure 5 , Figure 6 As shown, in one embodiment of this utility model, the control interface module is used to achieve safe interaction between the external controller and the APF main circuit through power filtering, opto-isolation and signal conditioning.

[0039] In specific implementation, the control interface module includes: power interfaces (5V1, Vcc1, Vcc2); 47μF / 10V electrolytic capacitors C94 and C95; connection sockets (2*3PIN_2.54mm) 3PIN socket X01 and 3PIN socket X02; and signal ports IO_IGBTA and opto-isolation devices. The power interface is filtered by electrolytic capacitors. The positive terminals of the electrolytic capacitors are connected to the power interface, and the negative terminals are grounded (24VGND). The filtered power interface (5V1, Vcc1, Vcc2) is connected to the external controller through the power pins (pins 1-3) of the 3-pin socket X02. The signal port IO_IGBTA receives control commands from the external controller through the signal pins (pins 4-6) of the 3-pin socket X01 and outputs a modulated signal. An opto-isolator is connected in series between the power interface and the signal port IO_IGBTA. Its input is connected to the filtered 5V1 / Vcc1-Vcc2 power lines, and its output is connected to the IO_IGBTA signal lines. Internally, it achieves electrical isolation through optocouplers to block common-mode noise from entering the signal circuit from the power circuit.

[0040] In this example, the power interface, the negative terminal of the electrolytic capacitor, and the ground terminals GND1 and GND2 of the signal port IO_IGBTA are all connected to the main ground plane (i.e., ground terminal 24VGND) through independent wires to ensure the purity of the ground signal.

[0041] like Figure 1 As shown, in one embodiment of this utility model, the control interface module further includes a signal conditioning circuit, which includes: a current-limiting resistor R31, filter capacitors C81 and C82, and a decoupling capacitor C101 (capacitors C101-C105 are all decoupling capacitors, providing a low-impedance path for the power network, absorbing transient noise, and preventing power fluctuations from affecting the signal conditioning circuit).

[0042] In practical implementation, one end of the current-limiting resistor R31 is connected to the external control signal input source (such as the output of an optocoupler or controller), and the other end is grounded (24VGND) through parallel filter capacitors C81 and C82 to filter out high-frequency noise. The filtered signal is output from the common node of the current-limiting resistor R31 and filter capacitors C81 and C82, and directly connected to the signal port IO_IGBTA. The decoupling capacitor C101 is connected in parallel between the power interface 5V1, Vcc1-Vcc2 and the ground terminal (24VGND) to suppress high-frequency noise in the power line and ensure the power supply stability of the signal conditioning circuit. It can be understood that resistor R31, as a current-limiting resistor, aims to prevent overload of the external control signal, and simultaneously forms a low-pass filter with C81 / C82, with a cutoff frequency of [missing information]. Filter out high-frequency interference.

[0043] At this point, the conditioned IO_IGBTA signal is transmitted to the clock signal source clk03 node of the transistor drive circuit through the opto-isolation device. The clk03 signal drives the bases of transistors Q31 and Q41 (through the 10K resistor R32), controls their switching state, and then adjusts the timing of the inverter unit (pin 5 of the G series drive interface) to ensure that the switching action of the inverter unit is strictly synchronized with the external command.

[0044] In one embodiment of this invention, the PWM control chip has a multi-channel architecture. Its VREF pin is connected to the 24V power supply node after voltage division by 10K resistors R53 and R55, and the GND pin is directly connected to the ground terminal 24VGND to provide a stable reference voltage and ensure signal ground consistency. Simultaneously, the control circuit adopts a layered grounding structure, where the digital ground GND1 and analog ground GND2 are isolated by a ferrite bead, and all grounding terminals are connected to the main grounding plane through their respective independent wires to eliminate ground loop interference and improve signal integrity.

[0045] The technical scope of this utility model is not limited to the content described above. Those skilled in the art can make various modifications and variations to the above embodiments without departing from the technical concept of this utility model, and all such modifications and variations should fall within the protection scope of this utility model.

Claims

1. A control circuit for an APF active filter device based on dual-frequency inverter drive, characterized in that: include: The module consists of a dual-frequency inverter drive module, a pulse width modulation module, and a control interface module. The dual-frequency inverter drive module includes multiple sets of inverter units. Each set of inverter units includes a G-series drive interface and multiple sockets E. The pins of the drive interface are directly connected to the pins of the corresponding sockets. The grounding terminal GND of each set of inverter units is connected to the main grounding plane to generate dual-frequency inverter drive signals. The pulse width modulation module includes an initial stage circuit and a main circuit that provide a clean 24V power supply to the control circuit. The main circuit includes a PWM control chip, an RC filter network circuit, and a reverse protection circuit. The output of the initial stage circuit is connected to the input of the RC filter network circuit through a 24V power node, providing a stable DC power supply to the PWM control chip. Simultaneously, the ground terminal of the initial stage circuit and the GND pin of the main circuit are connected to the main ground plane to ensure consistency between the power supply and signal ground. The filtered drive signal is input to the PWM control chip through the RC filter network circuit. After modulation, the signal is output to the dual-frequency inverter drive module via the OUT pin connected to the signal port IO_IGBTA of the control interface module, completing precise control of the APF main circuit. The reverse protection circuit is connected in parallel between the OUT pin of the PWM control chip and the G-series drive interface to ensure that the drive signal is transmitted within a safe voltage range.

2. The control circuit of the APF active filter device based on dual-frequency inverter drive according to claim 1, characterized in that: The RC filter network circuit includes: a first filter circuit and a second filter circuit, both receiving signals from the G-series drive interface, wherein... The first filter circuit includes resistors R51 and R54 and capacitors C141 and C142. One end of resistor R51 is connected to one end of capacitor C141 and then to the G-series drive interface. The other end of resistor R51 is connected to the VFB pin of the PWM control chip. Similarly, one end of resistor R54 is connected to one end of capacitor C142 and then to the G-series drive interface. C142 is connected to the COMP pin of the PWM control chip. The second filter circuit includes resistors R81 and R82 and capacitors C121 and C123. One end of resistor R81 and one end of capacitor C121 are connected to the G-series drive interface, and the other end of resistor R81 and the other end of C121 are connected to the RT / CT pin of the PWM control chip. One end of resistor R82 and one end of capacitor C123 are connected to the same G-series drive interface, and the other end of resistor R82 and the other end of C123 are connected to the ISNS pin of the PWM control chip.

3. The control circuit for the APF active filter device based on dual-frequency inverter drive according to claim 1, characterized in that: The reverse protection circuit includes: The BAV99 diodes D51 and D52, current-limiting resistors R85 and R86, and filter capacitors C151 and C152 are configured such that the BAV99 diodes D51 and D52 are connected in reverse parallel between the OUT pin of the PWM control chip and the G-series drive interface. The anodes of the BAV99 diodes D51 and D52 are connected to the OUT pin, and the cathodes are connected to the G-series drive interface. When a negative transient voltage occurs at the G-series drive interface, the BAV99 diodes D51 and D52 conduct and clamp the voltage to a safe range to prevent reverse current from impacting the PWM control chip. The current-limiting resistors R85 and R86 are connected between the OUT pin and the BAV99 diodes D51 and D52, respectively, to limit the peak output current and prevent overcurrent damage to the PWM control chip or diodes. Filter capacitors C151 and C152 are connected in parallel across current-limiting resistors R85 and R86, respectively, to filter out high-frequency noise in the drive signal and improve signal quality.

4. The control circuit for the APF active filter device based on dual-frequency inverter drive according to claim 1, characterized in that: The initial stage circuit includes: resistors RY1 and RY2, and a high-voltage capacitor CY1, wherein... The 24V power node is connected to one end of the high-voltage capacitor CY1 via parallel resistors RY1 and RY2, while the other end of the capacitor is connected to the 24VGND ground terminal. The high-voltage capacitor CY1 forms the main filter path across the power node and the ground terminal to form a high-frequency filter network and ensure power stability.

5. The control circuit for the APF active filter device based on dual-frequency inverter drive according to claim 1, characterized in that: The control interface module includes: The power interface, electrolytic capacitors, 3-pin connector X01, 3-pin connector X02, signal port IO_IGBTA, and opto-isolators are included. The power interface is filtered by electrolytic capacitors, with the positive terminals of the electrolytic capacitors connected to the power interface and the negative terminals grounded. The filtered power interface is connected to an external controller via the power pin of the 3-pin socket X02. The signal port IO_IGBTA receives control commands from the external controller and outputs a modulated signal via the signal pin of the 3-pin socket X01. The opto-isolator is connected in series between the power interface and the signal port IO_IGBTA, with its input connected to the filtered power line and its output connected to the IO_IGBTA signal line. Internally, it achieves electrical isolation through optocouplers, blocking common-mode noise from entering the signal circuit from the power circuit.

6. The control circuit for the APF active filter device based on dual-frequency inverter drive according to claim 5, characterized in that: The power interface, the negative terminal of the electrolytic capacitor, and the grounding terminals GND1 and GND2 of the signal port IO_IGBTA are all connected to the main grounding plane through independent wires to ensure the purity of the grounding signal.

7. The control circuit for the APF active filter device based on dual-frequency inverter drive according to claim 1, characterized in that: The dual-frequency inverter drive module further includes a transistor drive circuit for precisely controlling the switching timing of the inverter unit via a clock signal. The transistor drive circuit includes NPN transistor Q31 and NPN transistor Q41, wherein... The bases of transistors Q31 and Q41 are connected in parallel through a current-limiting resistor R32 and are connected to the clock signal source clk03. The base current is limited by the current-limiting resistor R32 to ensure that the clock signal stably drives the transistors. The collectors of transistors Q31 and Q41 are independently connected to the G-series drive interface of the dual-frequency inverter drive module, which is used to output switching control signals to the inverter unit. The emitters of transistors Q31 and Q41 are both directly connected to the main ground plane, forming a closed loop; When the clock signal source clk03 is high, transistors Q31 and Q41 are turned on, and the collector outputs a low level to the G-series drive interface, triggering the inverter unit to turn off; when the clock signal source clk03 is low, transistors Q31 and Q41 are turned off, and the collector is restored to a high level through the external pull-up resistor, driving the inverter unit to turn on.

8. The control circuit for the APF active filter device based on dual-frequency inverter drive according to claim 5, characterized in that: The control interface module further includes a signal conditioning circuit, which comprises: a current-limiting resistor R31, filter capacitors C81 and C82, and a decoupling capacitor C101. One end of the current-limiting resistor R31 is connected to an external control signal input source, and the other end is grounded through parallel filter capacitors C81 and C82 to filter out high-frequency noise. The filtered signal is output from the common node of the current-limiting resistor R31 and the filter capacitors C81 and C82 and is directly connected to the signal port IO_IGBTA. The decoupling capacitor C101 is connected in parallel between the power interface and the ground terminal to suppress high-frequency noise in the power line and ensure the power supply stability of the signal conditioning circuit. The conditioned IO_IGBTA signal is transmitted to the clock signal source clk03 node of the transistor drive circuit through an opto-isolated device. The clk03 signal drives the base of transistors Q31 and Q41, controls their switching state, and thus adjusts the timing of the inverter unit to ensure that the switching action of the inverter unit is synchronized with the external command.

9. The control circuit for the APF active filter device based on dual-frequency inverter drive according to claim 1, characterized in that: The PWM control chip has a multi-channel architecture. Its VREF pin is connected to the 24V power supply node after voltage division by 10k resistors R53 and R55, and the GND pin is directly connected to the ground terminal 24VGND to provide a stable reference voltage and ensure signal consistency.

10. The control circuit of the APF active filter device based on dual-frequency inverter drive according to claim 1, characterized in that: The control circuit adopts a layered grounding structure, and all grounding terminals are connected to the main grounding plane through their own independent wires to eliminate ground loop interference and improve signal integrity.

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