Cascade multi-level inverter topological structure based on direct-current coupling thyristors

Abstract

The utility model relates to a cascade multi-level inverter topological structure based on direct current coupling thyristors, and belongs to the technical field of power electronic converters. Comprising N H-bridge modules and N DC / DCamp, the H-bridge module comprises four IGBTs (Insulated Gate Bipolar Transistors), the PV panel module comprises N-1 bidirectional switch bridge arms and a power grid filter inductor Lf; the DC / DC amp; the PV panel module comprises a photovoltaic panel, a dual active bridge, a photovoltaic side capacitor Cpvj and a direct current side capacitor Cdcj; the bidirectional switch bridge arm comprises two thyristors Tj1 and Tj2 which are reversely connected in parallel; one end of the power grid filter inductor Lf is connected with the positive electrode of the power grid voltage source vg, the other end of the power grid filter inductor Lf is connected with the midpoint of the S11 and the S12 in the first H-bridge module, the N H-bridge modules are cascaded in sequence, and the midpoint of the SN3 and the SN4 in the Nth H-bridge module is connected with the negative electrode of the power grid voltage source vg. According to the invention, fault ride-through operation can be realized under the condition that the direct-current side voltage sensor has a fault, and large-range module power mismatch can be tolerated.

Description

Technical Field

[0001] This utility model relates to a cascaded multilevel inverter topology based on DC-coupled thyristors, belonging to the field of power electronic converter technology. Background Technology

[0002] As an advantageous topology for grid-connected photovoltaic (PV) systems, cascaded H-bridge inverters offer numerous advantages such as modularity and scalability. However, with increasing power generation scale, the number of modules involved in the cascade increases, and the number of components such as semiconductor switches and sensors also multiplies. Therefore, reliability becomes a significant drawback, prompting extensive research on the operational reliability of PV grid-connected inverters. Existing reliability studies primarily focus on the reliability reduction caused by semiconductor switch failures, as this is a more frequent and impactful issue for the inverter. Sensor failures, influenced by adverse weather conditions, sensor auxiliary power supplies, network attacks / malicious events, and physical wear, are also a major cause of failure in these multilevel converters. Specifically, DC bus voltage sensor failures can lead to current / voltage tracking errors and power mismatch, significantly reducing the overall converter reliability. Therefore, researching sensor failures, particularly those related to DC-side sensor failures, is crucial for improving converter reliability. Some researchers have improved converter reliability by reducing the number of sensors, while others have established observation models for the converter and used the estimated values ​​to replace the failure measurements in the control system for fault-tolerant control. The accuracy of these approaches depends on precise circuit parameters and modeling; inaccurate estimates can negatively impact final performance. Therefore, it is necessary to research a cascaded photovoltaic system based on DC-coupled thyristors to achieve fault ride-through operation and tolerate a wide range of module power mismatches in the event of a DC-side voltage sensor failure. Summary of the Invention

[0003] The technical problem to be solved by this utility model is to provide a cascaded multilevel inverter topology based on DC-coupled thyristors, which can achieve fault ride-through operation and tolerate a wide range of module power mismatch in the event of a DC-side voltage sensor failure.

[0004] The technical solution adopted by this utility model to solve the above problems is as follows: a cascaded multilevel inverter topology based on DC-coupled thyristors, including N H-bridge modules, N DC / DC & PV board modules, N-1 bidirectional switching bridge arms, and a grid filter inductor L. f ,

[0005] The H-bridge module contains four IGBTs: S j1 S j2 S j3 and Sj4 ;

[0006] The DC / DC & PV panel module includes a photovoltaic panel, a dual active bridge, and a photovoltaic-side capacitor C. pvj and DC side capacitor C dcj The bidirectional switching bridge arm includes two thyristors T connected in opposite directions in parallel. j1 and T j2 Where 1≤j≤N;

[0007] The power grid filter inductor L f One end is connected to the mains voltage source v g The positive terminal is connected, and the power grid filter inductor L f The other end connects to the S in the first H-bridge module. 11 and S 12 The midpoints of Sj3 and Sj4 in the j-th H-bridge module are connected, and the midpoints of Sj3 and Sj4 in the t-th H-bridge module are connected. t1 and S t2 Connecting the midpoints, in the Nth H-bridge module, S N3 and S N4 The midpoint of the grid voltage source v g The negative terminals are connected; where t = j + 1;

[0008] One end of the k-th bidirectional switch bridge arm is connected to the upper end of the k-th H-bridge module, and the other end is connected to the upper end of the (k+1)-th H-bridge module; where 1≤k≤N-1;

[0009] One end of the m-th DC / DC & PV board module is connected to the upper end of the m-th H-bridge module, and the other end is connected to the lower end of the m-th H-bridge module, where 1≤m≤N.

[0010] In the DC / DC & PV panel module, the upper end of the photovoltaic panel is connected to a photovoltaic-side capacitor C. pvj The upper end and the upper left end of the dual active bridge, and the lower end of the photovoltaic panel are connected to the photovoltaic-side capacitor C. pvj The lower end and the lower left end of the dual active bridge; the upper right end of the dual active bridge is connected to C. dcj At the upper end, the upper right end of the dual active bridge is connected to C. dcj The lower end.

[0011] Compared with existing technologies, the advantages of this invention are as follows: A cascaded multilevel inverter topology based on DC-coupled thyristors, by introducing bidirectional switching arms, forms redundant paths, providing multiple selectable current paths for grid current. When a DC voltage sensor in the cascaded photovoltaic system fails, the normal voltage sampling value is introduced into the control loop for judgment, selecting the optimal current path, i.e., the switching state combination, to achieve self-balancing of the DC-side voltages. This allows the cascaded photovoltaic system to continue operating normally even when a DC voltage sensor fails, improving the reliability of the cascaded photovoltaic system and providing assurance for fault repair. This application can achieve fault ride-through operation and tolerate a wide range of module power mismatches in the event of a DC-side voltage sensor failure, further improving the operational reliability of the cascaded photovoltaic system. Attached Figure Description

[0012] Figure 1 This invention relates to a cascaded multilevel inverter topology based on DC-coupled thyristors, as described in an embodiment of the present invention.

[0013] Figure 2 for Figure 1 A schematic diagram of the topology of the DC / DC & PV board module;

[0014] Figure 3 This invention relates to a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter based on a DC-coupled thyristor, as described in the embodiment of this utility model. g * ≥0, v r * A schematic diagram of the switching status of the two-module system when ≥0};

[0015] Figure 4 This invention relates to a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter based on a DC-coupled thyristor, as described in the embodiment of this utility model. g * ≥0, v r * A schematic diagram of the three-module system switching status when ≥0};

[0016] Figure 5 This invention relates to a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter based on a DC-coupled thyristor, as described in the embodiment of this utility model. g * ≥0, v r * A schematic diagram of the three-module system switching status when <0};

[0017] Figure 6This invention relates to a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter based on a DC-coupled thyristor, as described in the embodiment of this utility model. g * <0,v r * A schematic diagram of the three-module system switching status when <0};

[0018] Figure 7 This invention relates to a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter based on a DC-coupled thyristor, as described in the embodiment of this utility model. g * <0, v r * A schematic diagram of the three-module system switching status when ≥0};

[0019] Figure 8 This is a flowchart illustrating the mode combination selection of a three-module system based on a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter using DC-coupled thyristors, according to an embodiment of this utility model.

[0020] Figure 9 This invention provides a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter based on a DC-coupled thyristor, which switches from normal operating conditions to V... dc2 Simulated waveforms when a DC voltage sensor malfunctions;

[0021] Figure 10 This invention provides a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter based on a DC-coupled thyristor, which switches from normal operating conditions to V... dc3 Simulated waveforms when a DC voltage sensor malfunctions;

[0022] Figure 11 This invention provides a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter based on a DC-coupled thyristor, which switches from normal operating conditions to V... dc4 Simulated waveforms when a DC voltage sensor malfunctions;

[0023] Figure 12 This invention provides a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter based on a DC-coupled thyristor, which switches from normal operating conditions to V... dc4 Simulated waveforms when a DC voltage sensor malfunctions (voltage imbalance). Detailed Implementation

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0025] like Figure 1As shown, this embodiment presents a cascaded multilevel inverter topology based on DC-coupled thyristors, comprising N H-bridge modules, N DC / DC & PV board modules, N-1 bidirectional switching arms, and a grid filter inductor L. f Each H-bridge module contains four IGBTs: S j1 S j2 S j3 and S j4 Each DC / DC & PV panel module includes a photovoltaic panel, dual active bridges, and a photovoltaic-side capacitor C. pvj and DC side capacitor C dcj Each bidirectional switching bridge arm includes two anti-parallel thyristors T. j1 and T j2 Where 1≤j≤N.

[0026] Grid filter inductor L f One end is connected to the mains voltage source v g The positive terminals are connected, and the mains filter inductor L f One end is connected to the S in the first H-bridge module 11 and S 12 Connecting the midpoints, S in the first H-bridge module 13 and S 14 The midpoint of the second H-bridge module and S 21 and S 22 The first bidirectional switch bridge arm is connected to the upper end of the first H-bridge module, and the other end of the first bidirectional switch bridge arm is connected to the upper end of the second H-bridge module; one end of the first DC / DC & PV board module is connected to the upper end of the first H-bridge module, and the other end of the first DC / DC & PV board module is connected to the lower end of the first H-bridge module. Other H-bridge modules, DC / DC & PV board modules, and bidirectional switch bridge arms are connected in the same manner. Finally, the first... N In each H-bridge module, S N3 and S N4 The midpoint of the grid voltage source v g The negative electrode is connected.

[0027] like Figure 2 As shown, the upper part of the photovoltaic panel in the DC / DC & PV panel module is... C pvj The upper end of the photovoltaic panel is connected to the upper left end of the dual active bridge; the lower end of the photovoltaic panel is connected to... C pvj The lower end of the dual active bridge is connected to the lower left end, and the upper right end of the dual active bridge is connected to... C dcj The upper end is connected, and the lower right end of the dual active bridge is connected to... C dcj Connected to the lower end.

[0028] like Figure 3 As shown, a fault-tolerant strategy for a DC voltage sensor in a cascaded multilevel inverter topology based on DC-coupled thyristors is achieved by realizing voltage self-balancing based on the DC-side coupling principle of the modules. The subsystem comprising two H-bridge modules and one bidirectional switching arm is described. Based on the grid current reference value i... g * and port voltage modulation waveform v r * The combination of judgments can divide the operating area into four regions, Region I to Region IV. Region I is { i g * ≥0, v r * ≥0}, Region II is {i g * ≥0, v r * <0}, Region III is {i g * <0, v r * <0}, Region IV is {i g * <0, v r * ≥0}. When the system is running in Region I, the subsystem has five switching states: State I1 to State I5.

[0029] In State I1, S 11 and S 21 On, S 12 S 13 S 14 S 22 S 23 S 24 T 11 and T 12 When shut down, both modules of the system are in a bypass state, meaning they do not supply power to the system. C dc1 It doesn't charge or discharge. C dc2 When charging and discharging, and the DC-side voltage is balanced, the overall output level is 0.

[0030] In State I2, S 11 S 14 and T 11 On, S 12 S 13 S 21 S22 S 23 S 24 and T 12 When shut down, the two modules of the system are in parallel, supplying C dc1 Discharge or bypass, give C dc2 When charging or bypassing, and the DC side voltage is balanced, the overall output level is 0.

[0031] In State I3, S 14 S 24 and T 11 On, S 11 S 12 S 13 S 21 S 22 S 23 and T 12 When shut down, the two modules of the system are in parallel, providing... C dc1 Charging or bypassing, to C dc2 When discharging or bypassing, and the DC side voltage is balanced, the overall output level is 0.

[0032] In State I4, S 11 S 14 S 24 and T 11 On, S 12 S 13 S 21 S 22 S 23 and T 12 When shut down, the two modules of the system are in parallel, supplying C dc1 Discharge or give C dc2 When discharging and the DC-side voltage is balanced, the overall output level is +V. dc ;

[0033] In State I5, S 11 S 14 S 21 S 24 and T 11 On, S 12 S 13 S 22 S 23 and T 12 When shut down, the two modules of the system are in a series connection, and C is given. dc1 Discharge, to C dc2 When discharging and the DC-side voltage is balanced, the overall output level is +2V. dc .

[0034] Of the five states mentioned above, State I1 and State I5 only have one current flow path and cannot be C. dc1 and C dc2 The charging and discharging of C is selective, and the three parallel states, State I2, State I3, and State I4, each have multiple current flow paths, which can provide C with... dc1 and C dc2 The charging and discharging process provides selectivity. When v dc1 >v dc2 In this case, choosing State I2 and State I4 can help v dc1 and v dc2 The balance, that is, reducing v dc1 When v dc1 <v dc2 In this case, choosing State I3 and State I4 can help v dc1 and v dc2 The balance, that is, reducing v dc2 The analysis in other regions is similar to that in Region I.

[0035] The DC-side coupling principle of the modules is extended to a subsystem consisting of three H-bridge modules and two bidirectional switching arms, which can also be based on the grid current reference value i. g * and port voltage modulation waveform v r * The judgment combination divides the running area into four regions: Region I to Region IV. Region I is {i...} g * ≥0, v r * ≥0}, Region II is {i g * ≥0, v r * <0}, Region III is {i g * <0, v r * <0}, Region IV is {i g * <0,v r * ≥0}. Figures 4-7 The on / off status of each switch in the four areas is displayed respectively. Figure 4 in Region I{i g * ≥0, v r *The switch combinations in ≥0} are as follows Pattern 1-1~ Pattern 1-6.

[0036] Pattern In 1-6, S 11 S 14 S 21 S 24 S 31 S 34 On, S 12 S 13 S 22 S 23 S 32 S 33 T 11 T 12 T 21 T 22 Turn off, give C dc1 C dc2 C dc3 When discharging and the DC side voltage is balanced, the total AC output level is +3V. dc ;

[0037] Pattern In 1-5, S 11 S 14 S 24 S 31 S 34 T 11 On, S 12 S 13 S 21 S 22 S 23 S 32 S 33 T 12 T 21 T 22 Turn off, give C dc1 Or C dc2 Discharge, to C dc3 When discharging and the DC side voltage is balanced, the total AC output level is +2V. dc ;

[0038] Pattern In 1-4, S 11 S 14 S 21 S 24 S 34 T 21 On, S 12 S 13 S 22 S 23 S 31S 32 S 33 T 11 T 12 T 12 Turn off, give C dc1 Discharge, to C dc2 Or C dc3 When discharging and the DC side voltage is balanced, the total AC output level is +2V. dc ;

[0039] Pattern In 1-3, S 11 S 14 S 24 S 34 T 11 T 21 On, S 12 S 13 S 21 S 22 S 23 S 31 S 32 S 33 T 12 T 22 Turn off, give C dc1 Or C dc2 Or C dc3 When discharging and the DC-side voltage is balanced, the total AC-side output level is +V. dc ;

[0040] Pattern In 1-2, S 14 S 24 S 34 T 11 T 21 On, S 11 S 12 S 13 S 21 S 22 S 23 S 31 S 32 S 33 T 12 T 22 Turn off, give C dc1 Charging or bypassing, to C dc2 Charging, discharging, or bypassing, to C dc3 When discharging or bypassing, and the DC side voltage is balanced, the total AC side output level is 0.

[0041] Pattern In 1-1, S 11 S 14 S 24 T11 T 21 On, S 12 S 13 S 21 S 22 S 23 S 31 S 32 S 33 S 34 T 12 T 22 Turn off, give C dc1 Discharge or bypass, give C dc2 Charging, discharging, or bypassing, to C dc3 When charging or bypassing, and the DC side voltage is balanced, the total AC side output level is 0.

[0042] Output level is +2V dc Both 0 and 0 offer two different switching modes to choose from. Therefore, a more reasonable mode can be selected based on the relationship between the DC-side capacitor sizes to achieve DC-side voltage balance. This will be explained in detail below.

[0043] exist Pattern 1-4 and Pattern Among the choices 1-5, the voltage v in the middle is... dc2 In both cases, respectively with v dc1 and v dc3 Coupling can achieve selectivity in charging and discharging.

[0044] When v dc1 >v dc3 When, choose Pattern 1-4, can ensure that the grid current always supplies C dc1 Discharge, and v dc2 and v dc3 Coupled together, according to v dc2 and v dc3 Size of C dc2 and C dc3 Both discharge selectively. When v dc2 >v dc3 At that time, the grid current supplies C dc2 Discharge, C dc3 Bypass; v dc2 <v dc3 At that time, the grid current supplies C dc3 Discharge, C dc2 It was bypassed.

[0045] When v dc1 <v dc3 When, choose Pattern 1-5, can ensure that the grid current always supplies C dc3 Discharge, and vdc2 and v dc1 Coupled together, according to v dc2 and v dc1 Size of C dc2 and C dc1 Both discharge selectively. When v dc1 >v dc2 At that time, the grid current supplies C dc1 Discharge, C dc2 Bypass; v dc1 <v dc2 At that time, the grid current supplies C dc2 Discharge, C dc1 It was bypassed.

[0046] exist Pattern 1-1 and Pattern In selecting option 1-2, the choice also needs to be made based on the relationship between the voltages of each capacitor:

[0047] When v dc1 >v dc3 When, choose Pattern 1-1. If the capacitor voltage relationship is v dc2 >v dc1 >v dc3 At this time, the grid current supplies C dc2 Discharge, give C dc3 Charging, and C dc1 Bypassed; if the capacitor voltage relationship is v dc1 >v dc2 >v dc3 At this time, the grid current supplies C dc1 Discharge, give C dc3 Charging, and C dc2 Bypassed; if the capacitor voltage relationship is v dc1 >v dc3 >v dc2 At this time, the grid current supplies C dc1 Discharge, to C dc2 Charging, and C dc3 It was bypassed.

[0048] When v dc1 <v dc3 When, choose Pattern 1-2, if the capacitor voltage relationship is v dc1 <v dc3 <v dc2 At this time, the grid current supplies C dc2 Discharge, give C dc1 Charging, and C dc3 Bypassed; if the capacitor voltage relationship is v dc1 <v dc2 <v dc3At this time, the grid current supplies C dc3 Discharge, give C dc1 Charging, and C dc2 Bypassed; if the capacitor voltage relationship is v dc2 <v dc1 <v dc3 At this time, the grid current supplies C dc3 Discharge, to C dc2 Charging, and C dc1 It was bypassed.

[0049] The analysis in the other regions can be performed using the same process. It is worth noting that modes 2-1 and 2-2 are consistent with modes 1-1 and 1-2, and modes 4-1 and 4-2 are consistent with modes 3-1 and 3-2. The selection of specific switching mode combinations in different regions can be summarized as follows: Figure 8 The flowchart is shown. The fault-tolerant strategy for DC voltage sensors can achieve voltage balancing when an accurate intermediate DC voltage sample value is missing. Similarly, when an accurate DC voltage sample value is missing from either the left or right side, appropriate mode selection can also achieve voltage balancing across the DC sides.

[0050] Example 1: Setting the grid voltage v g =260V / 50Hz, number of modules N=4, DC link voltage v dcf = 75V, photovoltaic port voltage v dcf = 68V, filter inductor L f =5mH, DC link capacitor C dcj = 940μF, photovoltaic port capacitance C dcj =2200μF, DC link switching frequency is f sw_chb =2.5kHz, DC / DC link switching transistor frequency is f sw_dc =15kHz. For normal operating conditions (DC-side power balance), v dc2 DC voltage sensor failure (DC-side power imbalance), v dc3 DC voltage sensor failure (DC-side power imbalance), v dc4 DC voltage sensor failure (DC-side power imbalance), v dc5 The simulation verification was carried out under five operating conditions: DC voltage sensor failure (DC side power imbalance).

[0051] comprehensive Figure 9Simulation results show that within the time interval 0 to t1, all modules operate at their rated power points, and the DC-side capacitor voltages in the system are in a balanced state. At this time, the THD of the grid current is 2.71%. At t1 = 0.45s, v dc2 The corresponding DC voltage sensor malfunctioned, and the sampled v dc2 The voltage value is clamped to the upper limit of the overvoltage protection setting (approximately 1.25 times the reference value, i.e., 95V). After this moment, the voltage of each DC-side capacitor begins to drop. At t2 = 0.5s, v is activated. dc2 The bidirectional switching arms #1 and #2 on adjacent sides, along with modules #1, #2, and #3 in the THBM+3CDLMs system, form a coupled DC subsystem. Modulation is switched from LSPWM to a DC voltage sensor fault-tolerant strategy. After the switch, pulsed current flows through the bidirectional switching arms #1 and #2, meaning power is exchanged between modules #1 and #2, and between modules #2 and #3. When the current is positive, the faulty module #2 is primarily coupled to module #1; conversely, when the current is negative, the faulty module #2 is primarily coupled to module #3. During this process, the bidirectional switching arm #3 remains unused, and the current i b3 The current is 0 before and after the switchover. Because the photovoltaic power of each module is balanced, the bidirectional switch arm current i... b1 and i b2 The positive current portion is symmetrical to the negative current portion, and all DC-side capacitor voltages recover to the target reference value within 0.05s. The grid current also has good waveform quality (THD of 2.70%).

[0052] Combination Figure 10 The simulation results show that the system is in normal operation from 0 to t1. Under this condition, all modules operate at their rated power points, which is consistent with... Figure 9 The voltages of the DC-side capacitors in the system are consistent, and the voltages are in equilibrium. At t1 = 0.45s, v dc3 The corresponding DC voltage sensor malfunctioned, and the sampled v dc3 The voltage value is also clamped to the upper limit of the overvoltage protection setting (approximately 1.25 times the reference value, i.e., 95V). After this moment, the voltage of each DC-side capacitor begins to drop. At t2 = 0.5s, the bidirectional switching bridge arms #2 and #3 on both sides of vdc3 are activated. Modules #2, #3, and #4 in THBM+3CDLMs constitute a coupled DC subsystem, and the modulation is switched to a DC voltage sensor fault-tolerant strategy. The bidirectional switching bridge arm #1 was never put into use before and after the switching, and the current i on it... b1 The current i on the bidirectional switch bridge arm #2 is always 0. b2 The current waveform changes from 0 to mostly positive (the current waveform is mostly above the horizontal axis), while the current i on the bidirectional switch bridge arm #3... b3The waveform changes from 0 to mostly negative (the current waveform is mostly below the horizontal axis). This indicates that when the grid current is positive, the DC link of module #3 is coupled to the DC link of module #2; conversely, when the grid current is negative, the DC link of module #3 is coupled to the DC link of module #4, ensuring the balance of DC-side capacitor voltages. After applying the proposed strategy, all DC-side capacitor voltages can quickly recover to the target reference value, and the grid current also has good waveform quality (THD of 2.73%).

[0053] Combination Figure 11 The simulation results show that within the range of 0 to t1, all modules operate at their rated power point, which is consistent with... Figure 9 The voltages of the DC-side capacitors in the system are consistent, and the voltages are in equilibrium. At t1 = 0.45s, v dc4 The corresponding DC voltage sensor malfunctioned, and the sampled v dc4 The voltage value is clamped to the upper limit of the overvoltage protection setting (approximately 1.25 times the reference value, i.e., 95V), after which the voltages of the DC-side capacitors begin to drop. At t2 = 0.5s, the modulation switches from carrier rotation to the DC voltage sensor fault-tolerant strategy proposed in this paper. Unlike conditions two and three, the fault voltage at this time is... dc4 The corresponding module is located at the very end of the THBM+3CDLMs subsystem. Therefore, the only adjacent bidirectional switching arms #2 and #3 are selected, meaning modules #2, #3, and #4 form a coupled DC subsystem. In the resulting waveform, positive current values ​​represent power transfer from module #4 to modules #2 and #3, while negative current values ​​represent power transfer in the opposite direction. The current i on bidirectional switching arm #3... b3 It has both positive and negative current components. Due to the photovoltaic power balance of the module, the positive and negative current components are symmetrical, while i b2 Almost all current flows are positive, meaning that module #4 is coupled to module #3 and communicates with module #2 through module #3. Therefore, module #4 and module #3 can transfer power to each other, but module #2 can receive almost no power. After applying the proposed strategy, all DC-side capacitor voltages (including fault sensor voltages) recovered to the target reference value, and the grid current also had good waveform quality (THD of 2.77%).

[0054] Combination Figure 12 The simulation results show that Condition 5 and Condition 4 both have the same DC sensor fault. However, in Condition 5, modules #1 and #4 are in low-power mode (photovoltaic power of 0.8 pu), while modules #2 and #3 are in rated power mode (photovoltaic power of 1.0 pu). The system operates normally from 0 to t1. At t1 = 0.45s, v dc4The corresponding DC voltage sensor malfunctioned, consistent with the previous analysis. At t2 = 0.5s, the voltage sensor was switched on. dc4 DC voltage sensor fault tolerance strategy, after stabilization i b3 The amplitude of the positive current component becomes smaller than that of the negative current component, meaning the power transferred from module #4 to module #3 is lower than the power transferred from module #3 to module #4 in the reverse direction. This is because the original power of module #4 was lower than the original power of module #3. The power of modules #2 and #3 remains unchanged compared to operating condition four. Therefore, the current i on the bidirectional switch arm #2... b2 Almost no change.

[0055] By introducing a bidirectional switching bridge arm, redundant paths are formed, providing multiple selectable current paths for grid current. In the event of a DC voltage sensor failure in the cascaded photovoltaic system, normal voltage sampling values ​​are introduced into the control loop for judgment, selecting the optimal current path, i.e., the switching state combination, to achieve self-balancing of the DC-side voltages. This allows the cascaded photovoltaic system to continue operating normally even when a DC voltage sensor fails, improving the reliability of the cascaded photovoltaic system and providing assurance for fault diagnosis and maintenance. This application enables fault ride-through operation and tolerates a wide range of module power mismatches even when a DC-side voltage sensor fails, further improving the operational reliability of the cascaded photovoltaic system.

[0056] In addition to the above embodiments, this utility model also includes other implementation methods. All technical solutions formed by equivalent transformation or equivalent substitution should fall within the protection scope of the claims of this utility model.

Claims

1. A cascaded multilevel inverter topology based on DC-coupled thyristors, characterized in that: Includes N H-bridge modules, N DC / DC & PV board modules, N-1 bidirectional switching bridge arms, and a grid filter inductor L. f ; The H-bridge module contains four IGBTs: S j1 S j2 S j3 and S j4 ; 1≤j≤N; The DC / DC & PV panel module includes a photovoltaic panel, a dual active bridge, and a photovoltaic-side capacitor C. pvj and DC side capacitor C dcj The bidirectional switching bridge arm includes two thyristors T connected in opposite directions in parallel. j1 and T j2 ; The power grid filter inductor L f One end is connected to the mains voltage source v g The positive terminal is connected, and the power grid filter inductor L f The other end connects to the S in the first H-bridge module. 11 and S 12 The midpoints of Sj3 and Sj4 in the j-th H-bridge module are connected, and the midpoints of Sj3 and Sj4 in the t-th H-bridge module are connected. t1 and S t2 Connecting the midpoints, in the Nth H-bridge module, S N3 and S N4 The midpoint of the grid voltage source v g When the negative terminals are connected, t = j + 1; One end of the k-th bidirectional switch bridge arm is connected to the upper end of the k-th H-bridge module, and the other end is connected to the upper end of the (k+1)-th H-bridge module, where 1≤k≤N-1; One end of the m-th DC / DC & PV board module is connected to the upper end of the m-th H-bridge module, and the other end is connected to the lower end of the m-th H-bridge module, where 1 ≤ m ≤ N.

2. The cascaded multilevel inverter topology based on DC-coupled thyristors according to claim 1, characterized in that: In the DC / DC & PV panel module, the upper end of the photovoltaic panel is connected to a photovoltaic-side capacitor C. pvj The upper end and the upper left end of the dual active bridge, and the lower end of the photovoltaic panel are connected to the photovoltaic-side capacitor C. pvj The lower end and the lower left end of the dual active bridge; the upper right end of the dual active bridge is connected to C. dcj At the upper end, the upper right end of the dual active bridge is connected to C. dcj The lower end.

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