Power amplification circuit and radio frequency chip

Abstract

The utility model provides a power amplification circuit and a radio frequency chip. The power amplification circuit comprises an input switch circuit, an input matching circuit, a power amplifier, an output matching circuit, an output switch circuit, a controller, a time-delay circuit network and a biasing circuit. The output end of the time delay circuit network is connected with the second input end of the input switch circuit and is used for controlling the opening time sequence and the closing time sequence of the input switch circuit; the output end of the bias circuit is connected with the second input end of the power amplifier and used for providing bias voltage for the power amplifier. Compared with the prior art, the power amplification circuit controls the opening time sequence and the closing time sequence of the input switch circuit through the time delay circuit network, so that an input power signal is not too large, the output power signal can be prevented from being totally reflected into a power amplifier, the power amplifier is prevented from being seriously heated, and the service life of the power amplifier is prolonged. Therefore, the problem that the power amplifier is burnt out is solved, and the robustness of the power amplification circuit is effectively improved.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, and in particular to a power amplifier circuit and a radio frequency chip. Background Technology

[0002] The architecture of existing power amplifier chips is as follows Figure 1 As shown, Figure 1 This is a schematic diagram of a power amplifier circuit based on related technologies. It includes an input matching circuit, a power amplifier (PA), an output matching circuit, a bias circuit, a controller, and an output switch. The basic operation involves the controller generating an adjustable voltage via software configuration. This voltage is supplied to the bias circuit, which operates the PA at a suitable DC bias point. When an RF input signal is applied, the input matching circuit minimizes the input standing wave ratio (VSWR), allowing the signal to enter the PA's input. The bias circuit provides the PA with a suitable quiescent operating point, enabling the PA to amplify the input signal. The amplified signal is then passed through the output matching circuit to optimize linearity and efficiency. Finally, the amplified signal is output to the load via the switch.

[0003] In this existing architecture, if a high-power signal is input to the PA when it is turned on, but the output switch is not turned on, the PA will output a very high power signal. Since the switch is not turned on, it is equivalent to an open circuit at the output. This will cause the high-power signal to be reflected back into the PA, causing the PA to overheat and burn out.

[0004] Therefore, there is an urgent need for a new power amplifier circuit and RF chip to solve the above-mentioned technical problems. Utility Model Content

[0005] This invention provides a power amplifier circuit and an RF chip, which aims to prevent the power amplifier from burning out due to excessive input signal and the output switch not being turned on, thereby improving the robustness of the power amplifier circuit.

[0006] In a first aspect, the present invention provides a power amplifier circuit, which includes an input switching circuit, an input matching circuit, a power amplifier, an output matching circuit, an output switching circuit, a controller, a delay circuit network, and a bias circuit.

[0007] The first input terminal of the input switch circuit serves as the input terminal of the power amplifier circuit for receiving input signals, and the output terminal of the input switch circuit is connected to the input terminal of the input matching circuit.

[0008] The output terminal of the input matching circuit is connected to the first input terminal of the power amplifier, and the output terminal of the power amplifier is connected to the input terminal of the output matching circuit.

[0009] The output terminal of the output matching circuit is connected to the first input terminal of the output switching circuit, and the output terminal of the output switching circuit serves as the output terminal of the power amplifier circuit for outputting signals.

[0010] The input terminal of the delay circuit network, the input terminal of the bias circuit, and the second input terminal of the output switch circuit are respectively connected to the controller. The controller is used to control the power amplifier to turn on and off, the input switch circuit to turn on and off, and the output switch circuit to turn on and off, respectively.

[0011] The output terminal of the delay circuit network is connected to the second input terminal of the input switch circuit, and is used to control the turn-on and turn-off timing of the input switch circuit;

[0012] The output terminal of the bias circuit is connected to the second input terminal of the power amplifier to provide a bias voltage for the power amplifier.

[0013] Preferably, the input matching circuit includes a first inductor or a first capacitor;

[0014] The input terminal of the first inductor serves as the input terminal of the input matching circuit, and the output terminal of the first inductor serves as the output terminal of the input matching circuit.

[0015] The input terminal of the first capacitor serves as the input terminal of the input matching circuit, and the output terminal of the first capacitor serves as the output terminal of the input matching circuit.

[0016] Preferably, the output matching circuit includes a second inductor or a second capacitor;

[0017] The input terminal of the second inductor serves as the input terminal of the output matching circuit, and the output terminal of the second inductor serves as the output terminal of the output matching circuit.

[0018] The input terminal of the second capacitor serves as the input terminal of the output matching circuit, and the output terminal of the second capacitor serves as the output terminal of the output matching circuit.

[0019] Preferably, the power amplifier is a transistor or a field-effect transistor.

[0020] Secondly, this utility model also provides a radio frequency chip, which includes a power amplifier circuit as described in any of the above embodiments.

[0021] Compared with the prior art, the power amplifier circuit of this utility model adds a delay circuit network and an input switch circuit at the input end of the power amplifier. The delay circuit network controls the opening and closing timing of the input switch circuit, so that the input power signal is not too large. This can prevent the output power signal from being completely reflected into the power amplifier, causing the power amplifier to overheat and burn out. This effectively improves the robustness of the power amplifier circuit. Attached Figure Description

[0022] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description in conjunction with the following drawings. In the drawings:

[0023] Figure 1 This is a schematic diagram of the power amplifier circuit of the relevant technology;

[0024] Figure 2 This is a schematic diagram of the power amplifier circuit provided in an embodiment of the present invention;

[0025] Figure 3 This is a timing diagram of the power amplifier circuit provided in an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the pin structure of the input switch circuit of the power amplifier circuit provided in this embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0028] Example 1

[0029] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the power amplifier circuit 100 provided in this embodiment of the present invention.

[0030] This utility model provides a power amplifier circuit 100, which includes an input switch circuit 1, an input matching circuit 2, a power amplifier 3, an output matching circuit 4, an output switch circuit 5, a controller 6, a delay circuit network 7, and a bias circuit 8.

[0031] The first input terminal of the input switch circuit 1 serves as the input terminal of the power amplifier circuit 100 for receiving input signals, and the output terminal of the input switch circuit 1 is connected to the input terminal of the input matching circuit 2.

[0032] The output terminal of the input matching circuit 2 is connected to the first input terminal of the power amplifier 3, and the output terminal of the power amplifier 3 is connected to the input terminal of the output matching circuit 4.

[0033] The output terminal of the output matching circuit 4 is connected to the first input terminal of the output switching circuit 5. The output terminal of the output switching circuit 5 serves as the output terminal of the power amplifier circuit 100 for outputting signals.

[0034] The input terminal of the delay circuit network 7, the input terminal of the bias circuit 8, and the second input terminal of the output switch circuit 5 are respectively connected to the controller 6. The controller 6 is used to control the power amplifier 3 to turn on and off, the input switch circuit 1 to turn on and off, and the output switch circuit 5 to turn on and off, respectively.

[0035] The output terminal of the delay circuit network 7 is connected to the second input terminal of the input switch circuit 1, and is used to control the opening and closing timing of the input switch circuit 1.

[0036] The output terminal of the bias circuit 8 is connected to the second input terminal of the power amplifier 3, and is used to provide a bias voltage for the power amplifier 3.

[0037] In this embodiment of the invention, an input switch circuit 1 is added to the input terminal of the power amplifier 3. The input switch circuit 1 can be controlled to turn on and off by the controller 6, and the on-time and off-time of the input switch circuit 1 can be adjusted by the built-in software delay function in the delay circuit network 7. The power amplifier 3, the output switch circuit 5, and the input switch circuit 1 are all triggered by a rising edge, that is, when the control signal changes from low to high level, they are turned on, while they are triggered by a falling edge, that is, when the control signal changes from high to low level, they are turned off.

[0038] For details, please refer to Figure 3 , Figure 3 This is a timing diagram of the power amplifier circuit 100 provided in this embodiment of the present invention. When an RF signal is input, the controller 6 generates a voltage that is supplied to the bias circuit 8, at which time the power amplifier 3 is turned on. Figure 3 Point A in the diagram. At this moment, only power amplifier 3 is turned on; input switch circuit 1 and output switch circuit 5 are off. Power amplifier 3 will not output a high-power signal, thus preventing total reflection that could burn out power amplifier 3. After a delay, output switch circuit 5 turns on, corresponding to... Figure 3At point B, since input switch circuit 1 is not yet turned on, the input RF signal cannot enter power amplifier 3, and power amplifier 3 will not output a high-power signal. After a further delay, input switch circuit 1 turns on, corresponding to... Figure 3 Point C in the diagram indicates that the input signal is amplified by power amplifier 3, outputting a high-power signal to the load. This prevents the high-power signal from being reflected back to power amplifier 3 due to the output switch circuit 5 not being turned on, thus avoiding damage to power amplifier 3.

[0039] The turn-off process of the entire power amplifier circuit 100 is as follows:

[0040] When the timing signal arrives Figure 3 At point F, input switch circuit 1 will turn off first. At this time, the RF input signal will not be amplified by power amplifier 3, preventing power amplifier 3 from burning out due to excessive output signal power and output mismatch. After a period of time, power amplifier 3 will turn off, corresponding to... Figure 3 At point D, power amplifier 3 is not operating. After a period of time, output switch circuit 5 is turned off, corresponding to... Figure 3 At point D in the circuit, the entire power amplifier circuit 100 is turned off.

[0041] In this embodiment of the present invention, the input matching circuit 2 includes a first inductor or a first capacitor; the input terminal of the first inductor serves as the input terminal of the input matching circuit 2, and the output terminal of the first inductor serves as the output terminal of the input matching circuit 2; the input terminal of the first capacitor serves as the input terminal of the input matching circuit 2, and the output terminal of the first capacitor serves as the output terminal of the input matching circuit 2.

[0042] In this embodiment of the present invention, the output matching circuit 4 includes a second inductor or a second capacitor; the input terminal of the second inductor serves as the input terminal of the output matching circuit 4, and the output terminal of the second inductor serves as the output terminal of the output matching circuit 4; the input terminal of the second capacitor serves as the input terminal of the output matching circuit 4, and the output terminal of the second capacitor serves as the output terminal of the output matching circuit 4.

[0043] In this embodiment of the invention, the power amplifier 3 is a transistor or a field-effect transistor.

[0044] Please refer to Figure 4 , Figure 4This is a schematic diagram of the pin structure of the input switch circuit 1 of the power amplifier circuit 100 provided in this embodiment of the utility model. The delay circuit network 7 is implemented through software delay. The delay is achieved by writing an empty loop. The total machine cycles are calculated based on the assembly instructions generated by the Delay() function, and then the time consumed by a for loop is calculated based on the main frequency, thereby determining the delay time. Its implementation principle is as follows:

[0045] Rising edge procedure (start procedure):

[0046] reg_write(0x0E,0x03,0x2C)----Controller 6 outputs a high level to bias circuit 8, power amplifier 3 is turned on, corresponding to Figure 3 Point A in the middle;

[0047] `reg_write(0x0E,0x15,0x06)` ---- After a one-clock-cycle delay, controller 6 outputs an enable signal to output switch circuit 5, enabling output switch circuit 5. Figure 3 Point B in the middle;

[0048] reg_write(0x0A,0x00,0x00)----Delays for one clock cycle, input switch is not enabled;

[0049] reg_write(0x0A,0x00,0x00)----Delays for one clock cycle, input switch is not enabled;

[0050] reg_write(0x0A,0x00,0x00)----Delays for one clock cycle, input switch is not enabled;

[0051] reg_write(0x0A,0x00,0x00)----Delays for one clock cycle, input switch circuit 1 is not turned on;

[0052] reg_write(0x0A,0x00,0x01) ---- After a one-clock-cycle delay, controller 6 outputs an enable signal to input switch circuit 1, enabling input switch circuit 1. Figure 3 Point C in the middle;

[0053] Falling edge procedure (shutdown procedure):

[0054] `neg_reg_write(0x0A,0x00,0x00)` ---- Controller 6 outputs a shutdown signal to input switch circuit 1, shutting down input switch circuit 1. Figure 3 Point F in the middle;

[0055] neg_reg_write(0x0A,0x00,0x00)----Delays for one clock cycle;

[0056] neg_reg_write(0x0A,0x00,0x00)----Delays for one clock cycle;

[0057] neg_reg_write(0x0A,0x00,0x00)----Delays for one clock cycle;

[0058] neg_reg_write(0x0A,0x00,0x00)----Delays for one clock cycle;

[0059] `neg_reg_write(0x0E,0x03,0x00)` ---- Delays for one clock cycle; controller 6 outputs a shutdown signal to bias circuit 8, power amplifier 3 shuts down. Figure 3 Point D in the middle;

[0060] `neg_reg_write(0x0E,0x15,0x00)` ---- Delays for one clock cycle; controller 6 outputs a shutdown signal to output switch circuit 5, causing output switch circuit 5 to shut down. Figure 3 Point E in the diagram.

[0061] Please refer to Table 1, which is the logic table for input switch circuit 1.

[0062] Table 1

[0063]

[0064]

[0065] As shown in Table 1, the input signal is connected to pin RF6 of input switch circuit 1, and pin ANT of output switch circuit 5 is connected to input matching circuit 2.

[0066] The VIO, SCLK, and SDATA pins of controller 6 are connected to the VIO, SCLK, and SDATA pins of input switch circuit 1, and the delay function of delay circuit network 7 is implemented through a preset program.

[0067] reg_write(0x0A,0x00,0x01) turns on RF6 and ANT when Register0 is set to 01.

[0068] Compared with the prior art, the power amplifier circuit of this utility model adds a delay circuit network and an input switch circuit at the input end of the power amplifier. The delay circuit network controls the opening and closing timing of the input switch circuit, so that the input power signal is not too large. This can prevent the output power signal from being completely reflected into the power amplifier, causing the power amplifier to overheat and burn out. This effectively improves the robustness of the power amplifier circuit.

[0069] Example 2

[0070] This utility model embodiment also provides an radio frequency chip, which includes the power amplifier circuit 100 as described in the above embodiment and can achieve the same technical effect. Refer to the description in the above embodiment, and it will not be repeated here.

[0071] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0072] The embodiments of the present utility model have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present utility model. However, the present utility model is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes under the guidance of the present utility model without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present utility model.

Claims

1. A power amplifier circuit, characterized in that, The power amplifier circuit includes an input switching circuit, an input matching circuit, a power amplifier, an output matching circuit, an output switching circuit, a controller, a delay circuit network, and a bias circuit. The first input terminal of the input switch circuit serves as the input terminal of the power amplifier circuit for receiving input signals, and the output terminal of the input switch circuit is connected to the input terminal of the input matching circuit. The output terminal of the input matching circuit is connected to the first input terminal of the power amplifier, and the output terminal of the power amplifier is connected to the input terminal of the output matching circuit. The output terminal of the output matching circuit is connected to the first input terminal of the output switching circuit, and the output terminal of the output switching circuit serves as the output terminal of the power amplifier circuit for outputting signals. The input terminal of the delay circuit network, the input terminal of the bias circuit, and the second input terminal of the output switch circuit are respectively connected to the controller. The controller is used to control the power amplifier to turn on and off, the input switch circuit to turn on and off, and the output switch circuit to turn on and off, respectively. The output terminal of the delay circuit network is connected to the second input terminal of the input switch circuit, and is used to control the turn-on and turn-off timing of the input switch circuit; The output terminal of the bias circuit is connected to the second input terminal of the power amplifier to provide a bias voltage for the power amplifier.

2. The power amplifier circuit as described in claim 1, characterized in that, The input matching circuit includes a first inductor or a first capacitor; The input terminal of the first inductor serves as the input terminal of the input matching circuit, and the output terminal of the first inductor serves as the output terminal of the input matching circuit. The input terminal of the first capacitor serves as the input terminal of the input matching circuit, and the output terminal of the first capacitor serves as the output terminal of the input matching circuit.

3. The power amplifier circuit as described in claim 1, characterized in that, The output matching circuit includes a second inductor or a second capacitor; The input terminal of the second inductor serves as the input terminal of the output matching circuit, and the output terminal of the second inductor serves as the output terminal of the output matching circuit. The input terminal of the second capacitor serves as the input terminal of the output matching circuit, and the output terminal of the second capacitor serves as the output terminal of the output matching circuit.

4. The power amplifier circuit as described in claim 1, characterized in that, The power amplifier is a transistor or a field-effect transistor.

5. A radio frequency chip, characterized in that, The radio frequency chip includes the power amplifier circuit as described in any one of claims 1-4.

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