Semiconductor device

Abstract

A semiconductor device includes a substrate, an isolation insulating region on the substrate, a gate structure on the isolation insulating region, where the gate structure includes a first layer having a first height of a first conductive structure disposed on the isolation insulating region and a second layer having a second height of a second conductive structure disposed on the isolation insulating region. The second layer has a second height of a second conductive structure disposed on the first layer, wherein a ratio of the first height to the second height ranges from 0.02 to 0.06. The semiconductor device includes an interlayer dielectric layer disposed between gate structures.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] As the semiconductor industry has advanced to nanometer technology nodes in pursuit of higher conductivity, higher device density, higher efficiency, and lower cost, challenges from manufacturing and design issues have spurred design advancements, such as in field-effect transistors (FETs), including FinFETs, nanosheet FETs (NSFETs), metal-oxide-semiconductor FETs (MOSFETs), and gate-all-around FETs (GAAFETs). Traditional etching techniques that replace the sacrificial gate with a metal gate result in the metal gate extending into the vicinity of the source / drain regions, leading to increased parasitic capacitance and reduced transistor conductivity. Previous etching techniques using a combination of dry and wet etching processes to etch the sacrificial gate structure resulted in excessive rounding or punching etching into the isolation insulating layer. The loss in the isolation insulating layer and the extension of the metal gate near the source / drain epitaxial regions lead to undesirable parasitic capacitance. Further improvements are needed as transistor sizes continue to shrink to technology nodes below 20-25nm. Utility Model Content

[0003] Some embodiments disclosed herein provide a semiconductor device including a substrate, an isolation insulating region disposed on the substrate, and gate structures disposed on the isolation insulating region. Each gate structure includes a first layer and a second layer. The first layer has a first height of a first conductive structure disposed on the isolation insulating region, and the second layer has a second height of a second conductive structure disposed on the first layer. The semiconductor device includes sidewall spacers disposed on the sidewalls of the gate structures, wherein the ratio of the first height to the height measured from the upper surface of the first conductive structure to the bottom surface of the sidewall spacer is 0.3 to 0.9.

[0004] Some embodiments disclosed herein provide a semiconductor device including a substrate, an isolation region disposed on the substrate, and gate structures disposed on the isolation region, wherein each gate structure includes a first layer and a second layer on the first layer, wherein the first layer includes a curved upper surface. The semiconductor device includes spacers disposed on the sidewalls of the gate structures and an interlayer dielectric layer disposed on the sidewalls of the gate structures.

[0005] Some embodiments disclosed herein provide a semiconductor device including a substrate, an isolation insulating region disposed on the substrate, and gate structures disposed on the isolation insulating region. Each gate structure includes a first layer and a second layer. The first layer has a first height of a first conductive structure disposed on the isolation insulating region, and the second layer has a second height of a second conductive structure disposed on the first layer. The ratio of the first height to the second height ranges from 0.02 to 0.06. The semiconductor device includes an interlayer dielectric layer disposed between the gate structures. Attached Figure Description

[0006] This disclosure is best understood in conjunction with the accompanying drawings and the following detailed description. It should be emphasized that, in accordance with industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1A This is a partial plan view of a semiconductor device;

[0008] Figure 1B It corresponds Figure 1A A cross-sectional view of A-A';

[0009] Figure 1C It corresponds Figure 1A A cross-sectional view of B-B';

[0010] Figure 1D These are isometric views of semiconductor devices according to some embodiments of the present disclosure, and Figure 1E These are some embodiments based on the present disclosure. Figure 1D Partial isometric view;

[0011] Figure 2 This is a cross-sectional view of one of the various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0012] Figure 3A It is a cross-sectional view, and Figure 3B This is an isometric view of one of the various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0013] Figure 4A and Figure 4B This is a cross-sectional view of one of the various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0014] Figure 5A and Figure 5B This is a cross-sectional view of one of the various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0015] Figure 6A and Figure 6B This is a cross-sectional view of one of the various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0016] Figure 7A and Figure 7B This is a cross-sectional view of one of the various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0017] Figure 8A and Figure 8B This is a cross-sectional view of one of the various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0018] Figure 8C This is a cross-sectional view of one of the various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0019] Figure 9A and Figure 9B This is a cross-sectional view of one of the various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0020] Figure 10A and Figure 10B This is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0021] [Symbol Explanation]

[0022] 10:Substrate

[0023] 11: Fin structure / Lower fin structure / Lower well section

[0024] 15: Insulating layer / shallow trench isolation

[0025] 20: First semiconductor layer

[0026] 21: Source / Drain Space

[0027] 25: Second semiconductor layer / nanostructure / channel layer / nanofashelves

[0028] 29: Fin structure

[0029] 30,30',30”,30”': Internal spacers

[0030] 39: Sacrificial gate electrode layer

[0031] 40: Sacrificial gate structure

[0032] 40': Residual Amount / Residual Sacrificial Gate Portion

[0033] 41: Sacrificial gate dielectric layer

[0034] 45: First covering layer / sidewall spacer

[0035] 46: Insulation Part

[0036] 50: Source / Drain Structure

[0037] 68: Contact Etching Stop Layer

[0038] 70: Interlayer dielectric layer / dielectric layer

[0039] 72: Gate space

[0040] 92: Epitaxial layer / epitaxy region

[0041] 99: Metal gate / Metal gate electrode / Metal gate structure / Gate structure

[0042] 100: Gate dielectric layer

[0043] 101: Etching Stop Layer

[0044] H: Thickness

[0045] F,G,Ha',Hb',Hb”,Hb”',Hc',Hc”,Hc”': Height

[0046] M1',M2',M3': Depth

[0047] P': Distance

[0048] D': Bottom

[0049] θ1, θ2: Angles

[0050] X, Y, Z: Direction

[0051] A-A',B-B': line Detailed Implementation

[0052] The following disclosure provides numerous different embodiments or examples of various features for implementing the disclosed features. Specific embodiments or examples of elements and arrangements are described below to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the apparatus. Furthermore, in the description below, forming a first feature on or above a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. For simplicity and clarity, various features may be drawn at any scale.

[0053] Furthermore, the spatially related terms used herein, such as “below,” “under,” “below,” “above,” “on,” etc., are for descriptive purposes to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, these spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly. Furthermore, the term “made of” can mean “comprising” or “consisting of.”

[0054] Furthermore, in subsequent manufacturing processes, one or more additional operations may be performed between the described operations, and the order of operations may be changed. In this disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and unless otherwise stated, does not represent a component from A, a component from B, and a component from C. Throughout this disclosure, source and drain are used interchangeably, and source / drain refers to one or both of the source and drain. In the following embodiments, the materials, configurations, dimensions, processes, and / or operations described for one embodiment (e.g., one or more figures) may be employed in other embodiments, and their detailed description may be omitted. A source / drain configuration may refer individually or collectively to a source or drain, depending on the context.

[0055] The disclosed embodiments relate to a semiconductor device, particularly a field-effect transistor (FET) gate structure, such as, but not limited to, GAA FETs. Other disclosed embodiments include a method of manufacturing a semiconductor device, particularly a method of manufacturing a field-effect transistor gate structure, such as, but not limited to, GAA FETs.

[0056] In the embodiments disclosed herein, the conductivity and performance of the semiconductor device are optimized by reducing the parasitic capacitance of the device. The embodiments disclosed herein minimize the extension of the metal gate into the isolation insulation region near the source / drain regions, allowing the device to operate with increased performance and improved conductivity. In some embodiments, parasitic capacitance is reduced by limiting the extension of the metal gate into the isolation insulation region near the source / drain epitaxial regions after replacing the metal gate. In some embodiments, as parasitic capacitance is reduced, the device current increases and the device yield improves.

[0057] Figure 1A and Figure 1EThis is a schematic diagram illustrating various views of a semiconductor device, such as a GAA FET semiconductor device, according to one embodiment of this disclosure. Other embodiments include FET semiconductor devices, including FinFETs, nanosheet FETs (NSFETs), and metal-oxide-semiconductor FETs (MOSFETs).

[0058] Figure 1A This is a partial planar view of a GAA FET. The GAA FET includes a metal gate 99 and an epitaxial source-drain structure 50. Figure 1B It corresponds to Figure 1A A cross-sectional view of the channel region of the internal gate of the GAA FET cut along line A-A' in the X direction. Figure 1C It corresponds to Figure 1A A cross-sectional view taken along line B-B' in the X direction, showing the outer gate of the GAA FET. In some embodiments, the inner gate is disposed on the channel region, and the outer gate is disposed on the isolation layer. Figure 1D and Figure 1E An isometric view of a GAA FET semiconductor device according to one embodiment of this disclosure is shown, with Figures 1A to 1C Consistent with what is shown.

[0059] like Figure 1B As shown, semiconductor nanostructures 25 are provided on the semiconductor substrate 10 and are vertically aligned along the Z-direction (the normal direction of the main surface of the substrate 10). Figure 1B As shown, semiconductor nanowires or nanosheets (collectively referred to as nanostructures) 25, serving as channel layers, are disposed on the substrate 10. In some embodiments, the semiconductor nanostructures 25 are disposed on the fin structure 11 protruding from the substrate 10 (bottom fin structure 11) (see...). Figure 3A In some embodiments, each channel layer 25 is surrounded by a gate dielectric layer and one or more conductive layers including one or more work function adjustment layers and a gate electrode layer. In some embodiments, the semiconductor nanostructure 25 is made of Si, SiGe, or Ge.

[0060] In some embodiments, an interface dielectric layer (not shown) is formed between the channel and the gate dielectric layer of the semiconductor nanostructure 25. In some embodiments, the gate dielectric layer includes a high-k dielectric layer. The gate structure includes a gate dielectric layer, a gate electrode layer, and gate sidewall spacers. In some embodiments, the gate sidewall spacers are insulating sidewall spacers (or insulating spacers or sidewall spacers). In some embodiments, the gate structure includes a work function adjustment layer disposed between the gate dielectric layer and the gate electrode layer.

[0061] Although Figure 1BThree semiconductor nanostructures 25 are shown. The number of semiconductor nanostructures 25 is not limited to three, and can be as small as one or more than three, and up to ten. The drive current of the GAA FET device can be adjusted by changing the number of semiconductor nanostructures (nanowires, nanosheets, etc.).

[0062] In some embodiments, the source / drain structure 50 is disposed on opposite sides of the metal gate structure 99. In some embodiments, the epitaxial layer 92 is disposed on the lateral end face of the nanosheet 25 and the exposed surface of the lower fin structure 11, such as... Figure 1B As shown. In some embodiments, internal spacers 30 separate the metal gate structure 99 and the source / drain structure 50. The internal spacers are made of an insulating material and can be separated from the gate sidewall spacers 45 ( Figure 1C Made of the same material.

[0063] In some embodiments, source / drain (S / D) contacts (not shown) contact source / drain structures 50. In some embodiments, the S / D contacts comprise one or more metal or metal layers of Ti, TiN, Ta, TaN, Co, W, or alloys thereof. In some embodiments, a silicide layer (not shown) is formed on the source / drain structures 50 prior to forming the S / D contacts. In some embodiments, the silicide layer comprises WSi, NiSi, TiSi, CoSi, or other suitable silicide materials or alloys of metallic elements and silicon and / or germanium.

[0064] In some embodiments, an interlayer dielectric (ILD) layer 70 is disposed on the S / D structure 50, and a conductive contact layer (e.g., a plug or rod) (not shown) passing through the ILD layer 70 is disposed on the S / D structure 50. In other embodiments, the ILD layer 70 comprises one or more layers of insulating material, such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, or any other suitable insulating material.

[0065] In some embodiments, a filling insulating layer (not shown) is provided between the uppermost portion of the metal gate electrode 99 and the ILD layer 70. The filling insulating layer comprises one or more layers of insulating material, such as silicon oxide, silicon nitride, SiCN, SiON, SiOCN, or any other suitable insulating material.

[0066] In some embodiments, a contact etch stop layer 68 is provided between the ILD layer 70 and the S / D structure 50. Figure 1E In some embodiments, the contact etch stop layer 68 comprises one or more layers of silicon nitride, SiON, SiOC, SiOCN, or any other suitable insulating material.

[0067] Figures 2 to 9BThis is a schematic diagram illustrating various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure. It should be understood that... Figures 2 to 9B Additional operations are provided before, during, and after the process shown. For additional embodiments of this method, some of these operations may be substituted or omitted. The order of operations / processes is interchangeable. The same and / or similar materials, configurations, dimensions, and / or processes may be used. Although not explicitly stated... Figures 2 to 9B As shown, in some embodiments, the gate region and source / drain structure are repeated in the X direction in a desired number according to design requirements.

[0068] like Figure 2 As shown, a first semiconductor layer 20 and a second semiconductor layer 25 are alternately formed on the substrate 10. The first semiconductor layer 20 and the second semiconductor layer 25 are made of materials with different lattice constants, and may include one or more layers of silicon (Si), germanium (Ge), SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP.

[0069] In some embodiments, the first semiconductor layer 20 and the second semiconductor layer 25 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. In some embodiments, the first semiconductor layer 20 is made of Si. 1-x Ge x The semiconductor layer 25 is fabricated such that x is equal to or greater than about 0.1 and equal to or less than about 0.6, and the second semiconductor layer 25 is Si or Si 1-y Ge y , where y is less than x and equal to or less than approximately 0.2.

[0070] In other embodiments, the second semiconductor layer 25 is made of Si 1-x Ge x Fabricated where x is equal to or greater than about 0.1 and equal to or less than about 0.6, and the first semiconductor layer 20 is made of Si or Si 1-y Ge y It is formed where y is less than x and equal to or less than about 0.2. In some embodiments, the second semiconductor layer 25 is made of the same material as the semiconductor substrate 10.

[0071] The first semiconductor layer 20 and the second semiconductor layer 25 can be formed by one or more epitaxial (epitaxy / epitaxial, epi) processes. Epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes.

[0072] A first semiconductor layer 20 and a second semiconductor layer 25 are epitaxially formed alternately on a substrate 10. The thickness of the first semiconductor layer 20 may be equal to or greater than the thickness of the second semiconductor layer 25, and in some embodiments the thickness of the first semiconductor layer 20 is in the range of about 4 nanometers (nm) to about 30 nm, and in other embodiments it is in the range of about 5 nm to about 15 nm. In some embodiments, the thickness of the second semiconductor layer 25 is in the range of about 4 nm to about 30 nm, and in other embodiments it is in the range of about 5 nm to about 15 nm. The thickness of the first semiconductor layer 20 may be the same as or different from the thickness of the second semiconductor layer 25. Although in Figure 2 The diagram shows three first semiconductor layers 20 and three second semiconductor layers 25, but the number is not limited to three; it can be one, two, or more than three, but less than 20. In some embodiments, the number of first semiconductor layers 20 is one more than the number of second semiconductor layers 25 (i.e., the top layer is the first semiconductor layer).

[0073] A first semiconductor layer 20 and a second semiconductor layer 25 are provided on a substrate 10 and are arranged perpendicularly along the Z direction (the normal direction of the main surface of the substrate 10). In some embodiments, the substrate 10 includes a single-crystal semiconductor layer at least on its surface portion. The substrate 10 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 10 includes Si. x Ge 1-x 0 ≤ x ≤ 1. The substrate 10 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). In some embodiments, doping is, for example, boron (BF2) for n-type Fin FETs and phosphorus for p-type Fin FETs. In some embodiments, the substrate 10 is made of crystalline Si.

[0074] The substrate 10 may include one or more buffer layers (not shown) in its surface region. The buffer layers can gradually change the lattice constant from that of the substrate to the lattice constant of the source / drain structure. The buffer layers may be formed from epitaxially grown single-crystal semiconductor materials such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on the silicon substrate 10. The germanium concentration of the SiGe buffer layer can be increased from 30 atomic percent (atomic%) of the bottom buffer layer to 70 atomic percent (atomic%) of the top buffer layer.

[0075] After forming the stacked first semiconductor layer 20 and second semiconductor layer 25, a fin structure 29 is formed by one or more photolithography and etching operations, such as Figure 3A and Figure 3B As shown. Fin structures can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to pattern fin structures. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes to form patterns with, for example, a spacing smaller than that obtained by a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be subsequently used to pattern fin structures.

[0076] like Figure 3A As shown, the fin structure 29 extends along the X direction and is arranged in the Y direction. The number of fin structures is not limited to... Figure 3A The two shown can be as small as one or three or more (e.g.) Figure 3B (As shown). In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure to improve pattern fidelity during patterning operations. Figure 3A As shown, the fin structure 29 has an upper portion consisting of stacked first and second semiconductor layers 20 and 25, and a lower well portion 11 (platform structure).

[0077] In some embodiments, the width of the upper portion of the fin structure is in the range of about 5 nm to about 80 nm along the Y direction, and in other embodiments it is in the range of about 10 nm to about 40 nm.

[0078] After forming the fin structure 29, an insulating material layer comprising one or more layers of insulating material is formed on the substrate, such that the fin structure is completely embedded in the insulating layer. The insulating material used for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material formed by low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD. An annealing operation may be performed after forming the insulating layer. Subsequently, a planarization operation, such as chemical mechanical polishing (CMP) and / or etching-back methods, is performed to expose the upper surface of the uppermost second semiconductor layer 25 from the insulating material layer. In some embodiments, one or more fin liner layers are formed on the fin structure before forming the insulating material layer. In some embodiments, the finned substrate includes a first finned substrate and a second finned substrate, the first finned substrate being formed on the sidewalls of the bottom of the substrate 10 and the finned structure 11, and the second finned substrate being formed on the first finned substrate. The finned substrate is made of silicon nitride or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). The finned substrate can be deposited by one or more processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), although any acceptable process can be used.

[0079] Then, as Figure 3A As shown, the insulating material layer is recessed to form an insulating isolation layer 15, exposing the upper part of the fin structure 29. Through this operation, the fin structures 29 are separated from each other by the insulating isolation layer 15, also known as shallow trench isolation (STI). The insulating isolation layer 15 can be made of suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG); low-dielectric-constant dielectrics, such as carbon-doped oxides; extremely low-k dielectrics, such as porous carbon-doped silicon dioxide; polymers, such as polyimide; combinations of these, etc. In some embodiments, the insulating isolation layer 15 is formed by processes such as CVD, flowable CVD (FCVD), or spin-on-glass processes, although any acceptable process can be used.

[0080] In some embodiments, the insulating material layer is recessed until the upper portion of the fin structure (well layer) 11 is exposed. In other embodiments, the upper portion of the fin structure 11 is not exposed. The first semiconductor layer 20 is a sacrificial layer that is subsequently partially removed, while the second semiconductor layer 25 is a semiconductor line or wafer that is subsequently formed as a channel layer for a FET, such as a GAA FET. In other embodiments, the second semiconductor layer 25 is a sacrificial layer that is subsequently partially removed, while the first semiconductor layer 20 is a semiconductor line or wafer that is subsequently formed as a channel layer.

[0081] Figure 3B This is an isometric view showing the fin structure 29 separated by the shallow trench isolation 15 after the sacrificial gate dielectric layer 41 is formed on the fin structure 29 and the shallow trench isolation 15.

[0082] Next, a sacrificial (dummy) gate electrode layer 39 is formed, such as... Figure 4A and Figure 4B As shown, a sacrificial gate electrode layer 39 is formed on the exposed fin structure 29. Figure 4A It is along line A-A' ( Figure 1A ) sectional view, and Figure 4B It is along line B-B' on the external gate. Figure 1A (Cross-section view.) The sacrificial gate electrode layer 39 is formed by blanket deposition of the sacrificial gate electrode layer 39 on the fin structure 29, so that the fin structure is completely embedded in the sacrificial gate electrode layer 39.

[0083] The sacrificial gate electrode layer 39 comprises polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer 39 is in the range of about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer 39 is planarized. The sacrificial gate electrode layer 39 is deposited using CVD including LPCVD and PECVD, PVD, ALD, or other suitable deposition processes. Subsequently, a masking layer (not shown) is formed on the sacrificial gate electrode layer 39.

[0084] Next, a patterning operation is performed on the mask layer, and the sacrificial gate electrode layer 39 is patterned into a sacrificial gate structure 40, as follows. Figure 5A and Figure 5B As shown. By patterning the sacrificial gate structure, a stacked layer of first and second semiconductor layers is partially exposed on opposite sides of the sacrificial gate structure, thereby defining the source / drain region. In some embodiments, a sacrificial gate structure is formed on one or more fin structures, but the number of sacrificial gate structures in each fin structure is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the X direction, as shown. Figure 5AAs shown. In some embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity.

[0085] In other embodiments, a sacrificial gate structure 40 is formed by first blanket deposition of a sacrificial gate dielectric layer on the fin structure 29. A sacrificial gate electrode layer is then blanket deposited on the sacrificial gate dielectric layer and the fin structure, such that the fin structure is completely embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer is planarized. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. Subsequently, a masking layer is formed on the sacrificial gate electrode layer. The masking layer comprises a silicon nitride pad layer and a silicon oxide masking layer.

[0086] After forming the sacrificial gate structure 40, a first capping layer for gate sidewall spacers is formed on the sacrificial gate structure 40. The first capping layer is deposited conformally such that it has substantially equal thickness on vertical surfaces, such as the sidewalls, horizontal surfaces, and top of the sacrificial gate structure 40. In some embodiments, the thickness of the first capping layer is in the range of about 5 nm to about 20 nm. The first capping layer comprises one or more of silicon nitride, silicon oxide, SiON, SiCN, SiCO, SiOCN, or any other suitable dielectric material. The capping layer can be formed by ALD, CVD, or any other suitable method. In some embodiments, one or more additional capping layers are formed on the first capping layer 45 to form a multilayer gate sidewall spacer.

[0087] Next, as Figure 6A and Figure 6B As shown, the first capping layer is anisotropically etched to remove the first capping layer disposed on the source / drain region, while leaving the first capping layer as a sidewall spacer 45 on the side of the sacrificial gate structure 40. Figure 6A Show the line along line A-A' ( Figure 1AA cross-sectional view of the first semiconductor layer 20 and the second semiconductor layer 25 are then etched downwards into the source / drain region using one or more lithography and etching operations to form the source / drain space 21. In some embodiments, the substrate 10 (or the bottom of the fin structure 11) is also partially etched to form a mesa structure. In some embodiments, the n-type FET and the p-type FET are fabricated separately, and in this case, the area of ​​one type of FET is processed, and the area of ​​the other type of FET is covered with a protective layer, such as a silicon nitride layer. In some embodiments, the recessed fin structure has a U-shape. In other embodiments, the recessed fin structure has a V-shape showing the (111) facet of silicon crystallization. In other embodiments, the recess has an inverted trapezoidal or rectangular shape.

[0088] In some embodiments, the depression is formed by a dry etching process, which can be anisotropic. Anisotropic etching processes can be performed using a mixture of process gases including BF2, Cl2, CH3F, CH4, HBr, O2, Ar, and other etchant gases. The process gases can be activated into plasma using any suitable plasma generation method, such as transformer-coupled plasma (TCP) systems, inductively coupled plasma (ICP) systems, and magnetically enhanced reactive ion technology. In some embodiments, the plasma is a long-distance plasma generated in a separate plasma generation chamber connected to the process chamber. The process gases used in the plasma etching process include etchant gases such as H2, Ar, other gases, or combinations of gases. In some embodiments, carrier gases such as N2, Ar, He, and Xe are combined with the plasma etching process gases using hydrogen (H) radicals. H radicals can be formed by infusing H2 gas into the plasma generation chamber and igniting the plasma within the chamber. In some embodiments, an additional gas, such as Ar, can be ignited into plasma within the plasma generation chamber. H radicals can selectively etch the (100) plane onto either the (111) or (110) plane. In some cases, the etching rate of the (100) plane is approximately three times greater than that of the (111) plane. Due to this selectivity, during the second patterning process, etching by H radicals may tend to slow down or stop along the (111) or (110) plane of silicon.

[0089] Further, the first semiconductor layer 20 is laterally etched in the X direction within the source / drain space 21 to form a cavity (not shown). When the first semiconductor layer 20 is SiGe and the second semiconductor layer 25 is Si, the first semiconductor layer 20 can be selectively etched using a wet etchant, such as, but not limited to, a mixed solution of H2O2, CH3COOH, and HF, followed by rinsing with H2O. In some embodiments, etching with the mixed solution and rinsing with water are repeated 10 to 20 times. In some embodiments, the etching time with the mixed solution is in the range of about 1 minute to about 2 minutes. In some embodiments, the mixed solution is used at a temperature in the range of about 60°C to about 90°C. In some embodiments, other etchants are used.

[0090] In some embodiments, the cavity has a curved end shape (transverse U-shaped cross-section) protruding toward the first semiconductor layer 20. In other embodiments, the cavity has a transverse V-shaped cross-section with its apex located at the first semiconductor layer 20.

[0091] Next, a first insulating layer (not shown) is formed on the etched lateral ends of the first semiconductor layer 20 in the source / drain space 21, the end faces of the second semiconductor layer 25, and the sacrificial gate structure 40. The first insulating layer is conformally formed such that space is left in the source / drain space 21. The first insulating layer comprises one or any other suitable dielectric material of silicon nitride, silicon oxide, SiON, SiOC, SiCN, and SiOCN. In some embodiments, the first insulating layer is made of a different material than the sidewall spacers (first capping layer) 45, while in other embodiments, the first insulating layer is made of the same material as the sidewall spacers 45. The first insulating layer can be formed by ALD or any other suitable method. In some embodiments, by forming the first insulating layer, the cavity is completely filled by the first insulating layer.

[0092] After the first insulating layer is formed, an etching operation is performed to partially remove the first insulating layer, thereby forming the internal spacers 30, such as... Figure 6A and Figure 6B As shown. In some embodiments, after etching the first insulating layer, the insulating portion 46 remains on the sidewall spacer 45. In some embodiments, the end face of the inner spacer 30 is more recessed than the end face of the second semiconductor layer 25. The amount of recess is in the range of about 0.2 nm to about 3 nm, and in other embodiments, in the range of about 0.5 nm to about 2 nm. In other embodiments, the amount of recess is less than 0.5 nm and may be equal to 0 (i.e., the end face of the inner spacer 30 is flush with the end face of the second semiconductor layer 25). In some embodiments, an additional insulating layer with a thickness smaller than the first insulating layer is formed before forming the first insulating layer, so the inner spacer 30 has a two-layer structure. In some embodiments, the width (lateral length) of the inner spacer 30 is not constant.

[0093] After the internal spacers 30 are formed, in some embodiments, an epitaxial layer 92 is formed on the lateral end face of the second semiconductor layer 25 and the exposed surface of the lower fin structure 11, such as... Figure 7A As shown. In some embodiments, the epitaxial layer 92 comprises Si doped with P or As for n-type FETs and Si doped with B for p-type FETs. In some embodiments, the doping concentration of the epitaxial layer 92 is higher than the doping concentration of the second semiconductor layer 25. In some embodiments, the doping concentration of the epitaxial layer 92 gradually increases from the interface between the first epitaxial layer 92 and the second semiconductor layer 25 or the lower fin structure 11 to the source / drain space 21. In some embodiments, the thickness of the deposited epitaxial layer is in the range of about 1 nm to about 10 nm. In some embodiments, during the epitaxial formation of the epitaxial layer, some dopant elements diffuse into the second semiconductor layer 25 or the lower fin structure 11 to a depth of about 0.5 nm to about 2 nm.

[0094] Next, as Figure 7A As shown, a source / drain structure 50 is formed in the source / drain space 21. In some embodiments, the source / drain structure 50 includes one or more layers of SiC, SiP, SiAs, and / or SiCP for an n-type FET. In some embodiments, SiC or SiCP is used. In some embodiments, the source / drain structure 50 includes SiGe, SiGeSn, Ge, GeSn, and / or SiSn for a p-type FET. When SiGe is used, in some embodiments, the Ge content is about 60 atomic percent to about 80 atomic percent. In some embodiments, the source / drain structure 50 is formed by an epitaxial process. In some embodiments, the source / drain structure 50 applies tensile stress to the second semiconductor layer 25 for an n-type FET and compressive stress for a p-type FET.

[0095] Next, as Figure 7A and Figure 7B As shown, an interlayer dielectric (ILD) layer 70 is formed on the source / drain structure 50 and the sacrificial gate structure 40. In some embodiments, an etch stop layer 101 is disposed under the sacrificial gate structure 40. In some embodiments, a contact etch stop layer (CESL) 68 is formed prior to the formation of the ILD layer 70. Next, the dielectric layer 70 is planarized by chemical mechanical polishing (CMP) to expose the sacrificial gate material of each sacrificial gate structure 40, such as... Figure 7A and Figure 7BAs shown. The material of ILD layer 70 includes compounds containing Si, O, C and / or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers including polyimide, can be used for ILD layer 70. Materials used for CESL 68 include silicon nitride, silicon oxide, SiCN, SiON and SiOCN. The materials of ILD layer 70 and contact etch stop layer 68 are different from each other, and therefore have different etch selectivity.

[0096] Then, as Figure 8A and Figure 8B As shown, the sacrificial gate electrode material of each sacrificial gate structure 40 is substantially removed to form the gate space 72. During the removal of the sacrificial gate structure 40, the ILD layer 70 protects the source / drain structure 50. In some embodiments, when the sacrificial gate structure 40 is formed from polysilicon, plasma dry etching is performed to create the gate space 72. In some embodiments, dry silicon or dry byproduct etching is performed to substantially remove the sacrificial gate structure. The residual amount 40' of the sacrificial gate structure remains at the bottom of the gate space 72, as shown. Figure 8B As shown. In some embodiments, the sacrificial gate dielectric layer 41 is removed by an internal etching removal process.

[0097] The etching gases used to remove the sacrificial gate structure 40 include Cl2, HBr, CH2F2, CHF3, CF4, CHClF2, HF, and NH3. The passivation gases used for selective etching include N2, O2, CO2, CH4, and SO2. The dilution gases used for dry etching include He, Ar, and N2. Other conditions for the dry etching process include a power range from 10W to 4000W, a pressure range from 1mTorr to 800mTorr, and a gas flow rate from 20sccm to 3000sccm.

[0098] In some embodiments, the residual amount 40' of the sacrificial gate structure retained at the bottom of the gate space has a gate thickness H of about 3 to 6 nanometers, such as Figure 8C As shown. Over-etching to STI 15 is performed using the residual 40' of the sacrificial gate structure, minimizing the loss of STI 15. In some embodiments, the height F measured from the upper surface of the residual 40' of the inner gate to the bottom surface of the sidewall spacer 45 is in the range of about 7 to 10 nanometers. In other embodiments, the height G measured from the upper surface of the residual 40' of the inner gate to the bottom surface of CESL 68 is in the range of about 16 to 20 nanometers. In contrast, using conventional sacrificial gate removal techniques, the height measured from the bottom surface of the over-etched STI of the inner gate to the bottom surface of the sidewall spacer is 10 to 14 nanometers. Furthermore, due to STI loss in conventional techniques, the height measured from the bottom surface of the over-etched STI of the inner gate to the bottom surface of CESL is only 4 to 6 nanometers.

[0099] In some embodiments, the ratio of gate thickness H to height F is about 0.3 to 0.9. In some embodiments, the ratio of gate thickness H to height G is about 0.2 to 0.4. In other embodiments, the ratio of height F to height G is about 0.4 to 0.6. In some embodiments, this ratio improves metal gate rounding performance and reduces excessive recess into the STI.

[0100] In some embodiments, after removing the sacrificial gate structure, the first semiconductor layer 20 is removed to form nanowires or nanosheets (channel regions) of the second semiconductor layer 25. In some embodiments, the channel region is a single channel, while in others it is multi-channel. The first semiconductor layer 20 can be removed or etched using an etchant that selectively etches the first semiconductor layer 20 instead of the second semiconductor layer 25. In some embodiments, the channel region is formed by removing adjacent SiGe layers in a wafer-forming manner. Since the internal spacer 30 is pre-formed, the etching of the first semiconductor layer 20 stops at the internal spacer 30. In other words, the internal spacer 30 serves as an etch stop layer for etching the first semiconductor layer 20.

[0101] After forming the semiconductor nanowires or nanosheets (channel regions) of the second semiconductor layer 25, a metal gate structure 99 is formed, such as... Figure 9A and Figure 9B As shown. In some embodiments, a high-dielectric-constant gate dielectric layer 100 is formed before forming the metal gate electrode. In some embodiments, the high-dielectric-constant dielectric layer is made of hafnium oxide, zirconium oxide, aluminum oxide, aluminum nitride, titanium nitride, silicon nitride, silicon oxynitride, silicon oxy-carbo-nitride, or tantalum nitride. In some embodiments, the structure and / or material of the gate electrode of the n-type GAA FET differs from the structure and / or material of the gate electrode of the p-type GAA FET.

[0102] In some embodiments, the metal gate structure 99 includes one or more work function adjustment layers (not shown). In some embodiments, the work function adjustment layer is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or multiple layers of two or more of these materials. In some embodiments, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer for a p-channel FET. For an n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer. The work function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, the work function adjustment layer can be formed separately for n-channel FETs and p-channel FETs that can use different metal layers.

[0103] A gate electrode layer is formed on the work function adjustment layer to surround each channel layer. The gate electrode layer comprises one or more layers of conductive materials, such as tungsten, cobalt, copper, aluminum, titanium, tantalum, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0104] The gate electrode layer can be formed by CVD, ALD, electroplating, or other suitable methods. In some embodiments, the gate electrode layer is also deposited on the upper surface of the ILD layer 70. The gate dielectric layer (including a high dielectric constant dielectric), work function adjustment layer, and gate electrode layer on the ILD layer 70 are planarized using, for example, CMP, until the top surface of the ILD layer 70 is exposed. In some embodiments, after the planarization operation, the gate electrode layer is recessed and a cap insulating layer (not shown) is formed on the recessed gate electrode. In some embodiments, the cap insulating layer comprises one or more layers of silicon nitride-based material, such as silicon nitride. In other embodiments, the cap insulating layer is formed by depositing an insulating material followed by a planarization operation.

[0105] After metal gate replacement is performed according to the embodiments described herein, the extension of the metal gate near the epitaxial source / drain region is significantly smaller, such as... Figure 9A and Figure 9B As shown. In some embodiments, the metal height Ha' ( Figure 9A ) and metal height Hb'( Figure 9BThe difference is approximately 1 to 3 nanometers, which is an improvement over conventional technology, where the metal gate extends into the STI, resulting in a metal depth difference of approximately 14 to 18 nanometers. Furthermore, in some embodiments, a distance P' of approximately 10 to 15 nanometers is provided between the epitaxial region 92 and the bottom of the metal gate. Figure 9A This is an improvement on traditional technology, which creates a distance of only about 3 to 8 nanometers from the epitaxial region to the bottom of the metal gate.

[0106] Furthermore, in some embodiments, the depth M1' from the bottom of the internal spacer 30"' to the bottom D' of the metal gate structure 99 including the residual sacrificial gate portion 40' is... Figure 9A In some embodiments, the depth M2' from the bottom of the internal spacer 30' to the bottom D' of the metal gate structure 99 including the residual sacrificial gate portion 40' is approximately 4 to 6 nanometers, while with conventional techniques, the depth exceeds approximately 16 to 20 nanometers due to the metal gate extending into the STI. In still other embodiments, the depth M3' from the bottom of the internal spacer 30' to the bottom D' of the metal gate structure 99 including the residual sacrificial gate portion 40' is approximately 19 to 21 nanometers, while with conventional techniques, the depth exceeds approximately 31 to 35 nanometers due to the metal gate extending into the STI. In yet another embodiment, the depth M3' from the bottom of the internal spacer 30' to the bottom D' of the metal gate structure 99 including the residual sacrificial gate portion 40' is approximately 34 to 36 nanometers, while with conventional techniques, the depth exceeds approximately 46 to 50 nanometers due to the metal gate extending into the STI. In some embodiments, by reducing the depths of M1', M2', and M3', an appropriate distance can be maintained between the bottom of the metal gate electrode and the epitaxial source / drain region compared to the depths produced by conventional techniques, thereby achieving a reduction in the parasitic capacitance at the bottom of the metal gate electrode.

[0107] According to this disclosure, the gate length can be varied in some semiconductor devices. Depending on the application of a particular transistor, the gate length and bottom channel length of some transistors are greater than those of other transistors. In some embodiments, according to some examples, the first gate ( Figure 10A The length of the second gate is smaller than that of the larger gate. Figure 10B The length of ). In some embodiments, the upper surface of the residual amount 40' is in the first (or smaller) gate ( Figure 10A ) and the second (or larger) gate ( Figure 10B The structure has a curved surface. In some embodiments, the small gate angle θ1 (measured from the first interface between the sidewall spacer 45 and the metal gate electrode 99 to the second interface between the metal gate 99 and the residue 40' of the sacrificial gate structure) is... Figure 10A Approximately 92 to 95 degrees. In some embodiments, the large gate angle θ2 is measured from the first interface between the sidewall spacer 45 and the metal gate 99 to the second interface between the metal gate 99 and the residue 40' of the sacrificial gate structure. Figure 10B Approximately 100 to 105 degrees Celsius.

[0108] Furthermore, in some embodiments, for small gates ( Figure 10A A height Hb' of approximately 1 to 3 nanometers exists from the upper surface of the residual 40' of the sacrificial gate structure at its thickest point to the upper surface of the residual 40' of the sacrificial gate structure at its thinnest point. In some embodiments, for large gates ( Figure 10B A height Hc' of approximately 3 to 5 nanometers exists between the upper surface of the residual amount 40' of the sacrificial gate structure in the thickest part of the sacrificial gate structure and the upper surface of the residual amount 40' of the sacrificial gate structure in the thinnest part of the sacrificial gate structure.

[0109] In other embodiments, for small gates ( Figure 10A In other embodiments, for large gate structures, a height Hb of approximately 3 to 6 nanometers exists from the upper surface of the residual 40' of the sacrificial gate structure at its thickest point to the bottom surface of the residual 40' of the sacrificial gate structure. Figure 10B A height Hc of approximately 1 to 4 nanometers exists between the upper surface of the residual amount 40' of the sacrificial gate structure in the thickest part of the sacrificial gate structure and the bottom surface of the residual amount 40' of the sacrificial gate structure.

[0110] In yet another embodiment, for small gate ( Figure 10A There is a height Hb"' of approximately 4 to 8 nanometers between the bottom surface of the sidewall spacer 45 and the bottom surface of the etch stop layer 101. In some embodiments, for large gates ( Figure 10B A height Hc"' of approximately 4 to 8 nanometers exists between the bottom surface of the sidewall spacer 45 and the bottom surface of the etch stop layer 101. In some embodiments, the total height of the gate structure 99 is approximately 100 to 200 nanometers. In some embodiments, the ratio of the height of the residual 40' to the total height of the gate structure 99 is approximately 0.02 to 0.06, which improves the metal gate rounding performance and reduces excessive recess into the STI.

[0111] In some embodiments, after completing the GAA FET device ( Figure 1D Afterward, the parasitic capacitance of the device decreases because the metal gate over-extends into STI 15 and minimizes the loss of STI 15. Since the metal gate fill is prevented from extending near the source / drain epitaxial regions, parasitic capacitance is reduced, and device current and yield are improved.

[0112] It should be understood that not all advantages need to be discussed herein, all embodiments or examples do not require specific advantages, and other embodiments or examples may provide different advantages.

[0113] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device includes forming an isolation insulating layer on a substrate. A sacrificial gate layer is formed on the isolation insulating layer. The sacrificial gate layer is patterned to form a sacrificial gate structure. A spacer layer is formed on the sacrificial gate structure. An interlayer dielectric layer is formed on the sacrificial gate structure. The sacrificial gate structure is removed to form an opening in the isolation insulating layer. Residual amounts of the sacrificial gate structure are retained at the bottom of the openings in the isolation insulating layer. A metal gate electrode is formed in the opening. The metal gate electrode comprises a first material, and the residual amounts comprise a second material different from the first material. In one embodiment, the isolation insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG); carbon-doped oxide; porous carbon-doped silicon dioxide, or a polymer. In one embodiment, source / drain regions are formed on the substrate on opposite sides of the sacrificial gate structure. In one embodiment, the residual amounts of the sacrificial gate structure comprise polycrystalline silicon or amorphous silicon. In one embodiment, the interlayer dielectric layer comprises silicon oxide or polyimide. In one embodiment, the metal gate electrode comprises one or more layers of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, hafnium oxide, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, or TaSiN. In one embodiment, a fin structure protruding from the substrate is formed. In other embodiments, a nanostructure is formed on each fin structure. In one embodiment, the height of the residual material is approximately 0.02 to 0.06 of the height of the metal gate electrode. In one embodiment, sidewall spacers formed by spacer layers are formed on the sides of the metal gate electrode. The height of the residual material is approximately 0.3 to 0.9 of the height measured from the upper surface of the residual material to the bottom surface of the sidewall spacers.

[0114] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device includes forming an isolation insulating layer on a substrate. A sacrificial gate layer is formed on the isolation insulating layer. The sacrificial gate layer is etched to form a sacrificial gate structure. A spacer layer is formed on the sacrificial gate structure. An interlayer dielectric layer is formed on the sacrificial gate structure. The sacrificial gate structure is etched to form an opening in the isolation insulating layer. A conductive gate material is formed on reserved portions of the sacrificial gate structure, respectively located at the bottom of the opening. The reserved portions of the sacrificial gate structure are disposed between the conductive gate material and the isolation insulating layer, and the conductive gate material is different from the material of the sacrificial gate layer. In one embodiment, sidewall spacers formed by the spacer layer are formed on the sidewalls of the conductive gate material, wherein the height of one of the reserved portions is in a ratio of 0.3 to 0.9 to the height measured from the upper surface of one of the reserved portions to the bottom surface of the sidewall spacer. In one embodiment, the reserved portion of the sacrificial gate structure comprises polycrystalline silicon or amorphous silicon. In one embodiment, the etching of the sacrificial gate structure comprises plasma etching. In one embodiment, the reserved portion of the sacrificial gate structure comprises a curved upper surface. In one embodiment, fin structures protruding from the substrate are formed; and nanostructures are formed on each fin structure. In one embodiment, the ratio of the height of one of the retained portions to the height of the conductive gate material is 0.02 to 0.06.

[0115] According to another embodiment of this disclosure, a semiconductor device includes a substrate. An isolation insulating region is disposed on the substrate. Gate structures are disposed on the isolation insulating region. Each gate structure includes a first layer and a second layer. The first layer has a first height disposed on the isolation insulating region and made of a first conductive material, and the second layer has a second height disposed on the first layer and made of a second conductive material different from the first conductive material. The ratio of the first height to the second height ranges from 0.02 to 0.06. An interlayer dielectric layer is disposed between the gate structures. In one embodiment, source / drain regions are disposed on the substrate on opposite sides of the gate structures. In one embodiment, the first conductive material includes one or more layers of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, hafnium oxide, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, or TaSiN. In one embodiment, the second conductive material includes polycrystalline silicon or amorphous silicon. In one embodiment, the second conductive material comprises one or more layers of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, hafnium oxide, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, or TaSiN. In one embodiment, the first conductive material comprises polycrystalline silicon or amorphous silicon.

[0116] According to another embodiment of this disclosure, a semiconductor device includes a substrate, an isolation insulating region disposed on the substrate, and a gate structure disposed on the isolation insulating region. Each gate structure includes a first layer and a second layer. The first layer has a first height of a first conductive structure disposed on the isolation insulating region, and the second layer has a second height of a second conductive structure disposed on the first layer. The semiconductor device includes sidewall spacers disposed on the sidewalls of the gate structures, wherein the ratio of the first height to the height measured from the upper surface of the first conductive structure to the bottom surface of the sidewall spacers is 0.3 to 0.9. In one embodiment, the semiconductor device further includes a plurality of source / drain regions disposed on the substrate on opposite sides of the gate structures. In one embodiment, the ratio of the first height of the first conductive structure to the height of the gate structure is 0.02 to 0.06.

[0117] According to another embodiment of this disclosure, a semiconductor device includes a substrate, an isolation insulating region disposed on the substrate, and gate structures disposed on the isolation insulating region, wherein each gate structure includes a first layer and a second layer on the first layer, wherein the first layer includes a curved upper surface. The semiconductor device includes sidewall spacers disposed on the sidewalls of the gate structures and an interlayer dielectric layer disposed on the sidewalls of the gate structures. In one embodiment, the ratio of the height of the first layer to the height measured from the upper surface of the first layer to the bottom surface of the sidewall spacers is 0.3 to 0.9. In one embodiment, the ratio of the height of the first layer to the height of the second layer is 0.02 to 0.06. In one embodiment, the semiconductor device further includes fin structures protruding on the substrate and nanostructures disposed on the fin structures.

[0118] According to another embodiment of this disclosure, a semiconductor device includes a substrate, an isolation insulating region disposed on the substrate, and gate structures disposed on the isolation insulating region. Each gate structure includes a first layer and a second layer. The first layer has a first height of a first conductive structure disposed on the isolation insulating region, and the second layer has a second height of a second conductive structure disposed on the first layer. The ratio of the first height to the second height ranges from 0.02 to 0.06. The semiconductor device includes an interlayer dielectric layer disposed between the gate structures. In one embodiment, the semiconductor device further includes source / drain regions disposed on the substrate on opposite sides of the gate structures. In one embodiment, the semiconductor device further includes sidewall spacers disposed between the interlayer dielectric layer and the gate structures, wherein the ratio of the first height to the height measured from the upper surface of the first conductive structure to the bottom surface of the sidewall spacer is from 0.3 to 0.9.

[0119] The features of many embodiments or examples outlined above will enable those skilled in the art to better understand the viewpoints of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or adapting other processes and structures to achieve the same purpose and / or attain the same advantages as the embodiments or examples described herein. Those skilled in the art will also understand that such equivalent architectures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: One substrate; An isolation and insulation area is provided on the substrate; Multiple gate structures are disposed on the isolation and insulation region, wherein each gate structure includes a first layer and a second layer, the first layer having a first height of a first conductive structure disposed on the isolation and insulation region, and the second layer having a second height of a second conductive structure disposed on the first layer; Multiple sidewall spacers are disposed on multiple sidewalls of the multiple gate structures, wherein the ratio of the first height to the height measured from the upper surface of the first conductive structure to the bottom surface of the multiple sidewall spacers is 0.3 to 0.

9.

2. The semiconductor device as claimed in claim 1, characterized in that, The substrate further includes multiple source / drain regions disposed on opposite sides of the multiple gate structures.

3. The semiconductor device as claimed in claim 1, characterized in that, The ratio of the first height of the first conductive structure to the height of the plurality of gate structures is 0.02 to 0.

06.

4. A semiconductor device, characterized in that, include: One substrate; An isolation and insulation area is provided on the substrate; Multiple gate structures are disposed on the isolation and insulation region, wherein each gate structure includes a first layer and a second layer on the first layer, wherein the first layer includes a curved upper surface; Multiple sidewall spacers are disposed on multiple sidewalls of the multiple gate structures; as well as An interlayer dielectric layer is disposed on the multiple sidewalls of the multiple gate structures.

5. The semiconductor device as claimed in claim 4, characterized in that, The ratio of a height of the first layer to a height measured from an upper surface of the first layer to a bottom surface of the plurality of sidewall spacers is 0.3 to 0.

9.

6. The semiconductor device as claimed in claim 4, characterized in that, The ratio of the height of the first layer to the height of the second layer is between 0.02 and 0.

06.

7. The semiconductor device as claimed in claim 4, characterized in that, Further includes: Multiple fin structures protrude from this substrate; as well as Multiple nanostructures are disposed on each of the fin structures.

8. A semiconductor device, characterized in that, include: One substrate; An isolation and insulation area is provided on the substrate; Multiple gate structures are disposed on the isolation insulating region, wherein each gate structure includes a first layer and a second layer. The first layer has a first height of a first conductive structure disposed on the isolation insulating region, and the second layer has a second height of a second conductive structure disposed on the first layer. The ratio of the first height to the second height ranges from 0.02 to 0.06; and An interlayer dielectric layer is disposed between the plurality of gate structures.

9. The semiconductor device as claimed in claim 8, characterized in that, Further includes: Multiple source / drain regions are disposed on the substrate on opposite sides of the multiple gate structures.

10. The semiconductor device as claimed in claim 8, characterized in that, Further includes: Multiple sidewall spacers are disposed between the interlayer dielectric layer and the multiple gate structures, wherein the ratio of the first height to the height measured from the upper surface of the first conductive structure to the bottom surface of the multiple sidewall spacers is 0.3 to 0.9.

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