Semiconductor memory test equipment
By modifying the timing change circuit of the memory testing equipment to generate signals with different delays, the failure problem of semiconductor memory in signal integrity testing was solved, and reliability testing and parameter verification were realized in different application environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NEUMONDA TECHNOLOGY (JINAN) CO LTD
- Filing Date
- 2025-05-14
- Publication Date
- 2026-05-19
AI Technical Summary
In existing technologies, semiconductor memories have problems failing in signal integrity testing, especially when there are significant differences between the customer's application environment and the test environment. This can lead to reduced data eye diagrams or signal delays, resulting in application failure.
Semiconductor memory testing equipment is used to modify signal timing through timing change circuits, including clock signal generation circuits and delay modification circuits, to generate output signals with different delays. Combined with random or quasi-random signal control, the signal integrity and robustness of the memory are checked.
Effectively detect the signal integrity and robustness of memory, ensure signal reliability in different application environments, and verify the robustness of key DRAM parameters such as tAC by modifying clock signals and data eye diagrams.
Smart Images
Figure CN224263810U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of memory, specifically a semiconductor memory testing device. Background Technology
[0002] DRAM and flash memory technologies have been known for many years, with the basic technologies remaining largely unchanged, but the interfaces have evolved over time, such as Fast Page Mode (FPM), Extended Data Out (EDO), Synchronous DRAM (SDRAM), and Double Data Rate 1-4 (DDR1, DDR2, DDR3, DDR4). In some applications, DRAM components are soldered onto a PCB substrate to form modules, such as DIMM modules to be inserted into a computer system motherboard.
[0003] Testing of packaged memory components has traditionally been accomplished through several steps and multiple insertions. Existing memory testing includes aging tests, weak cell or core tests, speed tests, and application tests. A major challenge with existing testing methods is failure due to signal integrity issues. It is common for memory components to test as perfect but then fail in certain customer applications. This is often due to signal integrity problems and reduced data eye diagrams when components are used in customer environments that differ significantly from the testing environment. Figure 1 The diagram shows the data eye, which is composed (overlay) of all eight DQ signals and DQS signals of the DRAM in, for example, an x8 configuration. During testing, the tester "ggles" or samples at specific times, such as in the middle of the data eye. However, the tester can also correctly ggle the edge data eyes, where all signals are valid and as expected. However, if the customer's motherboard or printed circuit board design is poor, reflections in the data eye diagram may be reduced or one signal may be delayed more due to coupling, leading to application failure. Currently, there is no commercially viable solution for testing the signal integrity robustness of the DUT. Utility Model Content
[0004] The technical problem to be solved by this utility model is to provide a semiconductor memory testing device for detecting the signal integrity and robustness of the device under test.
[0005] To solve the aforementioned technical problem, the present invention adopts the following technical solution: a semiconductor memory testing device, comprising a control unit, a memory under test, and a timing change circuit. One of the following signals from the control unit—the logic system clock clk, the data clock DQS, the data DQ itself, or an address or command signal—is connected to the input terminal of the timing change circuit. The timing change circuit changes the timing of the input signal and outputs it. The output signal, along with other signals from the control unit, is connected to the memory under test. The memory under test is tested based on the signal output by the timing change circuit.
[0006] Furthermore, the timing modification circuit includes a clock signal generation circuit and a delay modification circuit. The clock signal generation circuit generates a clock signal input_clock and transmits it to the delay modification circuit. The delay modification circuit includes a clock signal input terminal and a control signal input terminal. The delay modification circuit generates an output signal with a delay relative to the input clock signal based on the input clock signal and the control signal. The output signal is transmitted to the memory under test.
[0007] Furthermore, the delay modification circuit generates at least two output signals with different timings, and the control signal of the delay modification circuit receives random or quasi-random signals during at least a portion of the test sequence.
[0008] Furthermore, the timing change circuit includes a clock signal generation circuit and a clock selection circuit. The clock signal generation circuit generates multiple clock signals with different timings and transmits them to the clock selection circuit. The clock selection circuit includes a clock signal input terminal and a control signal input terminal. The clock selection circuit selects one or more of the multiple input clock signals as output signals based on the input clock signal and the control signal. The output signal is transmitted to the memory under test.
[0009] Furthermore, the clock selection circuit generates at least two output signals with different timings, and the control signal of the clock selection circuit receives random or quasi-random signals during at least a portion of the test sequence.
[0010] Furthermore, the clock selection circuit is a multiplexed circuit.
[0011] Furthermore, it includes at least two memory devices under test and at least one control unit, the at least one control unit having at least one electrical signal connected to at least one memory device under test, the at least two memory devices under test and at least one control unit being connected by a connector, and the memory devices under test and the control unit being located on a circuit board.
[0012] The beneficial effects of this invention are as follows: This invention modifies the clock signal during testing, checking the robustness of the DUT to signal integrity by providing measures to examine the signal width margin and robustness of certain signals within the data eye diagram. The clock signal can be modified, as can the book select strobe (DQS). The memory uses the DQS to latch DQ data, and the shifting of the DQS signal during testing will check the robustness of the data eye diagram. The timing of individual address / command or data (DQ) signals can also be changed to verify the signal integrity robustness of each signal pin of the memory. To ensure clock signal diversity, random jitter is added when changing the clock signal. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of a data eye diagram;
[0014] Figure 2 This is a schematic diagram of the test equipment described in Example 1;
[0015] Figure 3 This is a schematic diagram of the test equipment described in Example 2. Detailed Implementation
[0016] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0017] Example 1
[0018] This embodiment discloses a semiconductor memory testing device, such as... Figure 2 As shown, the test includes a DUT board with at least two Devices under Test (DUTs) and a test board including at least one control unit. The control unit has at least one electrical signal connection to the at least one DUT. There are two configuration options for the control unit and the DUTs: First, the control unit is implemented by an FPGA, CPU, microcontroller, or other processing unit located on the test board, while the DUTs are located on a module such as a PCB (DUT board) to simulate a signal integrity environment similar to many customer applications. The control unit communicates with the DUTs on the DUT board via connectors. Second, the control unit and the DUT board are located on the same physical board, and the test is performed via an FPGA, CPU, microcontroller, or other signal processing unit. Testing in such an environment replicates the non-ideal signal integrity of the customer application more closely. However, it is still possible that the test results are slightly correct, and the DUT is confirmed to be functioning correctly. When plugged into a real customer application with poor signal integrity, minor faults may suddenly appear at the edge through the DUT.
[0019] Therefore, in this utility model disclosure, we propose a new test apparatus to check the robustness of a DUT to signal integrity by providing measures to examine certain signal width margins and robustness within the data eye diagram. To achieve signal integrity or data eye diagram robustness of the DUT, we modify the clock signal during testing. The clock signal of interest is, for example, the logic system clock clk, the data clock DQS, or the data DQ itself; in a radical approach, even the address or command signal Addr / cmd can be changed.
[0020] During testing, the clock signal is modified through a timing change circuit. One of the control unit's logic system clock clk, data clock DQS, data DQ itself, address, or command signal is connected to the input of the timing change circuit. The timing change circuit changes the timing of the input signal and outputs it. The output signal, along with other signals from the control unit, is connected to the memory under test. The memory under test is then tested based on the signal output by the timing change circuit.
[0021] In this embodiment, the timing modification circuit includes a clock signal generation circuit and a delay modification circuit. The clock signal generation circuit generates a clock signal input_clock and transmits it to the delay modification circuit. The delay modification circuit includes a clock signal input terminal and a control signal input terminal. The delay modification circuit generates an output signal with a delay relative to the input clock signal based on the input clock signal and the control signal. The output signal is transmitted to the memory under test.
[0022] In this embodiment, the output clock signal and input clock signal of the delay modification circuit are essentially the same, except for a time shift. For example, these clocks can all be shifted by 20 ps if clk_out is the same as clk or deviates from clk by as much as + / - 40 ps. Even with the clock signal shifted, it is feasible to check whether the DUT reliably outputs correctly over a wider range. In the case of DRAM, shifting the system clock signal clk will check the robustness of the signal on the red address / command bus. If the output data DQ is still correct, even if the signal integrity on the command bus is not ideal, the shifted clock indicates robust data eye receiving commands and ground from the controller. Another key parameter that can be checked in this way is the DRAM's tAC. tAC represents the time from clock to DQ in one clock cycle; for example, DRAM specifications may require tAC = + / - 250 ps. By shifting clk during testing, the robustness of operation relative to tAC can be verified.
[0023] In this embodiment, the number of DUTs on the DUT board is greater than 3. Specifically, the number of DUTs on the DUT board is 4, 8, 9, 16, or 18.
[0024] At least one DUT is a semiconductor memory, such as DRAM, flash memory, MRAM, RRAM, SRAM, or other semiconductor memory. Or at least one DUT is a DRAM compliant with JEDEC specifications.
[0025] In this embodiment, the output clock signal of the delay modification circuit is connected to at least one pinclk of at least one DRAM DUT, or to at least one pin DQS of at least one DRAM DUT, or to at least one pin DQ of at least one DRAM DUT, or to at least one address pin of at least one DRAM DUT, or to at least one command pin of at least one DRAM DUT.
[0026] In this embodiment, at least one control unit is performing a test sequence on at least one DUT, and during the test sequence, a delay modification circuit generates at least two different output_clock signals, and during the test sequence, the delay modification circuit is controlled by a control input signal that receives random or quasi-random signals for at least a portion of the test sequence.
[0027] Example 2
[0028] like Figure 3As shown, in this embodiment, the timing modification circuit includes a clock signal generation circuit and a clock selection circuit. The clock signal generation circuit generates multiple clock signals with different timings and transmits them to the clock selection circuit. The clock selection circuit includes a clock signal input terminal and a control signal input terminal. The clock selection circuit selects one or more of the multiple input clock signals as output signals based on the input clock signal and control signal. The output signal is transmitted to the memory under test (DUT). The clock selection circuit is a multiplexing circuit. The original clock is connected to the multiplexing circuit, and additional clock signals clk2 to clk5 are also connected to the input terminals of the multiplexer. These multiplexer input terminals have different time shifts from clk. For example, these clocks can all be shifted by 20 ps. The input multiplexer of the multiplexer determines which clock signals will be forwarded and connected to the DUT. In this way, the multiplexer can be controlled in 20 ps steps if clk_out is the same as clk or deviates from clk by up to + / - 40 ps. Even if the clock signal is shifted, it is feasible to check whether the DUT reliably outputs correctly over a wider range. When the DUT is DRAM, shifting the system clock signal clk will check the robustness of the signals on the red address / command bus. If the output data DQ is still correct, even if the signal integrity on the command bus is not ideal, the shifted clock indicates robust data eye receiving commands and ground from the controller. Another key parameter that can be checked in this way is the DRAM's tAC. tAC represents the time from clock to DQ in one clock cycle; for example, DRAM specifications might require tAC = + / - 250ps. By shifting clk during testing, the robustness of operation relative to tAC can be verified.
[0029] In this embodiment, the clock generation circuit generates n clock signals, where n is an integer from 2 to 10.000.
[0030] In this embodiment, at least one control unit is performing a test sequence on at least one DUT, and during such a test sequence, a clock selection circuit generates at least two output signals with different timings, and the control signal of the clock selection circuit receives random or quasi-random signals during at least a portion of the test sequence.
[0031] Combinations of several shifted clock signals are also possible. For some in the circuit design field, alternative clock delay mechanisms that do not rely on multiplexers can be implemented.
[0032] Everything else is the same as in Example 1, and will not be repeated here.
[0033] In the above description, the control unit is only used to send data, clock, address and other signals, and to execute test scripts to complete the test. The control unit is not improved, and the innovation of this utility model does not lie in the control unit.
[0034] The above description is only the basic principle and preferred embodiment of this utility model. Any improvements and substitutions made by those skilled in the art based on this utility model shall fall within the protection scope of this utility model.
Claims
1. A semiconductor memory testing device, characterized in that: The system includes a control unit, a memory under test (MDT), and a timing modification circuit. One of the following signals from the control unit—a logic system clock (clk), a data clock (DQS), the data clock (DQ) itself, or an address or command signal—is connected to the input of the timing modification circuit. The timing modification circuit modifies the timing of the input signal and outputs it. The output signal, along with other signals from the control unit, is connected to the MDT. The MDT is tested based on the signal output by the timing modification circuit. The timing modification circuit includes a clock signal generation circuit and a delay modification circuit. The clock signal generation circuit generates a clock signal (input_clock) and transmits it to the delay modification circuit. The delay modification circuit includes a clock signal input terminal and a control signal input terminal. Based on the input clock signal and the control signal, the delay modification circuit generates an output signal with a delay relative to the input clock signal. The output signal is transmitted to the MDT.
2. The semiconductor memory testing equipment according to claim 1, characterized in that: During the test, the delay modification circuit generates at least two output signals with different timings, and the control signal of the delay modification circuit receives random or quasi-random signals during at least a portion of the test sequence.
3. The semiconductor memory testing equipment according to claim 1, characterized in that: The timing change circuit includes a clock signal generation circuit and a clock selection circuit. The clock signal generation circuit generates multiple clock signals with different timings and transmits them to the clock selection circuit. The clock selection circuit includes a clock signal input terminal and a control signal input terminal. The clock selection circuit selects one or more of the multiple input clock signals as output signals based on the input clock signal and control signal. The output signal is transmitted to the memory under test.
4. The semiconductor memory testing equipment according to claim 3, characterized in that: During the test, the clock selection circuit generates at least two output signals with different timings, and the control signal of the clock selection circuit receives random or quasi-random signals during at least a portion of the test sequence.
5. The semiconductor memory testing equipment according to claim 4, characterized in that: The clock selection circuit is a multiplexed circuit.
6. The semiconductor memory testing equipment according to claim 1, characterized in that: It includes at least two memory devices under test and at least one control unit, wherein the at least one control unit has at least one electrical signal connected to at least one memory device under test, and the at least two memory devices under test and at least one control unit are connected by a connector or the memory devices under test and the control unit are located on a circuit board.