Semiconductor device

Abstract

The present disclosure relates to a semiconductor device comprising: a gate structure; epitaxial source / drain regions on opposite sides of the gate structure; a first source / drain contact surrounding a top surface, a bottom surface and opposite sides of a first one of the epitaxial source / drain regions; and a backside via underlying the first one of the epitaxial source / drain regions. The backside via is in contact with a bottom surface of the first source / drain contact.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a back-side via. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and by using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size. This continuous reduction in the minimum feature size allows more components to be integrated into a given area. Utility Model Content

[0004] In some embodiments, a semiconductor device includes a gate structure, an epitaxial source / drain region, a first source / drain contact, and a back-side via. The epitaxial source / drain region is located on an opposite side of the gate structure. The first source / drain contact surrounds a top surface, a bottom surface, and an opposite side of a first portion of the epitaxial source / drain region. The back-side via is located below the first portion of the epitaxial source / drain region. The back-side via contacts a bottom surface of the first source / drain contact.

[0005] In some embodiments, a semiconductor device includes a gate structure, epitaxial source / drain regions, and a source / drain contact. The epitaxial source / drain regions are located on opposite sides of the gate structure. A source / drain contact is located on a first portion of the epitaxial source / drain regions, extending from above a top surface of the first portion of the epitaxial source / drain regions to below a bottom surface of the first portion of the epitaxial source / drain regions.

[0006] In some embodiments, a semiconductor device includes a channel, a gate structure, epitaxial source / drain regions, and a first source / drain contact. The gate structure is located on the channel. The epitaxial source / drain regions are located on opposite sides of the channel. The first source / drain contact surrounds the entirety of a first one of the epitaxial source / drain regions. Attached Figure Description

[0007] A better understanding of the various features disclosed herein can be achieved by referring to the accompanying drawings and the following detailed description. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, for ease of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 1B For self Figure 1A The cross-sectional view obtained by section line A-A' in the diagram;

[0009] Figure 2A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 2B For self Figure 2A The cross-sectional view obtained by section line A-A' in the diagram;

[0010] Figure 3A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 3B For self Figure 3A The cross-sectional view obtained by section line A-A' in the diagram;

[0011] Figure 4A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 4B For self Figure 4A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 4C For self Figure 4A The cross-sectional view obtained by section line B-B' in the diagram;

[0012] Figure 5A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 5B For self Figure 5A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 5C For self Figure 5A The cross-sectional view obtained by section line B-B' in the diagram;

[0013] Figure 6A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 6B For self Figure 6A The cross-sectional view obtained by section line A-A' in the diagram;

[0014] Figure 7A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 7B For self Figure 7A The cross-sectional view obtained by section line A-A' in the diagram;

[0015] Figure 8A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 8B For self Figure 8A The cross-sectional view obtained by section line A-A' in the diagram;

[0016] Figure 9A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 9B For self Figure 9A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 9C For self Figure 9A The cross-sectional view obtained by section line B-B' in the diagram;

[0017] Figure 10A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 10B For self Figure 10A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 10C For self Figure 10A The cross-sectional view obtained by section line B-B' in the diagram;

[0018] Figure 11A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 11B For self Figure 11A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 11C For self Figure 11A The cross-sectional view obtained by section line B-B' in the diagram;

[0019] Figure 12A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 12B For self Figure 12A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 12C For self Figure 12A The cross-sectional view obtained by section line B-B' in the diagram;

[0020] Figure 12D According to some other embodiments, self Figure 12A The cross-sectional view obtained by section line B-B' in the diagram;

[0021] Figure 13A A plan view of an intermediate stage in the manufacturing of an IC structure. Figure 13B For self Figure 13A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 13C For self Figure 13A The cross-sectional view obtained by section line B-B' in the diagram;

[0022] Figure 13D According to some other embodiments, self Figure 13A The cross-sectional view obtained by section line B-B' in the diagram;

[0023] Figure 14 A graph illustrating the current-voltage (IV) simulation results of transistors with different contact schemes.

[0024] [Symbol Explanation]

[0025] 10:Substrate

[0026] 100: Buffer layer

[0027] 101: First semiconductor layer / Bottom semiconductor layer / Sacrificial layer

[0028] 102: Second semiconductor layer / channel layer / bottom channel layer / upper channel layer / nanofashes

[0029] 103: Shallow Trench Isolation (STI) Area

[0030] 104: Bottom Sacrificial Layer

[0031] 105: Virtual Gate Structure

[0032] 106: Sacrificial Dielectric Layer

[0033] 107i: Internal spacer

[0034] 107o: Gate spacer

[0035] 108: Epitaxial source / drain region / epitaxy region

[0036] 109: Metal silicide layer

[0037] 109': Backside metal silicide layer

[0038] 110: Interface Layer

[0039] 111: High-k gate dielectric layer

[0040] 112: Work function metal layer

[0041] 113: Filler metal layer / filler metal

[0042] 114: Dielectric Structure

[0043] 115: Source / Drain Contacts

[0044] 115L: Bottom contact part

[0045] 115M: Intermediate contact part

[0046] 115U: Top Contact Part

[0047] 116: Front-side interconnect structure

[0048] 116V: Front guide hole

[0049] 117: Backside interconnect structure

[0050] 117V: Backside guide hole

[0051] BS: Backside surface

[0052] C1: Curve

[0053] C2: Curve

[0054] F1: Upper slope

[0055] F2: Downslope

[0056] F3: Bottom Surface

[0057] FS: Fin structure / front surface

[0058] GS: Gate structure

[0059] GS1: Upper gate portion

[0060] GS2: Lower gate portion

[0061] GT1: Gate Trench

[0062] ILD: Interlayer Dielectric Layer

[0063] ILD1: Front interlayer dielectric layer

[0064] ILD_B: Backside interlayer dielectric layer

[0065] MS: Multilayer epitaxial stack

[0066] O1: Opening

[0067] O2: Source / drain contact opening

[0068] O3: Bottom opening

[0069] R1: Depression

[0070] SL1: Sacrifice Layer

[0071] SL2: Bottom Sacrificial Layer

[0072] SP: Serrated sidewall profile Detailed Implementation

[0073] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features can be formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0074] Furthermore, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar terms may be used herein to describe the relationship between an element or feature and other elements or features illustrated in the figures. In addition to the orientations described in the figures, spatial relative terms are also intended to include different orientations of the device during use or operation. The device may also be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The numerical values ​​given herein are approximate and are meant to be inferred unless explicitly stated otherwise. However, those skilled in this art should realize that the values ​​or ranges described throughout the description are merely examples and may be reduced or changed as integrated circuits are scaled.

[0075] This disclosure generally relates to integrated circuit structures and methods of forming them, and more specifically, to the fabrication of GAA transistors having back-side vias beneath the source and / or drain regions of a gate-all-around (GAA) transistor. It should also be noted that embodiments are presented in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of a channel region. These multi-gate devices may include p-type or n-type metal-oxide-semiconductor devices. Due to finned structures, specific examples are presented herein and referred to herein as FinFETs. Embodiments of a type of multi-gate transistor referred to herein as a gate-all-around (GAA) device are also presented herein. A GAA device includes any device whose gate structure or a portion thereof is formed on four sides of a channel region (e.g., surrounding a portion of the channel region). Devices presented herein also include embodiments in which the channel region is disposed in a nanosheet channel, nanowire channel, and / or other suitable channel configuration. Embodiments of devices having one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure are presented herein. However, those skilled in the art will recognize that the teachings can be applied to a single channel (e.g., a single nanosheet) or any number of channels. Those skilled in the art will also recognize other examples of semiconductor devices that can benefit from the various types of semiconductor devices disclosed herein.

[0076] Gate all-around (GAA) transistor structures can be patterned using any suitable method. For example, these structures can be patterned using one or more lithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine lithography and self-alignment processes, thereby allowing the production of patterns with, for example, smaller pitches compared to those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0077] As the fin width in fin field-effect transistors (FinFETs) shrinks, changes in channel width can lead to mobility losses. GAA transistors, such as nanosheet transistors, are being investigated as alternatives to finFETs. In nanosheet transistors, the transistor's gate surrounds the channel (e.g., nanosheet channels or nanowire channels), effectively enclosing or surrounding the channel. This type of transistor offers the advantage of improved gate-to-channel electrostatic control, which also reduces leakage current.

[0078] To create more wiring space for integrated circuit (IC) structures with a large number of GAA transistors, back-side interconnects (e.g., back-side metal lines) connected to the back-side surfaces of the source / drain regions of GAA transistors using back-side metal vias are being investigated as an alternative to front-side interconnects formed on the front side of the source / drain regions of the transistors. While back-side interconnects offer significant improvements in reducing IC coverage, they are not universally satisfactory. For example, the contact resistance of GAA transistors with back-side vias may increase because the back-side silicide regions are formed at low temperatures to prevent damage to front-end-of-line (FEOL) devices (e.g., GAA transistors). Therefore, this disclosure provides, in various embodiments, fully encircling source / drain contacts that surround all sides of the epitaxial source / drain regions, thereby reducing contact resistance with the back-side vias.

[0079] Figures 1A to 13D These are top and cross-sectional views of an intermediate stage in the fabrication of an IC structure for a GAA device coupled to a back-side metal via, according to some embodiments of this disclosure. It should be understood that... Figures 1A to 13D Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some operations described below may be replaced or eliminated. The order of operations / processes is interchangeable.

[0080] Figure 1AA top view of an intermediate stage in the manufacturing of an IC structure, and Figure 1B For self Figure 1A The cross-sectional view obtained by section line A-A' in the diagram. Figure 1A and Figure 1B The diagram illustrates a semiconductor substrate 10. In some embodiments, substrate 10 may be a semiconductor substrate, such as a host semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like. Substrate 10 may include semiconductor materials, such as elemental semiconductors including Si and Ge; compound or alloy semiconductors, including SiC, SiGe, GeSn, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP; combinations thereof, or the like. Substrate 10 may be doped or substantially undoped. In a particular example, substrate 10 is a host silicon substrate, which may be a wafer.

[0081] The substrate 10 may include one or more buffer layers 100 (referred to as "buffer") in its surface region. The buffer layer 100 can be used to change the lattice constant from the lattice constant of the substrate 10 to the lattice constant of the subsequently formed multilayer stack. The buffer layer 100 may be formed of an epitaxially grown single-crystal semiconductor material, such as, but not limited to, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP.

[0082] Figure 1A and Figure 1B Further explanation is provided regarding the bottom sacrificial layer (referred to as "SL2") 104 formed on the buffer layer 100 and the multilayer epitaxial stack MS formed on the bottom sacrificial layer 104. The multilayer epitaxial stack MS includes one or more first semiconductor layers 101 alternating with one or more second semiconductor layers 102. For illustrative purposes, as discussed in more detail below, the first semiconductor layer 101 serves as the sacrificial layer to be removed, referred to as "SL1," and the second semiconductor layer 102 serves as a channel layer, referred to as "channel," which will be patterned to form the channel region of a GAA transistor.

[0083] In some embodiments, the bottom sacrificial layer 104 is formed of a material with high etch selectivity to the first semiconductor layer 101 and the second semiconductor layer 102. Therefore, etching operations performed on the first semiconductor layer 101 and the second semiconductor layer 102 will result in no or negligible etching in the bottom sacrificial layer 104, thus resulting in no or negligible consumption of the bottom sacrificial layer 104. In some embodiments, the thickness of the bottom sacrificial layer 104 differs from the thickness of the first semiconductor layer 101 and / or the thickness of the second semiconductor layer 102 because the bottom sacrificial layer 104 serves a different function than the first semiconductor layer 101 and the second semiconductor layer 102. Specifically, the bottom sacrificial layer 104 will be removed in a subsequent process and replaced with source / drain contact metal, and therefore the thickness of the bottom sacrificial layer 104 depends on the desired dimensions of the source / drain contacts. In some embodiments, the thickness of the bottom sacrificial layer 104 is greater than the thickness of the first semiconductor layer 101 and / or the thickness of the second semiconductor layer 102. In some embodiments, the thickness of the subsequently formed contact is greater than the thickness of the GAA channel (i.e., the thickness of the second semiconductor layer 102) and the sheet-to-sheet distance (i.e., the thickness of the first semiconductor layer 101). In some embodiments, the thickness of the bottom sacrificial layer 104 is greater than about 5 nm, for example, the thickness ranges from about 5 nm to about 100 nm.

[0084] In some embodiments, the bottom sacrificial layer 104 is a dielectric material, such as silicon oxynitride (SiOCN), which is more suitable for epitaxial growth of epitaxial materials than silicon oxide (SiO2). In some embodiments, the bottom semiconductor layer 101 of a multilayer stacked MS can be grown on the SiOCN layer using techniques such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). In some embodiments, prior to the deposition of the bottom semiconductor layer 101, the SiOCN layer undergoes surface preparation, which may include cleaning with organic solvents, etching, and annealing to provide a substantially contaminant-free surface conducive to epitaxial growth.

[0085] In some embodiments, the number of second semiconductor layers is 3 to 100. In some embodiments, the first semiconductor layer 101 and the second semiconductor layer 102 are made of different semiconductor materials selected from the group consisting of: Si, Ge, Sn, Si 1- x Ge x 、Ge 1-y Sn y Si 1-x-y Ge x Sn y, III-V compounds and their combinations. In some embodiments, the first semiconductor layer 101 and the second semiconductor layer 102 are formed by epitaxy. In some embodiments, SiGe is Si 1-x Ge x , where 0 < x < 1. In some embodiments, the sacrificial layer 101 is formed of an oxide material.

[0086] In some embodiments, the first semiconductor layer 101 is formed of boron-doped germanium (Ge:B) without silicon, and the second semiconductor layer 102 is formed of silicon germanium in which the percentage of germanium atoms is greater than the percentage of silicon atoms, for example, Ge 0.9 Si 0.1 formed. In some embodiments where the first semiconductor layer 101 is formed of boron-doped germanium (Ge:B), a dopant (such as boron) can be introduced into the first semiconductor layer 101 by in-situ doping during the epitaxial growth of the first semiconductor layer 101.

[0087] The first semiconductor layer 101 and the second semiconductor layer 102 can be formed by one or more epitaxy (epitaxy or epitaxial, epi) processes. Epitaxy processes include CVD deposition techniques (such as vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. The thickness of the sacrificial layer 101 depends on the target distance between the channel layers 102 (also referred to as the inter-sheet distance if the channel layers 102 are patterned into nanosheets) and the target distance between the bottommost channel layer 102 and the bottom sacrificial layer 104. For example, the thickness range of the sacrificial layer 101 is from about 3 nm to about 200 nm. The thickness of the channel layer 102 depends on the target thickness of the transistor channel (also referred to as the nanosheet thickness if the channel layer 102 is patterned into nanosheets). For example, the thickness range of the channel layer 102 is from about 1 nm to about 50 nm. In some embodiments, the thickness of each of the sacrificial layers 101 is different from (e.g., greater than) the thickness of each of the channel layers 102, which allows the inter-sheet distance to be different from (e.g., greater than) the sheet thickness. In some embodiments, the thickness of the first of the channel layers 102 is different from the second of the channel layers 102, which allows nanosheets with different thicknesses to coexist in the GAA transistor. In some embodiments, the thickness of the first of the sacrificial layers 101 is different from the second of the sacrificial layers 101, which allows different inter-sheet distances to coexist in the GAA transistor.

[0088] After the epitaxial growth process of the multi-layer stack MS is completed, a patterning process is performed on the multi-layer stack MS, the bottom sacrificial layer 104, and the buffer layer 100 to form a fin structure FS protruding from the substrate 10, such as Figure 1A and Figure 1B As described. In some embodiments, the patterning process includes a lithography process for forming a patterned mask, followed by one or more etching processes using the patterned mask as an etching mask. The one or more etching processes may include a wet etching process, an anisotropic dry etching process, or a combination thereof, and may use one or more etchants, which etch the multilayer stack MS, the bottom sacrificial layer 104, and the buffer layer 100 at a faster etching rate than etching the patterned mask. Although Figure 1B The illustrated fin structure FS has vertical sidewalls, but in some other embodiments, the etching process can result in the formation of tapered sidewalls.

[0089] Once the fin structure FS is formed, a shallow trench isolation (STI) region 103 (interchangeably referred to as an isolation insulation layer) is formed around the lower part of the fin structure FS. Figure 1A and Figure 1B The STI region 103 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trench around the fin structure FS, followed by recessing the top surface of the dielectric material. High-density plasma chemical vapor deposition (HDP-CVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), spin coating, and / or similar methods or combinations thereof can be used to deposit the dielectric material of the STI region 103. After deposition, an annealing or curing process can be performed. In some cases, the STI region 103 may include a pad, for example, a thermal oxide pad grown by oxidizing the fin structure FS and the silicon or silicon-germanium surface of the substrate 10. For example, the recessed process may use a planarization process (e.g., chemical mechanical polishing (CMP)) followed by a selective etching process (e.g., wet etching or dry etching, or a combination thereof), which can recess the top surface of the dielectric material in the STI region 103 such that the upper part of the fin structure FS protrudes from the surrounding insulating STI region 103.

[0090] Figure 2A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 2B For self Figure 2AThe cross-sectional view obtained by section line A-A' in the diagram. Figure 2A and Figure 2B In this configuration, a sacrificial dielectric layer 106 is deposited over the substrate 10, and a dummy gate structure 105 is then formed on the fin structure FS. In some embodiments, the longitudinal axis of the dummy gate structure 105 is perpendicular to the longitudinal axis of the fin structure FS. The sacrificial dielectric layer 106 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate structure 105 may be a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate structure 105 is formed, for example, by depositing a dummy gate material layer on the sacrificial dielectric layer 106; and subsequently patterning the dummy gate material layer into a separate dummy gate structure 105 using suitable lithography and etching techniques.

[0091] Figure 3A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 3B For self Figure 3A The cross-sectional view obtained by section line A-A' in the diagram. Figure 3A and Figure 3B In this embodiment, gate spacers 107o are formed on the sidewalls of the dummy gate structure 105. In some embodiments of the spacer formation step, a spacer material layer is deposited on the substrate 10. The spacer material layer may be a conformal layer, which is then etched back to form gate sidewall spacers. In the illustrated embodiment, the spacer material layer is conformally disposed on the top and sidewalls of the dummy gate structure 105. The spacer material layer may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. The spacer material layer can be formed by depositing the dielectric material on the dummy gate structure 308 using processes such as CVD, subatmospheric CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes. An isotropic etching is then performed on the deposited spacer material layer to remove the horizontal portions of the spacer material layer. The vertical portion of the spacer material layer on the sidewall of the virtual gate structure 105 can be retained to form a gate sidewall spacer, which is referred to as gate spacer 107o for simplicity.

[0092] After the gate spacer 107o is formed, for example in an anisotropic etching step, the exposed portion of the sacrificial dielectric layer 106 and the lower portion of the fin structure FS extending laterally beyond the dummy gate structure 105 and the gate spacer 107o are removed until the bottom sacrificial layer 104 is exposed. In some embodiments, an etchant is used to perform etching, which erodes the fin structure FS but hardly erodes the dummy gate structure 105, the gate spacer 107o, and the bottom sacrificial layer 104. In other words, the dummy gate structure 105, the gate spacer 107o, and the bottom sacrificial layer 104 have higher etch resistance to the etching process than the etch resistance of the fin structure FS. Therefore, the height of the dummy gate structure 105 and the gate spacer 107o, as well as the thickness of the sacrificial layer 107, are not reduced during the etching step.

[0093] After etching the fin structure FS, the sidewalls of the first semiconductor layer 101 of the fin structure FS are etched to form a sidewall recess R1 between the corresponding second semiconductor layers 102. Although the sidewalls of the first semiconductor layer 101 in the recess R1 are... Figure 3B The middle layer is described as straight, but the sidewalls can be concave or convex. Isotropic etching processes such as wet etching or similar methods can be used to etch the sidewalls. In some embodiments where the first semiconductor layer 101 comprises, for example, Ge:B and the second semiconductor layer 102 comprises, for example, SiGe with a higher silicon content than the first semiconductor layer 101, dry etching processes using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or similar methods can be used to etch the sidewalls of the first semiconductor layer 101.

[0094] After the first semiconductor layer 101 is laterally recessed, an internal spacer 107i is formed in the sidewall recess R1. The internal spacer 107i serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed on the exposed surface of the bottom sacrificial layer 104, and the first semiconductor layer 101 will be replaced by a high-k / metal gate structure in a subsequent process.

[0095] The internal spacer 107i is formed from an internal spacer layer, which is deposited using a conformal deposition process such as CVD, ALD, or similar methods. The internal spacer layer may contain materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k-value less than about 3.5. The internal spacer layer is then anisotropically etched to form the internal spacer 107i. Although the outer sidewalls of the internal spacer 107i are depicted as flush with the sidewalls of the channel layer 102, the outer sidewalls of the internal spacer 107i may extend beyond or be recessed from the sidewalls of the channel layer 102. Furthermore, although the outer sidewalls of the internal spacer 107i are... Figure 3BWhile described as straight, the outer sidewalls of the internal spacer 107i can be concave or convex. The internal spacer layer can be etched using anisotropic etching processes, such as RIE, NBE, or similar methods. The internal spacer 107i serves to prevent subsequent etching processes (such as etching processes used to form the gate structure) from damaging the subsequently formed source / drain regions.

[0096] Figure 4A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 4B For self Figure 4A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 4C For self Figure 4A The cross-sectional view obtained by section line B-B' in the diagram. Figures 4A to 4C In this configuration, epitaxial source / drain regions 108 are formed on the exposed surface of the bottom sacrificial layer 104 and on the opposite side of the channel layer 102. In some embodiments, the source / drain regions 108 may apply stress to the channel layer 102, thereby improving device performance. Figure 4B As described, the dummy gate structure 105 is disposed between each adjacent pair of epitaxial source / drain regions 108. In some embodiments, the gate spacer 107o is used to separate the epitaxial source / drain regions 108 from the dummy gate structure 105, and the inner spacer 107i is used to separate the epitaxial source / drain regions 108 from the first semiconductor layer 101 by an appropriate lateral distance, such that the epitaxial source / drain regions 108 do not short-circuit with the subsequently formed gate structure.

[0097] In some embodiments, the epitaxial source / drain region 108 includes Si, Ge, Sn, and Si 1-x Ge x Si 1-x-y Ge x Sn y Or similar. For example, the epitaxial source / drain region 108 may include silicon germanium, such as Si. 0.1 Ge 0.9 In some embodiments, the epitaxial source / drain region 108 may include any acceptable material suitable for an n-type FET. For example, if the channel layer 102 is silicon, the epitaxial source / drain region 108 may include a material that applies tensile strain to the channel layer 102, such as silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. In some embodiments, the epitaxial source / drain region 108 may include any acceptable material suitable for a p-type FET. For example, if the channel layer 102 is silicon, the epitaxial source / drain region 108 may include a material that applies compressive strain to the channel layer 102, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like.

[0098] The epitaxial source / drain regions 108 can be formed by implanting dopants, followed by an annealing process. The impurity concentration in the source / drain regions can be approximately 1 × 10⁸. 16 atoms / cm 3 With approximately 1×10 23 atoms / cm 3 Between. In some embodiments, the dopant is, for example, boron for an n-type FET and phosphorus for a p-type FET. The n-type and / or p-type impurities used for the source / drain regions can be any impurities discussed above. In some embodiments, the epitaxial source / drain regions 108 can be doped in situ during growth.

[0099] In some embodiments, the epitaxial source / drain region 108 may have a surface protruding from each of the upper surfaces of the upper channel layer 102, and may have a small facet. In some embodiments, such as Figure 4C As described, each of the epitaxial source / drain regions 108 has a serrated sidewall profile SP, including multiple upper slopes F1 and multiple lower slopes F2 that appear alternately. The upper slopes F1 face upward away from the substrate 10, and the lower slopes F2 face the substrate 10.

[0100] Figure 5A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 5B For self Figure 5A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 5C For self Figure 5A The cross-sectional view obtained by section line B-B' in the diagram. Figures 5A to 5C In this process, a self-aligned silicide process can be performed on the epitaxial source / drain regions 108 to form a metal silicide layer 109 on the exposed surfaces of the epitaxial source / drain regions 108. The metal silicide layer 109 can be used to reduce the contact resistance between the source / drain regions 108 and the subsequently formed source / drain contacts. In the self-aligned process, a thin layer of metal, such as nickel (Ni), cobalt (Co), or titanium (Ti), is deposited over the substrate 10, particularly on the exposed surfaces of the epitaxial source / drain regions 108. The substrate 10 with the metal layer then undergoes one or more annealing steps, for example at a temperature of 600°C or higher. This annealing process causes the metal to selectively react with the exposed semiconductor material (e.g., silicon) of the epitaxial source / drain regions 108, thereby forming the metal silicide layer 109 (e.g., TiSi, NiSi, or the like), while the metal on the dielectric material remains unreacted. The unreacted metal can then be selectively removed using wet or dry etching processes, leaving metal silicide layers 109 on the epitaxial source / drain regions 108, respectively.

[0101] In some embodiments, such as Figure 5CAs explained, the bottom surface F3 of the epitaxial source / drain region 108 is completely in contact with the bottom sacrificial layer 104, therefore the bottom surface F3 of the epitaxial source / drain region 108 is not covered by the metal silicide layer 109. In some embodiments, the bottom end of the metal silicide layer 109 may contact the sidewall surface of the bottom sacrificial layer 104. In some embodiments, such as Figure 5C As explained, the metal silicide layer 109 is conformally fitted to the epitaxial source / drain region 108, and therefore the metal silicide layer 109 also has a serrated sidewall profile that inherits the serrated sidewall profile of the epitaxial source / drain region 108. More specifically, the metal silicide layer 109 has multiple upper slopes and multiple lower slopes alternating.

[0102] Figure 6A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 6B For self Figure 6A The cross-sectional view obtained by section line A-A' in the diagram. Figure 6A and Figure 6B In one or more etching steps, the dummy gate structure 105, gate spacer 107o, and sacrificial dielectric layer 106 are removed, forming a gate trench GT1 between the epitaxial source / drain regions 108. In some embodiments, the dummy gate structure 105, gate spacer 107o, and sacrificial dielectric layer 106 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate structure 105 and gate spacer 107o at a faster rate than etching the internal spacer 107o. During removal, the sacrificial dielectric layer 106 may be used as an etch stop layer while etching the dummy gate structure 105 and / or gate spacer 107o. Subsequently, after removing the dummy gate structure 105, the sacrificial dielectric layer 106 may be removed. In some embodiments, prior to forming the gate trench GT1, a dielectric layer, such as an interlayer dielectric layer (ILD), may be formed on the metal silicide layer 109 to protect the metal silicide layer 109 and the underlying epitaxial source / drain region 108 from etching operations used to form the gate trench GT1. For example, the interlayer dielectric layer (ILD) may be formed by depositing one or more dielectric materials (e.g., silicon oxide) on the substrate 10, followed by performing a CMP process on the interlayer dielectric layer (ILD) to expose the dummy gate structure 105.

[0103] Figure 7A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 7B For self Figure 7A The cross-sectional view obtained by section line A-A' in the diagram. Figure 7A and Figure 7BIn this process, the sacrificial layer 101 exposed in the gate trench GT1 is removed using an isotropic etching process (e.g., wet etching or the like) with an etchant selective to the material of the sacrificial layer 101. In other words, the sacrificial layer 101 is removed using a selective etching process that etches the sacrificial layer 101 at a faster etch rate than etching the channel layer 102 and the bottom sacrificial layer 104, thereby creating spaces between the channel layers 102 (also referred to as inter-layer spaces if the channel layers 102 are nanosheets). This step may be referred to as a channel release process. In this intermediate processing step, the spaces between the channel layers 102 can be filled with ambient environmental conditions (e.g., air, nitrogen, etc.). In some embodiments, the channel layer 102 may be referred to as a nanosheet, nanowire, nanoplate, or nanoring with nanoscale dimensions (e.g., several nanometers), depending on its geometry. In some embodiments, the thickness of the channel layer 102 (also referred to as a nanosheet or nanostructure) ranges from about 1 nm to about 50 nm, and the width or diameter is from about 1 nm to about 50 nm. In some embodiments, the cross-sectional profile of the channel layer 102 may be rectangular, square, circular, elliptical, rhomboid, etc., with or without rounded corners.

[0104] Figure 8A A top view of an intermediate stage in the manufacturing of an IC structure, and Figure 8B For self Figure 8A The cross-sectional view obtained by section line A-A' in the diagram. Figure 8A and Figure 8B In this process, a portion of the sacrificial layer 104 exposed in the gate trench GT1 is replaced by a dielectric structure 114, while the remainder of the sacrificial layer 104 remains below the epitaxial source / drain region 108. The dielectric structure 114 is formed of a different material than the sacrificial layer 104, thus exhibiting etch selectivity towards the sacrificial layer 104. Therefore, the dielectric structure 114 can be used to define the boundary of the source / drain contacts, which will replace the remainder of the sacrificial layer 104 in subsequent processing. In some embodiments, the dielectric structure 114 is an oxide material, such as silicon oxide or other suitable oxide materials. In some embodiments, the dielectric structure 114 is formed, for example, by etching an opening O1 in the sacrificial layer 104 in the gate trench GT1, depositing an oxide material into the opening O1 in the sacrificial layer 104, and then selectively etching back the oxide material to form the dielectric structure 114, wherein the top surface of the dielectric structure 114 is not higher than the bottom surface of the bottommost inner spacer 107i.

[0105] Figure 9A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 9B For self Figure 9A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 9C For self Figure 9AThe cross-sectional view obtained by section line B-B' in the diagram. Figures 9A to 9C In this configuration, an alternative gate structure GS is formed in the gate trench GT1 to surround each nanosheet 102 suspended in the gate trench GT1. The gate structure GS may be the final gate of a GAA transistor. The final gate structure may be a high-k / metal gate stack, however other compositions are also possible. In some embodiments, the gate structure GS forms a gate associated with a multichannel provided by the plurality of nanosheets 102. For example, the high-k / metal gate structure GS is formed within the inter-chip space provided by the release of the nanosheets 102. In various embodiments, the high-k / metal gate structure GS includes an interface layer 110 formed around the nanosheets 102, a high-k gate dielectric layer 111 formed around the interface layer 110, one or more work function metal layers 112 formed around the high-k gate dielectric layer 111, and a fill metal layer 113 formed around the one or more work function metal layers 112 and filling the remainder of the gate trench GT1. The formation of a high-k / metal gate structure GS may include one or more deposition processes to form various gate materials, followed by an etch-back process to remove excess gate material, resulting in a high-k / metal gate structure GS having a top surface that is substantially flush with the top surface of the interlayer dielectric layer ILD.

[0106] In some embodiments, the interface layer 110 is formed of a high-k dielectric material, such as aluminum oxide (Al₂O₃) with a dielectric constant of about 9, which is greater than the dielectric constant of silicon oxide (about 3.9). In some embodiments, the high-k dielectric layer 111 is formed of another high-k dielectric material with a dielectric constant greater than that of the interface layer 110. For example, the high-k dielectric layer 111 is formed of zirconium oxide (ZrO₂) with a dielectric constant of about 40, titanium oxide (TiO₂) with a dielectric constant of about 95, yttrium oxide (Y₂O₃) with a dielectric constant of about 14 to about 18, tantalum oxide (Ta₂O₅) with a dielectric constant of about 26, or zirconium hafnium oxide (HZO) with a dielectric constant of about 20 to about 45.

[0107] In some embodiments, the work function metal layer 112 includes one or more n-type work function metal (N-metal) layers and / or one or more p-type work function metal (P-metal) layers. Examples of n-type work function metals include, but are not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminum compounds, and / or other suitable materials. Examples of p-type work function metals include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. In some embodiments, the filler metal 113 may include, but is not limited to, Pt, Ti, TiN, Al, W, WN, Ru, RuO, Ta, Ni, Co, Cu, Ag, Au, or other suitable materials.

[0108] like Figure 9B As described, the gate structure GS includes an upper gate portion GS1 located above the topmost nanosheet 102, and a plurality of lower gate portions GS2 located in the inter-chip space between corresponding nanosheets 102. In some embodiments, the lower gate portions GS2 may include a different material composition than the upper gate portions GS1. For example, the upper gate portion GS1 includes filler metal 113, while the lower gate portions GS2 may not contain filler metal 113. This is because the inter-chip space may have been filled with a work function metal layer 112 before the filler metal 113 is deposited. In some embodiments, the width of the upper gate portion GS1 is greater than the width of the lower gate portion GS2. This is because the gate spacer 107o is removed together with the dummy gate structure 105, while the internal spacer 107i remains between the corresponding nanosheets 102.

[0109] Figure 10A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 10B For self Figure 10A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 10C For self Figure 10A The cross-sectional view obtained by section line B-B' in the diagram. Figures 10A to 10C In this process, an etching process is performed on the interlayer dielectric layer (ILD) to form source / drain contact openings O2 extending through the interlayer dielectric layer (ILD) to expose the metal silicide layer 109 and the bottom sacrificial layer 104 below the epitaxial source / drain region 108.

[0110] Figure 11A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 11BFor self Figure 11A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 11C For self Figure 11A The cross-sectional view obtained by section line B-B' in the diagram. Figures 11A to 11C In this process, the bottom sacrificial layer 104 is removed using a selective etching process. This selective etching process etches the material of the bottom sacrificial layer 104 (e.g., SiOCN) at a faster etch rate than etching other materials (e.g., metal silicides) exposed in the source / drain contact openings O2, thereby forming bottom openings O3 directly beneath the respective epitaxial source / drain regions 108. This allows for the formation of source / drain contact metal that completely surrounds the epitaxial source / drain regions 108 in subsequent processing. In some embodiments, hydrofluoric acid (HF) and / or nitric acid (HNO3) can be used to selectively remove the bottom sacrificial layer 104 (e.g., SiOCN).

[0111] Figure 12A A top view of an intermediate stage in the manufacturing of an IC structure. Figure 12B For self Figure 12A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 12C For self Figure 12A The cross-sectional view obtained by section line B-B' in the diagram. Figures 12A to 12C In this embodiment, source / drain contacts 115 are formed in the source / drain contact opening O2 and the bottom opening O3. In some embodiments, the source / drain contacts 115 are formed by depositing one or more metal materials (e.g., Pt, Ti, TiN, Al, W, WN, Ru, RuO, Ta, Ni, Co, Cu, Ag, Au, or similar materials or combinations thereof) using a suitable deposition technique (e.g., CVD, PVD, ALD, or similar materials or combinations thereof) to overfill the source / drain contact opening O2 and the bottom opening O3, followed by performing a CMP process to remove excess metal material outside the source / drain contact opening O2.

[0112] Because the removal of the bottom sacrificial layer 104 forms a bottom opening O3 below the epitaxial source / drain region 108, the source / drain contact 115 can be formed in the source / drain contact opening O2 and the bottom opening O3 to completely surround the epitaxial region 108. Specifically, as... Figure 12CAs described, the source / drain contact 115 includes a top contact portion 115U located above the metal silicide layer 109, an intermediate contact portion 115M flush with and in contact with the serrated sidewall profile of the epitaxial source / drain region 108 and the metal silicide layer 109, and a bottom contact portion 115L located below the epitaxial source / drain region 108 and the metal silicide layer 109. The intermediate contact portion 115M extends from the top contact portion 115U to the bottom contact portion 115L and has a serrated profile conforming to the serrated sidewall profile of the epitaxial source / drain region 108. In particular, the intermediate contact portion 115M forms a serrated interface with the metal silicide layer 109, and the serrated interface conforms to the serrated sidewall profile of the epitaxial source / drain region 108. The bottom contact portion 115L overlaps and contacts the entire bottom surface F3 of the epitaxial source / drain region 108. The top contact portion 115U overlaps and contacts the entire top surface of the metal silicide layer 109. Therefore, the epitaxial source / drain region 108 can be completely surrounded within the source / drain contact 115, thereby reducing contact resistance.

[0113] Figure 12D According to some other embodiments, self Figure 12A The cross-sectional view obtained by section line B-B'. In addition to forming an additional back-side metal silicide layer 109' on the bottom surface F3 of the epitaxial source / drain region 108 before forming the source / drain contact 115, Figure 12D The structure described in the text and Figure 12C The structure described herein is substantially the same. In some embodiments, the metal silicide layer 109 and the underlying back metal silicide layer 109' together form a continuous metal silicide layer that continuously surrounds the top surface, bottom surface, and opposing serrated sidewalls of the epitaxial source / drain region 108. The back metal silicide layer 109' and the metal silicide layer 109 together completely surround the epitaxial source / drain region 108, and the source / drain contact 115 completely surrounds the back metal silicide layer 109' and the metal silicide layer 109, thereby reducing the contact resistance.

[0114] Figure 13A This is a plan view of an intermediate stage in the fabrication of an IC structure after the formation of the front interconnect structure 116 and the back interconnect structure 117. Figure 13B For self Figure 13A The cross-sectional view obtained by section line A-A' in the diagram, and Figure 13C For self Figure 13A The cross-sectional view obtained by section line B-B'. To clearly indicate section lines A-A' and B-B', Figure 13A The planar view is scaled down to the level of the gate structure GS, therefore Figure 13B The front interconnect structure described in the document is not in Figure 13A The front interconnect structure 116 may include one or more front interlayer dielectric layers ILD1 formed on the lower interlayer dielectric layer ILD, and one or more metal interconnects, such as front vias 116V extending vertically in the interlayer dielectric layer ILD1.

[0115] In some embodiments, the front-side via 116V may be formed using, for example, a single damascene process, a dual damascene process, or similar combinations thereof. In some embodiments, the front-side interlayer dielectric layer ILD1 may comprise a low-k dielectric material disposed between such conductive features, for example, with a k-value below about 4.0 or even 2.0. In some embodiments, the front-side interlayer dielectric layer ILD1 may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or SiO2. x C y It is made of spin-coated glass, spin-coated polymer, silicon oxide, silicon oxynitride, combinations thereof, or the like, and these materials are formed by any suitable method, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD, or the like. The front via 116V may contain metallic materials such as W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, combinations thereof, or the like.

[0116] In some embodiments, after forming the front interconnect structure 116, a back interconnect structure 117 is formed on the back side of the GAA transistor. For example, the substrate 10 and buffer layer 100 can be removed using, for example, a CMP process, a polishing process, or the like, to expose the bottom contact portion 115L of the source / drain contact 115. Next, a back interlayer dielectric layer ILD_B can be formed on the bottom contact portion 115L of the source / drain contact 115, and then a back via 117V can be formed in the back interlayer dielectric layer ILD_B to contact the bottom contact portion 115L of the source / drain contact 115. In some embodiments, the back-side via 117V is formed by, for example, etching a via that extends vertically through the back-side interlayer dielectric layer ILD_B; depositing one or more metal materials (e.g., Pt, Ti, TiN, Al, W, WN, Ru, RuO, Ta, Ni, Co, Cu, Ag, Au, or combinations thereof) that are overfilled using a suitable deposition technique (e.g., CVD, PVD, ALD, or similar combinations thereof); and then performing a CMP process to remove excess metal material outside the via.

[0117] exist Figure 13B In the IC structure, there is a front surface FS and a back surface BS opposite to the front surface FS. In the illustrated embodiment, the front surface FS is the top surface of the front interlayer dielectric layer ILD1, and the back surface BS is the bottom surface of the back interlayer dielectric layer ILD_B. Each component within the IC structure has a front surface facing the front surface FS and a back surface facing the back surface BS. In some embodiments, the back via 117V contacts the back surface (i.e., the bottom surface) of the source / drain contact 115 that completely surrounds the epitaxial source / drain region 108, thereby reducing contact resistance.

[0118] Figure 13D According to some other embodiments, self Figure 13A The cross-sectional view obtained by section line B-B'. Except for the formation of a back-side metal silicide layer 109' on the bottom surface F3 of the epitaxial source / drain region 108 before the formation of the source / drain contact 115, Figure 13D The structure described in the text is basically the same as Figure 13C The structure described herein is the same as previously discussed. Figure 12D The discussion.

[0119] Figure 14 A graph illustrating the current-voltage (IV) simulation results for transistors with different contact schemes. Figure 14 In the middle, the drain current (I D Plotted on the vertical axis, gate voltage (V) G Plotted on the horizontal axis. Curve C1 represents the IV characteristics of a transistor with a fully encircling source / drain contact 115 coupled to a back-side via 117V, as shown below. Figures 13C to 13D As explained in the diagram. In contrast, curve C2 represents the IV characteristics of the transistor coupled to the back-side via 117V without the fully surrounding source / drain contact 115. A comparative analysis based on curves C1 and C2 reveals that the transistor with the fully surrounding source / drain contact 115 exhibits improved drain current performance, indicating a reduction in contact resistance. This improvement is supported by the observed approximately 18% reduction in drain current without the fully surrounding source / drain contact 115.

[0120] In the foregoing embodiments, the IC structure includes a GAA transistor with a full-around source / drain contact. However, in some other embodiments, planar transistors, FinFETs, nanowire FETs, or complementary field-effect transistors (CFETs) may also be formed with full-around source / drain contacts. Based on the above discussion, it can be seen that this disclosure has many advantages. However, it should be understood that other embodiments may have additional advantages, and not all advantages are necessarily disclosed herein, and no particular advantage is necessary for all embodiments. One advantage is that a full-around contact increases the contact area, which in turn reduces the source / drain contact resistance, thus increasing the transistor's on-state current.

[0121] In some embodiments, a method includes: forming a bottom sacrificial layer on a substrate; forming an epitaxial structure on the bottom sacrificial layer; etching the epitaxial structure to expose the bottom sacrificial layer; forming an epitaxial source / drain region on the exposed bottom sacrificial layer; removing the bottom sacrificial layer from a bottom surface of the epitaxial source / drain region; and after removing the bottom sacrificial layer, forming a source / drain contact surrounding the bottom surface, a top surface, and opposing sidewalls of the epitaxial source / drain region. In some embodiments, the method further includes forming a silicide layer on the epitaxial source / drain region before forming the source / drain contact. In some embodiments, the source / drain contact surrounds the silicide layer. In some embodiments, a bottom surface of the source / drain contact is lower than a bottom end of the silicide layer. In some embodiments, the method further includes forming a back-side via, a top end of the back-side via contacting a bottom surface of the source / drain contact. In some embodiments, the method further includes forming a silicide layer on a bottom surface of the epitaxial source / drain region before forming the source / drain contact. In some embodiments, the source / drain region is in contact with a bottom surface of the silicide layer. In some embodiments, the epitaxial structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternating with the first semiconductor layers, and the bottom sacrificial layer is formed of a material different from the first semiconductor layers and the second semiconductor layers. In some embodiments, the method further includes removing the first semiconductor layer and forming a gate structure surrounding the second semiconductor layer. In some embodiments, a thickness of the bottom sacrificial layer is greater than a thickness of either the first semiconductor layer or the second semiconductor layer. In some embodiments, the bottom sacrificial layer is formed of silicon oxycarbon nitride (SiOCN).

[0122] In some embodiments, a method includes: forming an epitaxial stack on a substrate, the epitaxial stack including a plurality of channel layers; forming epitaxial source / drain regions on opposite sides of the epitaxial stack; forming a gate structure surrounding each of the plurality of channel layers; forming a gate structure surrounding each of the plurality of channel layers; and forming a source / drain contact on a first of the epitaxial source / drain regions. The source / drain contact extends from above a top surface of the first of the epitaxial source / drain regions to below a bottom surface of the first of the epitaxial source / drain regions. In some embodiments, the source / drain contact overlaps the entire bottom surface of the first of the epitaxial source / drain regions. In some embodiments, the source / drain contact overlaps the entire top surface of the first of the epitaxial source / drain regions. In some embodiments, the source / drain contact has a serrated profile conforming to a serrated sidewall profile of the first of the epitaxial source / drain regions. In some embodiments, the method further includes forming a back-side via below a bottom surface of the source / drain contact.

[0123] In some embodiments, a semiconductor device includes: a gate structure; epitaxial source / drain regions located on opposite sides of the gate structure; a first source / drain contact surrounding a top surface, a bottom surface, and an opposite side of the first epitaxial source / drain region; and a back-side via located below the first epitaxial source / drain region. The back-side via contacts a bottom surface of the first source / drain contact. In some embodiments, the device further includes a second source / drain contact surrounding a top surface, a bottom surface, and an opposite side of the second epitaxial source / drain region. In some embodiments, the device further includes a silicide layer contacting the top surface, the bottom surface, and the opposite side of the first epitaxial source / drain region. In some embodiments, the first source / drain contact and the silicide layer form a sawtooth interface.

[0124] In some embodiments, a semiconductor device includes a gate structure, an epitaxial source / drain region, and a source / drain contact. The epitaxial source / drain region is located on an opposite side of the gate structure. A source / drain contact is located on a first portion of the epitaxial source / drain region, extending from above a top surface of the first portion of the epitaxial source / drain region to below a bottom surface of the first portion of the epitaxial source / drain region. In some embodiments, the semiconductor device further includes a back-side via located below the first portion of the epitaxial source / drain region. In some embodiments, the back-side via contacts a bottom surface of the first source / drain contact.

[0125] In some embodiments, the semiconductor device includes a channel, a gate structure, epitaxial source / drain regions, and a first source / drain contact. The gate structure is located on the channel. The epitaxial source / drain regions are located on opposite sides of the channel. The first source / drain contact surrounds the entirety of a first portion of the epitaxial source / drain regions. In some embodiments, the semiconductor device further includes a second source / drain contact surrounding the entirety of a second portion of the epitaxial source / drain regions. In some embodiments, the semiconductor device further includes a silicide layer surrounding the entirety of the first portion of the epitaxial source / drain regions.

[0126] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A gate structure; The epitaxial source / drain regions are located on opposite sides of the gate structure; A first source / drain contact surrounds a top surface, a bottom surface, and an opposite side of the epitaxial source / drain region; and A back-side via is located below the first one in the epitaxial source / drain region, and the back-side via is in contact with a bottom surface of the first source / drain contact.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A second source / drain contact surrounds a top surface, a bottom surface, and an opposite side of a second epitaxial source / drain region.

3. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A silicide layer is in contact with the top surface, the bottom surface, and the opposite side of the first epitaxial source / drain region.

4. The semiconductor device as claimed in claim 3, characterized in that, The first source / drain contact forms a sawtooth interface with the silicide layer.

5. A semiconductor device, characterized in that, Include: A gate structure; The epitaxial source / drain regions are located on opposite sides of the gate structure; and A source / drain contact is located on a first one of the epitaxial source / drain regions, the source / drain contact extending above a top surface of the first one in the epitaxial source / drain region to below a bottom surface of the first one in the epitaxial source / drain region.

6. The semiconductor device as claimed in claim 5, characterized in that, Also includes: A back-side via is located below the first one in the epitaxial source / drain region.

7. The semiconductor device as claimed in claim 6, characterized in that, The back-side guide hole contacts a bottom surface of the first source / drain contact.

8. A semiconductor device, characterized in that, Include: One channel: A gate structure is located on this channel; The epitaxial source / drain regions are located on opposite sides of the channel; and A first source / drain contact, which surrounds the entirety of the first one in the epitaxial source / drain region.

9. The semiconductor device as claimed in claim 8, characterized in that, Also includes: A second source / drain contact surrounds the entirety of the second one in the epitaxial source / drain region.

10. The semiconductor device as claimed in claim 8, characterized in that, Also includes: A silicide layer surrounds the entirety of the first in the epitaxial source / drain region.

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