Package substrate and semiconductor package

Abstract

The utility model discloses a packaging substrate and a semiconductor package, and belongs to the technical field of semiconductor packaging. According to the invention, the core insulation structure is wrapped by six surfaces of the lamination insulation structure, so that the core insulation structure is completely wrapped by other insulation materials and is not in contact with the atmosphere, and the moisture absorption problem of the core insulation structure is effectively avoided; the used insulating material has the characteristics of insulation, oxygen insulation and moisture insulation, so that the reliability of the product is remarkably improved; according to the invention, a packaging mode without turning over is adopted, packaging can be directly completed, the technological process is simplified, and the packaging cost is reduced; meanwhile, the advantage that the core insulation structure can be provided with through holes with the diameter smaller than 10 micrometers is kept, the requirement of a thin circuit wiring layer is met, the thin circuit wiring layer in the wiring structure adopts a lamination insulation structure, the lowest layer connected with the reballing layer (the diameter of the through holes reaches 250 micrometers or above) can be mixed with other dielectric materials for use, and the optimal balance between the technical performance and the cost is achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate and semiconductor packaging. Background Technology

[0002] As electronic products evolve towards thinner, smaller, and higher-performance designs, semiconductor packaging technology is constantly innovating. Fan-out panel-level packaging (FOPLP), as an advanced packaging technology, has attracted considerable attention due to its ability to provide higher I / O density, better electrical performance, and smaller package size. In FOPLP technology, the packaging substrate acts as a bridge connecting the chip to external circuitry, and its structural design and material selection have a decisive impact on packaging performance and reliability.

[0003] Currently, common packaging substrates typically employ multi-layer structures, including a core layer and a stacked structure. However, several problems remain to be solved in existing technologies. In FOPLP advanced packaging, the commonly used PSPI (photosensitive polyimide) material is highly hygroscopic; exposure to the atmosphere can cause delamination of the RDL (redistribution layer), severely impacting product reliability. To address this issue, the industry has proposed a six-sided packaging solution, but this requires multiple processes (transfer, molding, polishing, and demolding), significantly increasing packaging costs. Furthermore, existing packaging substrate structures are insufficient in terms of high-density wiring and heat dissipation performance, making it difficult to meet the demands of high-performance electronic products.

[0004] Therefore, there is an urgent need to develop a new type of packaging substrate structure that can effectively solve the RDL delamination problem caused by moisture absorption of PSPI material, simplify the manufacturing process, reduce packaging costs, and meet the requirements of high-density wiring and good heat dissipation performance. Utility Model Content

[0005] The technical problem this invention aims to solve is to address the issue that in advanced FOPLP (Fan-Out Panel Level Packaging) packaging, the PSPI (Photosensitive Polyimide) material is extremely hygroscopic, and exposure to the atmosphere can cause RDL (Redistribution Layer) delamination, severely affecting product reliability. It also addresses the shortcomings of existing six-sided packaging solutions that require multiple processes (transfer, molding, grinding, and unpacking), leading to a significant increase in packaging costs. The invention provides a packaging substrate and semiconductor packaging.

[0006] This application discloses a packaging substrate, comprising:

[0007] The core insulation structure boasts the highest height.

[0008] A multilayer insulation structure covers the upper surface, lower surface and sidewalls of the core insulation structure, so that the core insulation structure is embedded in the multilayer insulation structure. The multilayer insulation structure has a first width, which is greater than the first height.

[0009] Multiple wiring structures extend through the core insulation structure and the multilayer insulation structure, and a first connection pad is provided on the lower surface of the wiring structure.

[0010] Optionally, the core insulation structure includes at least one first insulation layer.

[0011] Optionally, the first insulating layer is made of photosensitive polyimide.

[0012] Optionally, the thickness of the first insulating layer is between 3 μm and 20 μm.

[0013] Optionally, the multilayer insulation structure includes at least two second insulation layers.

[0014] Optionally, the second insulating layer is made of Ajinomoto additive material.

[0015] Optionally, the thickness of the second insulating layer is between 15 μm and 50 μm.

[0016] Optionally, the wiring structure is connected to an external connection terminal via a first connection pad.

[0017] Optionally, the first width is the vertical distance between the sidewall of the core insulation structure and the outer edge of the multilayer insulation structure.

[0018] This application provides a semiconductor package, including: a chip, an interposer, multiple connectors and a molding compound, and also includes the above-mentioned package substrate;

[0019] The upper surface of the wiring structure is provided with a second connection pad;

[0020] The interposer layer is located between the packaging substrate and the chip, and the interposer layer has a vertical interconnect structure inside, which is electrically connected to the connector.

[0021] The connector extends through the interposer layer and connects the second connection pad to the chip.

[0022] The molding compound encapsulates the chip and partially covers the upper surface of the packaging substrate.

[0023] In this application, a multilayered insulation structure is used to cover the core insulation structure on all six sides, completely encapsulating the core insulation structure within other insulating materials and preventing it from contacting the atmosphere, thus effectively avoiding the moisture absorption problem of the core insulation structure. The insulating materials used have the characteristics of being insulating, oxygen-proof, and moisture-proof, significantly improving product reliability. This application adopts a packaging method that does not require a flip-board, allowing for direct packaging, simplifying the process and reducing packaging costs. At the same time, it maintains the advantage of the core insulation structure being able to have vias smaller than 10µm, meeting the requirements of fine-line routing layers. In the wiring structure, the fine-line routing layer uses a multilayered insulation structure, while the bottommost layer connecting the ball (with via diameters of 250µm or more) can use a mixture of other dielectric materials, achieving an optimal balance between technical performance and cost. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0025] Figure 1 This is a cross-sectional view of one embodiment of the semiconductor package described in this application. Detailed Implementation

[0026] The advantages of this application are further illustrated below with reference to the accompanying drawings and specific embodiments.

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0028] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0029] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0030] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.

[0031] The following terms are used in this document.

[0032] FOPLP (Fanout panel level package): Fanout panel level package;

[0033] PSPI (Photosensitive Polyimide): Photosensitive polyimide;

[0034] ABF (Ajinomoto Build-up Film): Ajinomoto's build-up material

[0035] RDL (redistribution layer): redistribution layer;

[0036] PLP (panel-level package): Panel-level package;

[0037] Molding compound: molding compound / molding material.

[0038] Example 1

[0039] See Figure 1 As shown, a packaging substrate includes a core insulating structure 2, a multilayer insulating structure 1, and multiple wiring structures 3.

[0040] The core insulating structure 2 has a first height 'a', and the core insulating structure 2 includes at least one first insulating layer. The first insulating layer is made of photosensitive polyimide material. The thickness of the first insulating layer is between 3 μm and 20 μm, and can be a specific value such as 3 μm, 10 μm, 15 μm, or 20 μm. In a preferred embodiment, the thickness of the first insulating layer is 10 μm.

[0041] The laminated insulation structure 1 covers the upper surface, lower surface, and sidewalls of the core insulation structure 2, so that the core insulation structure 2 is embedded within the laminated insulation structure 1. The laminated insulation structure 1 has a first width b, which is greater than a first height a. Here, the first width b refers to the vertical distance between the sidewall of the core insulation structure 2 and the outer edge of the laminated insulation structure 1. The laminated insulation structure 1 includes at least two second insulation layers. The second insulation layers are made of Ajinomoto additive material. The thickness of the second insulation layer is between 15μm and 50μm, and can be a specific value such as 15μm, 25μm, 35μm, or 50μm. In a preferred embodiment, the thickness of the second insulation layer is 30μm. The thickness of the laminated insulation structure 1 located below the core insulation structure 2 is between 15μm and 50μm, and can be a specific value such as 15μm, 20μm, 35μm, or 45μm. In a preferred embodiment, the thickness c of the laminated insulation structure 1 located below the core insulation structure 2 is 25μm.

[0042] Multiple wiring structures 3 penetrate the core insulation structure 2 and the multilayer insulation structure 1, and a first connection pad 31 is provided on the lower surface of the wiring structure. The wiring structure is connected to external connection terminals through the first connection pad 31. This design enables the packaging substrate to achieve electrical connection functions while maintaining structural stability and reliability.

[0043] In this packaging substrate structure design, the core insulating structure 2 is completely embedded inside the multilayer insulating structure 1, forming an integrated structure, which improves the mechanical strength and stability of the packaging substrate. At the same time, by rationally designing the structural ratio of the first width b being greater than the first height a, the packaging substrate has sufficient space in the horizontal direction to accommodate more wiring structures, improving wiring density and wiring flexibility.

[0044] The wiring structure runs through the core insulation structure 2 and the multilayer insulation structure 1, and is connected to the external connection terminal through the first connection pad 31, realizing an effective connection between the internal and external circuits of the packaging substrate. This design not only simplifies the manufacturing process of the packaging substrate, but also improves the electrical performance and reliability of the packaging substrate.

[0045] In this embodiment, by using ABF (or other dielectric materials with insulating, oxygen- and water-resistant properties) to cover the PSPI on all six sides, the PSPI is completely encapsulated in other insulating materials and does not come into contact with the atmosphere, effectively avoiding the moisture absorption problem of the PSPI. The insulating materials used have insulating, oxygen- and water-resistant properties, which significantly improves product reliability. This application adopts a packaging method that does not require a flip-board, which can directly complete the packaging process, simplifying the process and reducing packaging costs. At the same time, it maintains the advantage of PSPI being able to form vias smaller than 10um, meeting the requirements of fine-line routing layers. In the RDL, the fine-line routing layer uses photosensitive dielectric materials such as PSPI, while the bottommost layer connecting the ball-mounted structure (with via diameters of 250um or more) can use a mixture of other dielectric materials, achieving an optimal balance between technical performance and cost.

[0046] Example 2

[0047] See Figure 1 As shown, a semiconductor package includes a packaging substrate, a chip 5, an interposer 6, multiple connectors 7, and a molding compound 4.

[0048] The packaging substrate includes a core insulating structure 2, a multilayer insulating structure 1, and multiple wiring structures 3. The core insulating structure 2 has a first height 'a' and includes at least one first insulating layer. The first insulating layer is made of photosensitive polyimide, and its thickness is between 3 μm and 20 μm. The multilayer insulating structure 1 covers the upper surface, lower surface, and sidewalls of the core insulating structure 2, embedding the core insulating structure 2 within it. The multilayer insulating structure 1 has a first width 'b', which is greater than the first height 'a'. The multilayer insulating structure 1 includes at least two second insulating layers, which are made of Ajinomoto additive material, and their thickness is between 15 μm and 50 μm. The multilayer insulating structure 1 located below the core insulating structure 2 has a thickness of 15 μm to 50 μm. Multiple wiring structures 3 penetrate the core insulating structure 2 and the multilayer insulating structure 1. A first connecting pad 31 is provided on the lower surface of each wiring structure, and a second connecting pad is provided on the upper surface of each wiring structure. The wiring structure is connected to the external connection terminal via the first connection pad 31. The wiring structure is made of electroplated copper.

[0049] Interposer 6 is located between the package substrate and chip 5. Vertical interconnect structures are embedded within interposer 6 for electrical connection of connectors 7. Interposer 6 is filled with adhesive. The width of the vertical interconnect structure is less than 100 μm. This design allows for higher density electrical connections within a limited space, improving the integration of the package.

[0050] Connector 7 extends through the interposer layer 6 and connects the second bonding pad to the chip 5. Connector 7 uses bumps or solder balls, with the bump diameter between 250μm and 300μm and the solder ball diameter between 250μm and 300μm. This size of connector 7 provides sufficient mechanical strength and electrical connection performance while maintaining appropriate spacing to avoid short-circuit risks.

[0051] The molding compound 4 encapsulates the chip 5 and partially covers the upper surface of the packaging substrate. The molding compound 4 protects the chip 5 and the interconnect structure, preventing damage to the chip 5 from the external environment, while also providing mechanical support and enhancing the structural stability of the entire package.

[0052] In a preferred embodiment, the semiconductor package further includes at least one surface-mount passive component disposed on the upper surface of the multilayer insulating structure 1 and electrically connected to the wiring structure. These passive components may be resistors, capacitors, or inductors, etc., which work in conjunction with the chip 5 to optimize circuit performance, reduce signal interference, and improve the overall electrical characteristics of the package.

[0053] This semiconductor packaging structure, through the combined design of the core insulating structure 2 and the multilayer insulating structure 1, provides better mechanical strength and thermal stability. The vertical interconnect structure in the interposer layer 6 and the connector 7 together form an efficient electrical path, ensuring a reliable connection between the chip 5 and the packaging substrate. The overall design achieves high-density, high-reliability semiconductor packaging, suitable for integrated circuit applications in various electronic devices.

[0054] Finally, it should be noted that the above description is only a preferred embodiment of this application and is not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A packaging substrate, characterized in that, include: The core insulation structure boasts the highest height. A multilayer insulation structure covers the upper surface, lower surface and sidewalls of the core insulation structure, so that the core insulation structure is embedded in the multilayer insulation structure. The multilayer insulation structure has a first width, which is greater than the first height. Multiple wiring structures extend through the core insulation structure and the multilayer insulation structure, and a first connection pad is provided on the lower surface of the wiring structure.

2. The packaging substrate according to claim 1, characterized in that, The core insulation structure includes at least one first insulation layer.

3. The packaging substrate according to claim 2, characterized in that, The first insulating layer is made of photosensitive polyimide.

4. The packaging substrate according to claim 2 or 3, characterized in that, The thickness of the first insulating layer is between 3 μm and 20 μm.

5. The packaging substrate according to claim 1, characterized in that, The multilayer insulation structure includes at least two second insulation layers.

6. The packaging substrate according to claim 5, characterized in that, The second insulating layer uses Ajinomoto additive material.

7. The packaging substrate according to claim 5 or 6, characterized in that, The thickness of the second insulating layer is between 15 μm and 50 μm.

8. The packaging substrate according to claim 1, characterized in that, The wiring structure is connected to external connection terminals via a first connection pad.

9. The packaging substrate according to claim 1, characterized in that, The first width is the vertical distance between the sidewall of the core insulation structure and the outer edge of the multilayer insulation structure.

10. A semiconductor package, comprising: A chip, an interposer, multiple connectors, and a molding compound, characterized in that it further includes the packaging substrate according to any one of claims 1-8; The upper surface of the wiring structure is provided with a second connection pad; The interposer layer is located between the packaging substrate and the chip, and the interposer layer has a vertical interconnect structure inside, which is electrically connected to the connector. The connector extends through the interposer layer and connects the second connection pad to the chip. The molding compound encapsulates the chip and partially covers the upper surface of the packaging substrate.

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