Semiconductor structure

Abstract

The utility model provides a semiconductor structure. The semiconductor structure includes: a substrate; a gate structure whose lowest surface covers a central portion of the substrate; a first source / drain feature and a second source / drain feature surrounding a central portion of the substrate; a first source / drain contact over the first source / drain feature; and a second source / drain contact over the second source / drain feature; the lowest surface of the gate structure is directly located between the first source / drain contact and the second source / drain contact.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure. Background Technology

[0002] The electronics industry has a growing demand for smaller, faster electronic devices capable of supporting increasingly complex and sophisticated functions. Consequently, the semiconductor industry is increasingly focused on manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, this demand has been largely met by shrinking the size of semiconductor ICs (e.g., minimizing feature size), thereby increasing production efficiency and reducing costs. However, this scaling also increases the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar progress in semiconductor manufacturing processes and technologies.

[0003] To improve gate control, reduce open-circuit current, and mitigate the short-channel effect (SCE) by increasing gate-channel coupling, multi-gate devices have been introduced. One such multi-gate device is the fin field-effect transistor (FinFET). FinFET gets its name from its fin-like structure, which extends from the substrate to form the FET channel. Another multi-gate device is the gate-all-around (GAA) transistor, partly to address the performance challenges associated with FinFET. GAA devices are named for their gate structure, which extends completely around the channel, providing better electrostatic control than FinFET. Both FinFET and GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes. Furthermore, the three-dimensional structure of these devices allows for significant scaling while maintaining gate control and reducing short-channel effects. Utility Model Content

[0004] Another embodiment of this disclosure provides a semiconductor structure, the semiconductor structure including: a substrate; a gate structure, the lowest surface of which covers a central portion of the substrate; a first source / drain feature and a second source / drain feature surrounding the central portion of the substrate; a first source / drain contact located above the first source / drain feature; and a second source / drain contact located above the second source / drain feature; and the lowest surface of the gate structure is directly located between the first source / drain contact and the second source / drain contact.

[0005] Another embodiment of this disclosure provides a semiconductor structure comprising: a gate-all-around (GAA) structure including an outer gate portion, the outer gate portion being covered by a stack of vertically spaced inner gate portions separated by semiconductor nanosheets; and a vertically extending metal contact laterally adjacent to the outer gate portion and the stack of vertically spaced inner gate portions; wherein the stack of vertically spaced inner gate portions includes an uppermost inner gate portion; and wherein an epitaxial material of 0 to 2 nanometers is directly located between the uppermost inner gate portion and the vertically extending metal contact.

[0006] In another embodiment, a semiconductor structure is provided, comprising: a substrate; a gate structure, the lowest surface of which covers a central portion of the substrate; a first source / drain feature and a second source / drain feature surrounding the central portion of the substrate; a first source / drain contact located above the first source / drain feature; and a second source / drain contact located above the second source / drain feature. The first and second source / drain features each have a U-shaped cross-section, including an outer corner and an inner corner, wherein the inner corner is adjacent to the gate structure and located between the gate structure and the outer corner, and the lowest surface of the gate structure is directly located between the first and second source / drain contacts. Attached Figure Description

[0007] The best understanding of the various features disclosed herein can be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for ease of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a layout plan view of a multi-gate device according to some embodiments;

[0009] Figure 2 The flowchart illustrates a method according to some embodiments;

[0010] Figures 3 to 24 According to Figure 2 The method is a cross-sectional view of a semiconductor device during the continuous stages of manufacturing.

[0011] [Symbol Explanation]

[0012] 10: Substrate / Semiconductor Substrate

[0013] 11: Lattice unit

[0014] 20: Parallel Active Region

[0015] 30: Parallel gate line

[0016] 100: Semiconductor devices / Multi-gate devices / P-type metal-oxide-semiconductor devices / N-type metal-oxide-semiconductor multi-gate devices / FinFET devices / Gate all-around (GAA) devices

[0017] 200: Semiconductor device / Gate all-around (GAA) device / Multi-gate device / Device

[0018] 202:Substrate

[0019] 205: Central Section

[0020] 212: Epitaxial Stacking

[0021] 214: Epitaxial layer

[0022] 216: Epitaxial layer

[0023] 217: Masking layer

[0024] 218: First masking layer

[0025] 219: Second masking layer

[0026] 220: Fins

[0027] 220a: Partial

[0028] 221: Shallow Trench Isolation (STI) Feature / Isolation Feature

[0029] 222: Sacrificial gate structure

[0030] 223: Sacrificial gate dielectric

[0031] 224: Sacrificial gate electrode

[0032] 225: Masking layer

[0033] 226: Masking layer

[0034] 227: Masking layer

[0035] 230: Spacer

[0036] 231: Lining layer

[0037] 232: Main Spacing Layer

[0038] 233: Bottom gap surface

[0039] 234: Gap / Groove

[0040] 235: Fin Fragment

[0041] 300: Isolation layer

[0042] 400: Source / Drain Characteristics

[0043] 411:Inner corner

[0044] 412:Outer corner

[0045] 421: Lowest point

[0046] 422: Upper end

[0047] 431:External surface

[0048] 432: Internal surface

[0049] 433: Horizontal plane

[0050] 440: Dielectric Pad

[0051] 450: Dielectric / Interlayer Dielectric (ILD) Layer

[0052] 499: Gate cavity

[0053] 500: Gate structure

[0054] 501: Gate Structure

[0055] 502: Gate structure

[0056] 503: Gate Structure

[0057] 510: Upper gate / outer gate section

[0058] 520: Internal gate portion

[0059] 521: Lowest internal gate portion / Internal gate portion

[0060] 522: Intermediate internal gate portion / Internal gate portion

[0061] 523: Topmost internal gate portion / Internal gate portion

[0062] 540: Gate dielectric layer

[0063] 550: Gate electrode material

[0064] 560: Semiconductor nanosheets / channel regions / nanofashelves

[0065] 561: Lowest level nanosheets / nanofiber

[0066] 562: Intermediate Nanosheets / Nanosheets

[0067] 563: Top layer nanosheets / nanofiber

[0068] 569: Sidewall

[0069] 599: Upper surface

[0070] 600: Floor

[0071] 700: Second Interlayer Dielectric (ILD) Layer

[0072] 720: Upper opening

[0073] 730: Sidewall

[0074] 780: Trench

[0075] 781: Bottom Surface

[0076] 782: Horizontal plane

[0077] 783: Horizontal plane

[0078] 784: First end

[0079] 785: Second End

[0080] 800: Source / Drain contact / Conductive contact / Connection

[0081] 801: Upper part

[0082] 810: Silicide

[0083] 820: Metal filler

[0084] 825: Protrusion

[0085] 826: Wall

[0086] 832:External surface

[0087] 833: Horizontal plane

[0088] 896: Horizontal center line

[0089] 897: Line

[0090] 898: Vertical center line

[0091] 899: Line

[0092] 900: Interconnection Structure

[0093] 910: Dielectric layer

[0094] 920: Metallization layer

[0095] 1000: Method

[0096] 2161: Groove

[0097] 2162: Internal spacer

[0098] 2169: Gap

[0099] 5211: Lowest Surface

[0100] 5611: Lowest Surface

[0101] A1:Angle

[0102] A2: Angle

[0103] B1, B2, B3: Vertical distance

[0104] D1: Distance

[0105] F1, F2, F3: Vertical distance

[0106] L1, L2, L3: Vertical distance

[0107] S1, S2, S3: Vertical distance

[0108] S1010: Operation

[0109] S1020: Operation

[0110] S1030: Operation

[0111] S1040: Operation

[0112] S1050: Operation

[0113] S1060: Operation

[0114] S1070: Operation

[0115] S1080: Operation

[0116] S1090: Operation

[0117] S1110: Operation

[0118] S1120: Operation

[0119] S1130: Operation

[0120] S1140: Operation

[0121] S1150: Operation

[0122] S1160: Operation

[0123] S1170: Operation

[0124] S1171: Operation

[0125] S1172: Operation

[0126] S1173: Operation

[0127] S1180: Operation

[0128] S1190: Operation

[0129] S1200: Operation

[0130] T1, T2, T3: Vertical distance

[0131] U1, U2, U3: Vertical distance

[0132] W0, W1, W2, W3: Lateral width Detailed Implementation

[0133] The following disclosure provides numerous different embodiments or instances for implementing various features of this subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, forming a first feature on a second feature can include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, this disclosure may repeatedly reference numbers and / or letters in various instances. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0134] Furthermore, for ease of description, spatial relative terms such as "above," "overlapping," "above," "upper," "top," "below," "under," "below," "lower," "bottom," and "side" are used herein to describe the relationship between an element or feature and another element or feature shown in the figures. In addition to the orientations described in the figures, spatial relative terms also include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0135] In some embodiments herein, a “material layer” is a layer comprising at least 50% by weight of the identified material, such as at least 60% by weight, at least 75% by weight, or at least 90% by weight, or substantially 100% by weight of the identified material; and a “material” layer comprising at least 50% by weight, such as at least 60% by weight, at least 75% by weight, or at least 90% by weight, or substantially 100% by weight of the identified material. For example, in some embodiments, a titanium nitride layer and each of the titanium nitride layers is at least 50% by weight, at least 60% by weight, at least 75% by weight, at least 90% by weight, or at least 95% by weight, or substantially 100% by weight of titanium nitride.

[0136] For the sake of brevity, this document may not describe in detail the known techniques associated with the manufacture of conventional semiconductor devices. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionality not described in detail herein. In particular, the various processes in semiconductor device manufacture are well-known; therefore, for the sake of brevity, many known processes will only be briefly mentioned herein, or omitted entirely without providing details of well-known processes. Those skilled in the art will readily recognize upon a full reading of this disclosure that the structures disclosed herein can employ a variety of techniques and can be incorporated into various semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of components, and a single component shown in a figure may represent multiple components.

[0137] Figure 1 The lattice unit 11 is described as a portion of the semiconductor substrate 10 in the semiconductor device 100. As shown, the parallel active regions 20 are spaced apart from each other and extend along the X direction. Furthermore, the parallel gate lines 30 are spaced apart from each other and extend in the Y direction perpendicular to the X direction. The exemplary parallel gate lines 30 are formed of a conductive material (such as a metal) and constitute the gate structure of the semiconductor device 100.

[0138] The semiconductor device 100 may be a multi-gate device 100. In various embodiments, the multi-gate device 100 may include a FinFET device, a GAA transistor, or other types of multi-gate devices. The multi-gate device 100 is formed on the substrate 10.

[0139] Multi-gate device 100 may include a P-type metal-oxide-semiconductor device 100 or an N-type metal-oxide-semiconductor multi-gate device 100. Specific examples are described herein and referred to as FinFET device 100 due to its fin-like structure. An embodiment of a multi-gate transistor referred to as a gate-all-around (GAA) device 100 is also described herein. GAA device 100 includes any device in which a gate structure or a portion thereof is formed on all four sides of a channel region (e.g., surrounding a portion of the channel region). Devices described herein also include embodiments having channel regions configured in nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. Here, the terms "nanosheet" or "nanosheet channel" are intended to include nanowire channel and strip channel configurations.

[0140] In some embodiments, substrate 10 may be a semiconductor substrate, such as a silicon substrate. Substrate 10 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 10 may include various doping configurations, depending on design requirements known in the art. Substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Additionally, substrate 10 may also include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 10 may optionally include an epitaxial layer, which may be strained to improve performance, and may include a silicon-on-insulator (SOI) structure, and / or have other suitable reinforcing features.

[0141] This document describes embodiments of devices with one or more channel regions (such as nanosheets) associated with a gate structure. For example, a stack of vertically spaced nanosheet channels can be provided. However, those skilled in the art will recognize that this teaching is applicable to a single channel (e.g., a single nanosheet) or any number of channels. Other examples of semiconductor devices that can benefit from the various embodiments disclosed herein will be apparent to those skilled in the art.

[0142] In some embodiments, conductive contacts are formed in contact with source / drain features. As used herein, “source / drain region” or “source / drain feature” may refer to either the source or the drain, and may refer to either one or both depending on the context.

[0143] Furthermore, a conductive path from the source / drain junction to the channel region (such as a nanosheet channel or a stack of nanosheet channels) can reduce resistance. Specifically, the method described herein provides a direct, shortest conductive path from the source / drain junction to the channel region. For example, in the embodiments disclosed herein, the source / drain features are partially recessed, and the source / drain junction is directly adjacent to and formed at the same height as the nanosheet channel region. For example, a direct lateral horizontal path from the source / drain junction to the nanosheet channel is provided. Additionally, the lateral distance between the source / drain junction and each nanosheet channel can be minimized by removing or reducing the number of source / drain features located between the source / drain junction and each nanosheet channel.

[0144] In some embodiments, the methods described herein can prevent the current coating. Therefore, device performance is improved or enhanced compared to devices where the current path must pass vertically and horizontally through the source / drain feature material between the source / drain contact and the channel region.

[0145] Compared with the prior art, the embodiments disclosed herein have advantages, but it should be understood that other embodiments may have different advantages. Not all advantages are necessarily discussed herein, nor is it required that all embodiments have specific advantages.

[0146] See Figure 2 The illustration depicts a method 1000 for manufacturing a semiconductor device 200 (such as a multi-gate device 100) according to various embodiments. The method 1000 will be discussed below with reference to a GAA device 200 having a channel region, which may be referred to as a nanosheet or nanosheet channel, and may include various geometries (such as cylindrical, strip-shaped) and sizes. However, it should be understood that various embodiments of method 1000 can also be applied to other types of multi-gate devices without departing from the scope of this disclosure. In some embodiments, method 1000 can be used to manufacture the device referenced above. Figure 1 The multi-gate device 100 is described above. Therefore, one or more states discussed above with reference to the multi-gate device 100 can also be applied to method 1000. It should be understood that method 1000 includes steps with complementary metal-oxide-semiconductor (CMOS) technology process flow characteristics, and therefore will only be briefly described here. In addition, other steps may be performed before, after and / or during method 1000.

[0147] The following will refer to Figures 3 to 24 Description method 1000, Figures 3 to 24 A perspective view of the multi-gate device 200 is provided, showing the multi-gate device 200 along the line with... Figure 1 A cross-sectional view of a plane substantially parallel to the planes defined by the X and Z axes, and the multi-gate device 200 along the plane defined by the X and Z axes. Figure 1 A cross-sectional view of a plane substantially parallel to the planes defined by the Y-axis and Z-axis, as described, illustrates the various stages of manufacturing according to method 1000.

[0148] Furthermore, the semiconductor device 200 may include various other devices and features, such as other types of devices like additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random-access memory (SRAM), and / or other logic circuits, but these have been simplified for a better understanding of the concepts disclosed herein. In some embodiments, the semiconductor device 200 includes multiple semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., which may be interconnected. It should also be noted that the process steps of method 1000, including any descriptions given with reference to the figures, are merely illustrative and are not intended to limit the scope of the specific descriptions beyond those specifically described in the following claims.

[0149] In operation S1010, method 1000 provides substrate 202, such as Figure 3As shown. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 202 may include various doping configurations, depending on design requirements known in the art. For example, different doping profiles (e.g., p-wells, n-wells) may be formed on substrate 202 in regions designed for different device types (e.g., n-type field-effect transistors, p-type field-effect transistors, PFETs). Suitable doping may include ion implantation and / or diffusion processes of dopants, such as boron (B) for p-wells and phosphorus (P) for n-wells. In some embodiments, substrate 202 includes at least a single-crystal semiconductor layer on its surface. Substrate 202 may contain single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 202 may also include compound semiconductors and / or alloy semiconductors. In the illustrated embodiment, substrate 202 is made of crystalline silicon.

[0150] like Figure 3 As shown, in operation S1020, method 1000 ( Figure 2 One or more epitaxial layers are formed on substrate 202. In some embodiments, an epitaxial stack 212 is formed on substrate 202. Epitaxial stack 212 includes an epitaxial layer 214 of a first composition sandwiched between epitaxial layers 216 of a second composition. The first and second compositions may be different. Possible embodiments include those where the first and second compositions have different oxidation rates and / or etch selectivity. In one embodiment, epitaxial layer 216 is SiGe and epitaxial layer 214 is silicon. In embodiments where epitaxial layer 216 comprises silicon-germanium and epitaxial layer 214 comprises silicon, the oxidation rate of silicon is less than that of silicon-germanium. It should be noted that Figure 3 The description of three epitaxial layers 214 and 216 is for illustrative purposes only and does not limit the specific content described in the claims. It should be understood that any number of epitaxial layers can be formed in the epitaxial stack 212; the number of layers depends on the number of channel regions required by the GAA device 200. In some embodiments, the number of epitaxial layers 216 is between 2 and 10, for example, 6 or 7.

[0151] In some embodiments, the thickness of epitaxial layer 216 ranges from about five nanometers to about fifteen nanometers. The thickness of epitaxial layer 216 can be substantially uniform. In some embodiments, the thickness of epitaxial layer 214 ranges from about five nanometers to about fifteen nanometers. In some embodiments, the stacked epitaxial layers 214 have substantially uniform thickness. As described below, epitaxial layer 214 can be used as a channel region for a subsequently formed multi-gate device, and its thickness is selected according to device performance. Epitaxial layer 216 can be used as a gap between adjacent channel regions of a subsequently formed multi-gate device, and its thickness is selected according to device performance.

[0152] For example, the epitaxial growth of the epitaxial stack 212 can be accomplished using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer (such as epitaxial layer 216) comprises the same material as the substrate 202. In some embodiments, epitaxial layers 214 and 216 comprise materials different from the substrate 202. As described above, in at least some embodiments, epitaxial layer 216 comprises epitaxially grown Si. 1-x Ge x The epitaxial layer 214 comprises an epitaxially grown silicon (Si) layer (where x is from about 10% to about 55%). Alternatively, in some embodiments, either of the epitaxial layers 214 and 216 may comprise other materials, such as germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInp and / or GaInAsP, or combinations thereof. As described above, the materials of the epitaxial layers 214 and 216 may be selected based on different oxidation and etch selectivity characteristics. In various embodiments, the epitaxial layers 214 and 216 are substantially dopant-free (i.e., having a dopant content of about 0 cm⁻¹). -3 To approximately 1×10 17 cm -3 The concentration of foreign doping is controlled, for example, no intentional doping is performed during the epitaxial growth process. In some embodiments, the bottom and top layers of the epitaxial stack 212 are SiGe layers (not shown). In other embodiments, the bottom layer of the epitaxial stack 212 is a Si layer, and the top layer of the epitaxial stack 212 is a SiGe layer (not shown).

[0153] like Figures 3 to 4 As shown, in operation S1030, method 1000 ( Figure 2The epitaxial stack 212 is patterned to form semiconductor fins 220. In some embodiments, operation S1030 includes forming a masking layer 217 on the epitaxial stack 212, such as... Figure 3 As shown. Masking layer 217 includes a first masking layer 218 and a second masking layer 219. The exemplary first masking layer 218 is a pad oxide layer made of silicon oxide, which can be formed by thermal oxidation. The exemplary second masking layer 219 is made of silicon nitride (SiN), which can be formed by chemical vapor deposition (CVD) (including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD)), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. Masking layer 217 is patterned into a photomask pattern using patterning operations including lithography and etching. Operation S1030 then patterns the epitaxial stack 212 through openings defined in the patterned masking layer 217 using etching processes such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. The stacked epitaxial layers 214 and 216 are therefore patterned into fins 220. Although Figure 4 This illustrates the formation of one fin 220, but any appropriate number of fins can also be formed. Grooves are etched between adjacent fins 220.

[0154] In various embodiments, each fin 220 includes an upper portion of staggered epitaxial layers 214 and 216, and a lower portion formed by etching the substrate 202. Each fin 220 projects upward from the substrate 202 along the Z direction and extends longitudinally along the Y direction. The sidewalls of each fin 220 may be straight or inclined (not shown). Figure 4 In the middle, the additional fins are spaced apart along the Y direction. The width of the fins 220 can be the same or different.

[0155] like Figure 5 As shown, in operation S1040, method 1000 ( Figure 2Shallow trench isolation (STI) features (also referred to as STI features) 221 are formed in the trenches adjacent to the dielectric layer in each fin 220. The method for forming the STI features 221 is to first fill the trenches around each fin 220 with a dielectric material layer to cover the top surface and sidewalls (not shown) of the fin 220. The dielectric material layer may include one or more dielectric materials. Suitable dielectric materials for the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited using any suitable technique, including thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD, and / or spin coating techniques. Then, as... Figure 5 As shown, the dielectric material layer is planarized using methods such as chemical mechanical planarization (CMP) until the top surface of the masking layer 217 is exposed, and the dielectric material layer is recessed to form a shallow trench isolation (STI) feature (also referred to as STI feature) 221. In the illustrated embodiment, the STI feature 221 is formed on the substrate 202. Any suitable etching technique can be used to recess the isolation feature 221, including dry etching, wet etching, RIE, and / or other etching methods, and in an exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation feature 221 without etching the fins 220. Masking layer 217 (e.g. Figure 4 (As shown) It can also be removed before, during, and / or after the recess of isolation feature 221. In some embodiments, mask layer 217 can be removed by a CMP process performed before the recess of isolation feature 221. In some embodiments, mask layer 217 is removed by an etchant used for recessing isolation feature 221.

[0156] like Figure 6 As shown, in operation S1050, method 1000 ( Figure 2 A sacrificial (virtual) gate structure 222 is formed. The sacrificial gate structure 222 is formed on the fin 220 as a portion of the channel region. The sacrificial gate structure 222 may extend onto multiple adjacent fins (not shown). The sacrificial gate structure 222 is located directly above and defines the channel region of the GAA device to be formed. Each sacrificial gate structure 222 includes a sacrificial gate dielectric 223 and a sacrificial gate electrode 224 on the sacrificial gate dielectric 223. As shown, the sacrificial gate structures 222 extend longitudinally in the Y direction and are spaced apart in the X direction.

[0157] The sacrificial gate structure 222 is formed by first depositing a sacrificial gate dielectric layer on the fin 220. Then, a sacrificial gate electrode layer is deposited on both the sacrificial gate dielectric layer and the fin 220. The sacrificial gate dielectric layer includes silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nanometers to about 200 nanometers. The sacrificial gate electrode layer includes silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer ranges from about 1 nanometer to about 5 nanometers. In some embodiments, the sacrificial gate electrode layer is planarized. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. A masking layer 225 is formed on the sacrificial gate electrode layer. The masking layer 225 may include a masking layer 226 such as silicon oxide and a masking layer 227 such as silicon nitride. Subsequently, a patterning operation is performed on the mask layer 225 to pattern the sacrificial gate electrode layer and the sacrificial gate dielectric layer into a sacrificial gate structure 222, including a sacrificial gate dielectric 223 and a sacrificial gate electrode 224.

[0158] As shown in the figure, the fins 220 are exposed between and on opposite sides of the sacrificial gate structures 222, thereby defining the source / drain (S / D) region. In this disclosure, the source and drain are interchangeable, and their structures are essentially the same.

[0159] Still referencing Figure 6 In operation S1060, method 1000 ( Figure 2 Spacers 230 are formed on the sidewalls of the sacrificial gate structure 222 and the fin 220 by depositing spacer material, followed by etching. Spacers 230 may include spacer materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN thin film, silicon oxycarbide, SiOCN thin film, and / or combinations thereof. In some embodiments, each spacer includes multiple layers, such as a pad layer 231 and a main spacer layer 232 on the sidewall of the pad layer 231.

[0160] For example, spacers 230 can be formed by depositing spacer materials, including pad material layers and dielectric material layers, on the sacrificial gate structure 222 using processes such as subatmospheric CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes.

[0161] like Figure 7As shown, after the deposition of the pad material layer and the dielectric material layer, in operation S1070, an etch-back process (e.g., anisotropic etching) is performed to expose and remove portions 220a (e.g., S / D regions) of the fin 220 that are adjacent to and not covered by the sacrificial gate structure 222. The pad material layer and the dielectric material layer may remain on the sidewalls of the sacrificial gate structure 222 as gate sidewall spacers 230, and on the fin sidewalls as fin sidewall spacers 230. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The thickness of the spacer 230 may range from about 5 nanometers to about 20 nanometers.

[0162] Cross-reference Figure 7 and Figure 8 , Figure 8 For along Figure 7 The cross-sectional view taken from line 8-8, i.e., the X-section view, is obtained in operation S1070, method 1000. Figure 2 The portion of the fin 220 not covered by the sacrificial gate structure 222 is recessed, forming a gap or groove 234 in the S / D region. It should be noted that... Figure 7 Only an adjacent portion of the sacrificial gate structure 222 and fin 220 is shown for a clearer view. Figure 6 Etching of the S / D region between the sacrificial gate structure 222. Figure 8 For along Figure 7 The cross-sectional view of line 8-8 is shown, but it illustrates three sacrificial gate structures 222 and fins 220 located below the sacrificial gate structures 222.

[0163] like Figure 8 Most clearly, the stacked epitaxial layers 214 and 216 are etched onto the bottom gap surface 233 formed by the fins 220. In many embodiments, operation S1070 forms the gaps 234 by a suitable etching process, such as a dry etching process, a wet etching process, or a combination thereof. The result of the etching process is that the fin segments 235 on the upper part of the fins 220 are defined by the gaps 234 and separated from each other.

[0164] like Figure 8 As further shown, method 1000 ( Figure 2 This includes lateral etching of the epitaxial layer 216 of the second composition in operation S1080. In an exemplary embodiment, a SiGe etching process is performed to laterally recess the epitaxial layer 216. Thus, a pocket 2161 is formed at a position adjacent to the epitaxial layer 216 laterally and to the epitaxial layer 214 longitudinally.

[0165] like Figure 9 As shown, method 1000 ( Figure 2This includes forming an internal spacer 2162 in a groove 2161 laterally adjacent to the epitaxial layer 216 during operation S1090. Figure 9 This is an X-section cross-sectional view. In an exemplary embodiment, the internal spacer 2162 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, silicon carbide carbide, silicon carbide oxynitride, and / or other suitable dielectric materials. The internal spacer 2162 may be formed by ALD or any other suitable method. As shown, after the material forming the internal spacer 2162 has been deposited, the material may be trimmed from the sidewalls of the epitaxial layer 214.

[0166] like Figure 10 As shown, the method can continue to form source / drain characteristics 400 in operation S1110. Figure 10 This is an X-section cross-sectional view. In an exemplary embodiment, the source / drain feature 400 is formed by epitaxial growth. For example, operation S1110 may include selectively growing epitaxial material on substrate 202 to form the source / drain feature 400. In an exemplary embodiment, the source / drain feature 400 is a strained source / drain feature 400.

[0167] In an exemplary embodiment, the source / drain feature 400 may include n-type epitaxial material source / drain features and p-type epitaxial material source / drain features. The epitaxial material may include one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET, or one or more layers of Si, SiGe, and Ge for a p-channel FET. For a p-channel FET, the source / drain may also contain boron (B). The source / drain epitaxial layer can be formed using epitaxial growth methods such as CVD, ALD, or molecular beam epitaxy (MBE).

[0168] exist Figure 11 In method 1000, operation S1120 includes covering the source / drain feature 400 with a dielectric material. Specifically, a dielectric pad 440 may be formed on the source / drain feature 400 and along the sidewall of the spacer 230. Furthermore, a dielectric material 450 may also be formed on the dielectric pad 440 on the source / drain feature 400. Specifically, the gap 234 is filled with the dielectric material 450. In an exemplary embodiment, the dielectric material 450 is a first interlayer dielectric layer (ILD). The dielectric material 450 may be silicon oxide or other suitable dielectric material. In some embodiments, the dielectric pad 440 is a dielectric material, such as silicon nitride or other suitable material.

[0169] like Figure 12As further shown, method 1000 includes opening and removing the sacrificial gate structure 222 in operation S1130. Specifically, a chemical mechanical planarization (CMP) process can be performed to remove the mask layer 225 and expose the sacrificial gate electrode 224. Furthermore, the sacrificial gate electrode 224 is removed to form a gate cavity 499. As shown, the gate cavity 499 is defined by the spacer 230 and the uppermost epitaxial layer 214. Figure 12 This is a cross-sectional view of the X-section.

[0170] exist Figure 13 In method 1000, the epitaxial layer 216 of the second component is removed in operation S1140. As a result, gaps 2169 are formed between the epitaxial layers 214 of the first component. Thus, the epitaxial layers 214 of the first component form vertically spaced nanosheets 560 of semiconductor material. The nanosheets 560 include a lowest nanosheet 561, a highest or uppermost nanosheet 563, and an intermediate nanosheet 562. Figure 13 This is a cross-sectional view of the X-section.

[0171] exist Figure 14 In the process, method 1000 includes performing a metal gate replacement process in operation S1150 to form a gate structure 500, such as gate structure 501, gate structure 502 and gate structure 503. Figure 14 This is a cross-sectional view of the X-section.

[0172] In an exemplary embodiment, the metal gate replacement process includes forming a gate dielectric layer 540 in the gate cavity 499 and the gap 2169, and forming a gate electrode material 550 on the gate dielectric layer 540 to fill the gate cavity 499 and the gap 2169.

[0173] An exemplary gate dielectric layer 540 is conformally deposited in the gate cavity 499 and the gap 2169. The gate dielectric layer 540 may be formed on the semiconductor nanosheet 560, and the gate electrode material 550 may be formed on the gate dielectric layer 540. Thus, each semiconductor nanosheet 560 is encapsulated in the gate dielectric layer 540 and surrounded by the gate electrode material 550.

[0174] According to some embodiments, the gate dielectric layer 540 comprises silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 540 is a high-k dielectric material, wherein the k value of the gate dielectric layer 540 may be greater than about 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming the gate dielectric layer 540 may include molecular-beam deposition (MBD), ALD, PECVD, etc.

[0175] Gate electrode material 550 is deposited on gate dielectric layer 540 and fills the remainder of the gate cavity. Gate electrode material 550 can be a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiples thereof. For example, although a single-layer gate material is shown in the figure, any number of work function tuning layers can be deposited.

[0176] like Figure 14 As shown, the replacement metal gate process further includes removing excess portions of the gate dielectric layer 540 and gate electrode material 550 located on the upper surface of the first ILD layer 450. For example, a planarization process, such as a CMP process, can be performed to remove the excess portions of the gate dielectric layer 540 and gate electrode material 550. Therefore, the device 200 has an upper surface 599. Thus, the remaining material portions of the gate dielectric layer 540 and gate electrode material 550 form a replacement gate structure 500 of the device 200. The gate dielectric layer 540 and gate electrode material 550 may be collectively referred to as a "gate," a "gate stack," or a "gate structure." Each gate structure 500 may extend along the sidewall of the channel region of the fin structure.

[0177] like Figure 14 As shown, each gate structure 500 includes an upper gate or outer gate portion 510 located on the uppermost nanosheet 563. Furthermore, each gate structure 500 also includes an inner gate portion 520 located below the uppermost nanosheet 563. Specifically, each gate structure 500 includes an uppermost inner gate portion 523 located directly below the uppermost nanosheet 563, a lowest inner gate portion 521 located directly below the lowest nanosheet 561, and a middle inner gate portion 522 located directly above the lowest nanosheet 561. Each gate structure 500 is directly located on the central portion 205 of the substrate 202.

[0178] exist Figure 15 The method may include forming a dielectric material on device 200 in operation S1160. For example, a layer 600, such as a contact etch stop layer (CESL) or a capping layer, may be formed on the upper surface 599. In an exemplary embodiment, the vertical thickness of layer 600 in the Z direction is 1 to 5 nanometers. Figure 16 This is a cross-sectional view of the X-section.

[0179] Operation S1160 further includes forming a second interlayer dielectric (ILD) layer 700 on layer 600. In some embodiments, the second ILD layer 700 is silicon oxide or another suitable material. In some embodiments, the second ILD layer 700 and the first ILD layer 450 are the same material, such as silicon oxide.

[0180] exist Figure 16 In operation S1171, method 1000 includes performing a first etching process to form an upper opening 720 on a selected source / drain feature 400. Figure 16 This is a cross-sectional view of the X-section. As shown, the upper opening 720 is defined by the sidewall 730 formed by the second ILD layer 700 and layer 600.

[0181] In one exemplary embodiment, the first etching process may have etch selectivity, thereby removing layer 600 at a faster or higher etch rate than the first ILD layer 450. In one exemplary embodiment, the first etching process has etch selectivity, thereby removing layer 600 at a faster or higher etch rate than the second ILD layer 700. As shown, under the selected etch selectivity, the first etching process may be performed on the upper surface 599 of the first ILD layer 450.

[0182] exist Figure 17 In operation S1172, method 1000 includes performing a second etching process to remove the exposed portions of dielectric pad 440 and first ILD layer 450, thereby extending the upper opening 720 to the selected source / drain feature 400. Figure 17 This is a cross-sectional view of the X-section. As shown, the upper opening 720 is defined by the sidewall 730 formed by the second ILD layer 700 and layer 600, and the spacer 230.

[0183] exist Figure 18 In operation S1173, method 1000 includes performing a third etching process to form a trench 780 on and / or within a selected source / drain feature 400. Figure 18 This is a cross-sectional view of the X-section. Figure 18 In one embodiment, the trench 780 has a bottom surface 781 with a U-shaped cross-section. The bottom surface 781 extends to its deepest point located in the horizontal plane 782, i.e., a plane extending in the X and Y directions at a constant Z value. No part of the trench 780 is lower than the horizontal plane 782. Figure 18As shown, the horizontal plane 782 is located below the lowest surface 5211 of the lowest inner gate portion 521, that is, at a depth deeper than in the Z direction, below the lowest surface 5211 of each metal gate 501-503. Correspondingly, the horizontal plane 782 is located below the lowest surface 5611 of the lowest nanosheet 561 in each metal gate 501-503, that is, at a depth deeper than in the Z direction.

[0184] It should be noted that, although Figures 16 to 18 An opening and etching of a source / drain feature 400 is illustrated, but this is for illustrative purposes only. Adjacent source / drain features 400 can be opened and etched, and contacts can be formed therein according to the following process, such that the central portion 205 of the gate 500 and nanosheet 560 and the underlying substrate 202 can be surrounded by two adjacent source / drain contacts 800, as described in the process below.

[0185] See Figure 19 , Figure 18 The embodiments are further processed. Specifically, in operation S1180, method 1000 forms silicide 810 in trench 780. Specifically, a silicide process can be performed to convert the upper portion 801 of the source / drain feature 400 into silicide 810. For example, metal can be deposited in the trench, and a heat treatment can be performed to form silicide 810.

[0186] In operation S1190, method 1000 can continue to fill trench 780 with metal filler 820, such as Figure 19 As shown. In some embodiments, the conductive material includes a metal, such as tungsten (W) or other suitable material. A planarization process can be performed to remove the covering portion of the metal filler 820 onto the self-dielectric 450. Operations S1180 and S1190 can form a conductive contact 800, i.e., a source / drain contact 800, connected to a selected source / drain feature 400.

[0187] Method 1000 can continue with further processing in operation S1200. For example, dielectric layer 910 and metallization layer 920 can be deposited and etched to form interconnect structure 900, such as... Figure 19 As shown. Further processing may include passivation and other back-end of line (BEOL) processes such as packaging.

[0188] Figure 20 Highlighting the connection with Figure 19 In this embodiment, the gate 500 is adjacent to the source / drain feature 400. For example... Figure 20As shown, the source / drain feature 400 has a U-shaped cross-section with a lowest point of 421. An inner corner 411 extends from the lowest point 421 to the upper end 422. Similarly, an outer corner 412 extends from the lowest point 421 to the upper end 422. The source / drain feature 400 has an outer surface 431 that contacts the substrate 202, gate portions (including spacers) 521, 522, 523, and 510, and nanosheets 561, 562, and 563. Furthermore, the source / drain feature 400 also has an inner surface 432 that contacts the silicide or filler metal of the contact 800.

[0189] like Figure 20 As shown, the source / drain feature 400 has a lateral width W0 that extends along the X direction from the outer surface 431 to the inner surface 432 at the lowest surface of the lowest inner gate portion 521. In some embodiments, the lateral width W0 is 10 to 20 nanometers. The source / drain feature 400 has a lateral width W1 that extends along the X direction from the outer surface 431 at the interface between the lowest inner gate portion 521 and the lowest nanosheet 561 to the inner surface 432. In some embodiments, the lateral width W1 is 0 to 20 nanometers, for example, 0 to 15 nanometers, 0 to 5 nanometers, or 0 to 2 nanometers. At the interface between the intermediate inner gate portion 522 and the nanosheet 562, the source / drain feature 400 has a lateral width W2 that extends along the X direction from the outer surface 431 to the inner surface 432. In some embodiments, the lateral width W2 is 0 to 5 nanometers, for example, 0 to 2 nanometers. The source / drain feature 400 has a lateral width W3 that extends along the X direction from the outer surface 431 of the interface between the uppermost inner gate portion 523 and the uppermost nanosheet 563 to the inner surface 432. In some embodiments, the lateral width W3 is 0 to 2 nanometers. In some embodiments, W0 > W1 > W2 > W3.

[0190] like Figure 20As shown, the inner corner 411 and outer corner 412 may not extend to the height of the outer gate portion 510. In other words, each upper end 422 may be located on a plane below the interface of the outer gate portion 510 and the uppermost nanosheet 563. In some embodiments, each upper end 422 may be located in a plane below the interface of the uppermost nanosheet 563 and the uppermost inner gate portion 523. In some embodiments, each upper end 422 may be located in a plane below the interface of the uppermost inner gate portion 523 and the nanosheet 562. In some embodiments, each upper end 422 may be located in a plane below the interface of the nanosheet 562 and the inner gate portion 522. In some embodiments, each upper end 422 may be located in a plane below the interface of the inner gate portion 522 and the nanosheet 561. In some embodiments, each upper end 422 may be located in a plane below the interface of the nanosheet 561 and the inner gate portion 521. In some embodiments, each upper end 422 may be located in a plane below the internal gate portion 521 and the interface of the substrate 202.

[0191] See now Figure 21 The structure of the source / drain feature 400 is further described. Figure 21 In the middle, metal filler 820 and silicide 810 (see Figure 19 These are collectively referred to as contact 800. Figure 21 In the middle, the lowest point of the inner surface 432 of the source / drain feature 400 is located on a horizontal plane 433 defined by a constant height in the Z direction of the Y-axis and X-axis. The horizontal plane 433 also defines the lowest point of the contact 800, which is defined by the lowest point of the silicide 810.

[0192] As shown in the figure, the horizontal plane 433 is located at a vertical distance B1 in the Z direction from the interface between the substrate 202 and the internal gate portion 521. In some embodiments, the vertical distance B1 is 5 to 30 nanometers.

[0193] The horizontal plane 433 is located at a vertical distance T1 in the Z direction between the interface of the internal gate portion 521 and the nanosheet 561. In some embodiments, the vertical distance T1 is 15 to 35 nanometers.

[0194] The horizontal plane 433 is located at a vertical distance B2 in the Z direction from the interface between the nanosheet 561 and the internal gate portion 522. In some embodiments, the vertical distance B2 is 20 to 40 nanometers.

[0195] The horizontal plane 433 is located at a vertical distance T2 in the Z direction between the interface of the internal gate portion 522 and the nanosheet 562. In some embodiments, the vertical distance T2 is 30 to 50 nanometers.

[0196] The horizontal plane 433 is located at a vertical distance B3 in the Z direction from the interface between the nanosheet 562 and the internal gate portion 523. In some embodiments, the vertical distance B3 is 40 to 60 nanometers.

[0197] The horizontal plane 433 is located at a vertical distance T3 in the Z direction from the interface between the internal gate portion 523 and the nanosheet 563. In some embodiments, the vertical distance T3 is 50 to 70 nanometers.

[0198] like Figure 21 As further shown, the source / drain feature 400 forms an angle A1 between the vertical central line 898 passing through the lowest point of the inner surface 432 and the line 899 from the lowest point of the inner surface 432 to the upper end 422. In some embodiments, the angle A1 is 20 to 85 degrees.

[0199] See now Figure 22 The structure of the metal packing 820 at contact 800 is further described. Figure 22 In the figure, silicide 810 is not shown. Metal filler 820 has an outer surface 832. As shown, the lowest point of the outer surface 832 of the metal 820 of the contact 800 is located on a horizontal plane 833 defined by a constant height in the Z direction by the Y-axis and X-axis.

[0200] As shown in the figure, the horizontal plane 833 is located at a vertical distance L1 in the Z direction from the interface between the substrate 202 and the internal gate portion 521. In some embodiments, the vertical distance L1 is 0 to 20 nanometers.

[0201] The horizontal plane 833 is located at a vertical distance U1 in the Z direction between the interface of the internal gate portion 521 and the nanosheet 561. In some embodiments, the vertical distance U1 is 10 to 30 nanometers.

[0202] The horizontal plane 833 is located at a vertical distance L2 in the Z direction from the interface between the nanosheet 561 and the internal gate portion 522. In some embodiments, the vertical distance L2 is 15 to 35 nanometers.

[0203] The horizontal plane 833 is located at a vertical distance U2 in the Z direction between the interface of the internal gate portion 522 and the nanosheet 562. In some embodiments, the vertical distance U2 is 25 to 45 nanometers.

[0204] The horizontal plane 833 is located at a vertical distance L3 in the Z direction from the interface between the nanosheet 562 and the internal gate portion 523. In some embodiments, the vertical distance L3 is 35 to 55 nanometers.

[0205] The horizontal plane 433 is located at a vertical distance U3 in the Z direction from the interface between the internal gate portion 523 and the nanosheet 563. In some embodiments, the vertical distance U3 is 45 to 65 nanometers.

[0206] Figure 23 Another embodiment is described, wherein the third etching process of operation S1173 forms a trench 780 above and / or inside the selected source / drain feature 400. Figure 23 This is a cross-sectional view of the X-section. Figure 23 In one embodiment, the trench 780 has a bottom surface 781, which may have a generally linear cross-section. For example... Figure 23 As shown, the horizontal plane 783 is defined by the highest point of the bottom surface 781, meaning that no part of the source / drain feature 400 is located above the horizontal plane 783.

[0207] As shown in the figure, the bottom surface 781 terminates at a first end 784 and a second end 785. The height difference between the bottom surface 781 from the first end 784 to the second end 785 can be 0 to 15 nanometers.

[0208] like Figure 23 As shown, the horizontal plane 783 can be formed at a distance D1 below the lowest surface 5211 of the gate 500 (i.e., the lowest surface 5211 of the inner gate portion 521). In some embodiments, the distance D1 is 0 to 15 nanometers, for example, 0 to 10 nanometers.

[0209] The third etch in operation S1173 can be performed in a single process or multiple processes. In some embodiments, the third etch includes dry etching, such as capacitively coupled plasma (CCP) or inductively coupled plasma (ICP) etching. In some embodiments, the dry etching uses a gas selected from C4F6 or C4F8. In some embodiments, the dry etching is high-voltage plasma dry etching. For example, the dry etching can be performed at pressures from 10 to 500 millitors (mTorr). In some embodiments, the dry etching is performed at temperatures from -30 (-30) to 140 degrees Celsius.

[0210] In some embodiments, the third etching additionally or alternatively includes wet etching. For example, wet etching may use an etchant such as dilute NH4OH. In some embodiments, wet etching is performed at a temperature of 20 to 100 degrees Celsius.

[0211] In summary, the first etching process of operation S1171, the second etching process of operation S1172, and the third etching process of operation S1173 represent operation S1170 for opening and forming trench 780 on the selected source / drain feature 400. In some embodiments, operations S1171, S1172, and / or S1173 may be combined into one or two processes. For example, the etching for forming trench 780 may also remove the dielectric pad 440 and the first ILD layer 450 of the dielectric material on the source / drain feature 400.

[0212] As shown in the figure, the horizontal plane 783 is located at a vertical distance S1 in the Z direction from the interface between the substrate 202 and the internal gate portion 521. In some embodiments, the vertical distance S1 is 0 to 20 nanometers.

[0213] The horizontal plane 783 is located at a vertical distance F1 in the Z direction from the interface between the internal gate portion 521 and the nanosheet 561. In some embodiments, the vertical distance F1 is 10 to 30 nanometers.

[0214] The horizontal plane 783 is located at a vertical distance S2 in the Z direction from the interface between the nanosheet 561 and the internal gate portion 522. In some embodiments, the vertical distance S2 is 15 to 35 nanometers.

[0215] The horizontal plane 783 is located at a vertical distance F2 in the Z direction from the interface between the internal gate portion 522 and the nanosheet 562. In some embodiments, the vertical distance F2 is 25 to 45 nanometers.

[0216] The horizontal plane 783 is located at a vertical distance S3 in the Z direction from the interface between the nanosheet 562 and the internal gate portion 523. In some embodiments, the vertical distance S3 is 35 to 55 nanometers.

[0217] The horizontal plane 783 is located at a vertical distance F3 in the Z direction from the interface between the internal gate portion 523 and the nanosheet 563. In some embodiments, the vertical distance F3 is 45 to 65 nanometers.

[0218] See Figure 24 , Figure 23 The embodiments are further processed. Specifically, in operation S1180, method 1000 forms silicide 810 in trench 780. Specifically, a silicide process can be performed to convert the upper part of the source / drain feature 400 into silicide 810. For example, metal can be deposited in the trench, and a heat treatment can be performed to form silicide 810.

[0219] In operation S1190, method 1000 can continue to fill trench 780 with metal filler 820, such as Figure 24As shown. In some embodiments, the conductive material includes a metal, such as tungsten (W) or other suitable material. A planarization process can be performed to remove the covering portion of the metal filler 820 onto the self-dielectric 450. Operations S1180 and S1190 can form a conductive contact 800, i.e., a source / drain contact 800, connected to a selected source / drain feature 400.

[0220] Method 1000 can continue with further processing in operation S1200. For example, dielectric layer 910 and metallization layer 920 can be deposited, planarized, and etched to form interconnect structure 900, such as... Figure 24 As shown. Further processing may include passivation and other back-end of line (BEOL) processes such as packaging.

[0221] As shown in the figure, Figures 23 to 24 In this embodiment, during the silicide process, the sidewalls 569 of the nanosheet 560 are not covered by the source / drain features 400. Therefore, as Figure 24 As shown, the sidewalls 569 of the nanosheet 560 can be recessed and transformed into silicide. Then, during the formation of the metal filler 820, protrusions 825 of the metal filler 820 fill the recessed sidewalls 569. The protrusions 825 extend outward from the wall portion 826 where the metal filler 820 connects to the internal spacer 2162.

[0222] Each laterally extending protrusion 825 can form an angle A2 from a horizontal central line 896 passing through the outermost point of the protrusion 825 and a line 897 from the outermost point of the protrusion 825 to the junction with the vertical wall portion 826. In some embodiments, the angle A1 is 20 to 85 degrees.

[0223] Each embodiment provides a channel region 560 formed directly between the source / drain contacts 800, such that the current path can be completely horizontal from the source / drain contacts 800 through their respective channel regions 560 to the other source / drain contact 800. Furthermore, this embodiment can reduce or eliminate source / drain feature material between the source / drain contacts 800 and the channel regions 560.

[0224] In one embodiment, a method of manufacturing a semiconductor structure includes: forming a stack of semiconductor nanosheets on a substrate; forming source / drain features adjacent to the semiconductor nanosheet stack; etching a portion of the source / drain features to form a trench, wherein the trench extends to or below the lowest surface of the lowest semiconductor nanosheet in the semiconductor nanosheet stack; and forming conductive contacts of the source / drain features in the trench.

[0225] In some embodiments of the method, the lowest semiconductor nanosheet in the semiconductor nanosheet stack is located above the lowest inner gate portion; and the conductive contact is laterally adjacent to the lowest inner gate portion.

[0226] In some embodiments of the method, the lowest semiconductor nanosheet in the semiconductor nanosheet stack is located above the lowest internal gate portion; and the horizontal plane is located below the lowest surface of the lowest internal gate portion.

[0227] In some embodiments of the method, the horizontal plane is located 0 to 30 nanometers below the lowest surface of the lowest semiconductor nanosheet in the stack.

[0228] In some embodiments of the method, the horizontal plane is located 5 to 30 nanometers below the lowest surface of the lowest semiconductor nanosheet in the stack.

[0229] In some embodiments of the method, after the conductive contacts of the source / drain features are formed in the trench, any portion of the source / drain features is not located between the conductive contacts and the semiconductor nanosheet stack.

[0230] In some embodiments of the method, after forming a conductive contact of the source / drain feature in the trench, the remaining portion of the source / drain feature is located between the conductive contact and at least one of the semiconductor nanosheets in the semiconductor nanosheet stack, and the lateral width of the remaining portion does not exceed 15 nanometers.

[0231] In some embodiments of the method, the step of etching portions of the source / drain features to form a trench includes: performing dry plasma etching at a pressure of at least 10 millitor; and / or performing wet etching.

[0232] In another embodiment, a semiconductor structure is provided, comprising: a substrate; a gate structure, the lowest surface of which covers a central portion of the substrate; a first source / drain feature and a second source / drain feature surrounding the central portion of the substrate; a first source / drain contact located above the first source / drain feature; and a second source / drain contact located above the second source / drain feature; wherein the lowest surface of the gate structure is directly located between the first source / drain contact and the second source / drain contact.

[0233] In some embodiments of the semiconductor structure, the first source / drain feature and the second source / drain feature each have a U-shaped cross-section, including an outer corner and an inner corner, with the inner corner adjacent to the gate structure and located between the gate structure and the outer corner.

[0234] In some embodiments of the semiconductor structure, the gate structure includes an outer gate portion covered by a stack of vertically spaced inner gate portions separated by semiconductor nanosheets; the lateral thickness of the inner and outer corners adjacent to the lowest surface is 10 to 20 nanometers; and the lateral thickness of the inner and outer corners adjacent to the uppermost inner gate portion is 0 to 2 nanometers.

[0235] In some embodiments of the semiconductor structure, the first source / drain feature and the second source / drain feature each have an uppermost surface, which extends from the inner surface closest to the gate structure to the outer surface farthest from the gate structure, and the uppermost surface is located at or below the lowest surface of the gate structure.

[0236] In some embodiments of the semiconductor structure, the vertical distance between the uppermost surface and the lowest surface of the gate structure is 0 to 10 nanometers.

[0237] In some embodiments of the semiconductor structure, the gate structure includes an outer gate portion, on which stacked vertically spaced inner gate portions separated by semiconductor nanosheets are formed; a first source / drain contact and a second source / drain contact each include a sidewall closest to the gate structure; and the first source / drain contact and the second source / drain contact each include a protrusion extending laterally from the sidewall toward the semiconductor nanosheet.

[0238] In some embodiments of the semiconductor structure, each protrusion has a circular outer surface with an angle of 20 to 85 degrees.

[0239] In another embodiment, a semiconductor structure is provided, comprising: a gate-all-around (GAA) structure including an outer gate portion, the outer gate portion being covered by a stack of vertically spaced inner gate portions separated by semiconductor nanosheets; and vertically extending metal contacts laterally adjacent to the outer gate portion and the stack of vertically spaced inner gate portions; wherein the stack of vertically spaced inner gate portions includes an uppermost inner gate portion; and wherein 0 to 2 nanometer epitaxial material is directly located between the uppermost inner gate portion and the vertically extending metal contacts.

[0240] In some embodiments of the semiconductor structure, the vertically spaced internal gate portions stack includes a lowest internal gate portion; and epitaxial material of 0 to 20 nanometers is located directly between the lowest internal gate portion and the vertically extending metal junction.

[0241] In some embodiments of the semiconductor structure, the vertically spaced internal gate portion stack includes a lowest internal gate portion; no epitaxial material is directly located between the uppermost internal gate portion and the vertically extending metal contact; and no epitaxial material is directly located between the lowest internal gate portion and the vertically extending metal contact.

[0242] In some embodiments of the semiconductor structure, the bottom surface of the vertically extending metal contact has a U-shaped cross-section with an angle of 20 to 85 degrees.

[0243] In some embodiments of the semiconductor structure, the vertically extending metal contacts include the sidewall closest to the GAA structure; and the vertically extending metal contacts include protrusions extending laterally from the sidewall toward the semiconductor nanosheet.

[0244] In another embodiment, a semiconductor structure is provided, comprising: a substrate; a gate structure, the lowest surface of which covers a central portion of the substrate; a first source / drain feature and a second source / drain feature surrounding the central portion of the substrate; a first source / drain contact located above the first source / drain feature; and a second source / drain contact located above the second source / drain feature. The first and second source / drain features each have a U-shaped cross-section, including an outer corner and an inner corner, wherein the inner corner is adjacent to the gate structure and located between the gate structure and the outer corner, and the lowest surface of the gate structure is directly located between the first and second source / drain contacts.

[0245] In some embodiments of the semiconductor structure, the gate structure includes an outer gate portion covered by a stack of vertically spaced inner gate portions separated by a plurality of semiconductor nanosheets; the lateral thickness of the inner and outer corners adjacent to the lowest surface is 10 to 20 nanometers; and the lateral thickness of the inner and outer corners adjacent to the uppermost inner gate portion is 0 to 2 nanometers.

[0246] The foregoing summary outlines the features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can easily serve as the basis for designing or modifying other processes and structures to achieve the same objectives and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, Include: One substrate; A gate structure, wherein a lowest surface of the gate structure covers a central portion of the substrate; A first source / drain feature and a second source / drain feature surround the central portion of the substrate; A first source / drain contact is located above the first source / drain feature; and A second source / drain contact is located above the second source / drain feature; The lowest surface of the gate structure is located directly between the first source / drain contact and the second source / drain contact.

2. The semiconductor structure as described in claim 1, characterized in that, The first source / drain feature and the second source / drain feature each have an uppermost surface. The uppermost surface extends from an inner surface closest to the gate structure to an outer surface farthest from the gate structure, and the uppermost surface is located at or below the lowest surface of the gate structure.

3. The semiconductor structure as described in claim 2, characterized in that, The vertical distance between the uppermost surface and the lowest surface of the gate structure is 0 to 10 nanometers.

4. The semiconductor structure as described in claim 2, characterized in that, in: The gate structure includes an outer gate portion covered by a stack of vertically spaced inner gate portions separated by multiple semiconductor nanosheets; The first source / drain contact and the second source / drain contact each include a sidewall closest to the gate structure; and The first source / drain contact and the second source / drain contact each include a protrusion extending laterally from the sidewall toward the plurality of semiconductor nanosheets.

5. The semiconductor structure as described in claim 4, characterized in that, Each of the protrusions has a circular outer surface with an angle of 20 to 85 degrees.

6. A semiconductor structure, characterized in that, Include: A gate-surround structure includes an outer gate portion covered by a stack of vertically spaced inner gate portions separated by a plurality of semiconductor nanosheets; and A vertically extending metal contact is stacked laterally adjacent to the outer gate portion and the vertically spaced inner gate portions; The vertically spaced internal gate portion stack includes an uppermost internal gate portion; and The 0 to 2 nanometer epitaxial material is located directly between the uppermost internal gate portion and the vertically extending metal junction.

7. The semiconductor structure as described in claim 6, characterized in that, in: The vertically spaced internal gate portion stack includes a lowest internal gate portion; and Epitaxial material of 0 to 20 nanometers is located directly between the lowest internal gate portion and the vertically extending metal junction.

8. The semiconductor structure as described in claim 6, characterized in that, in: The vertically extending metal contact includes the sidewall closest to the gate surround structure; and The vertically extending metal contact includes a protrusion extending laterally from the sidewall toward the plurality of semiconductor nanosheets.

9. A semiconductor structure, characterized in that, Include: One substrate; A gate structure, wherein a lowest surface of the gate structure covers a central portion of the substrate; A first source / drain feature and a second source / drain feature surround the central portion of the substrate; A first source / drain contact is located above the first source / drain feature; and A second source / drain contact is located above the second source / drain feature; The first source / drain feature and the second source / drain feature each have a U-shaped cross-section, including an outer corner and an inner corner, wherein the inner corner is adjacent to the gate structure and located between the gate structure and the outer corner, and the lowest surface of the gate structure is directly located between the first source / drain contact and the second source / drain contact.

10. The semiconductor structure as described in claim 9, characterized in that, in: The gate structure includes an outer gate portion covered by a stack of vertically spaced inner gate portions separated by multiple semiconductor nanosheets; The inner and outer corners each have a side thickness of 10 to 20 nanometers adjacent to the lowest surface; and The inner and outer corners are respectively adjacent to a side thickness of 0 to 2 nanometers of the uppermost internal gate portion.

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