semiconductor devices
By incorporating a material reduction groove into the semiconductor device packaging structure, the problem of GaN devices being easily combustible at high temperatures is solved, achieving effective energy release and improved safety while maintaining the heat dissipation performance of the packaging material.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- INNOSCIENCE (SHENZHEN) SEMICON CO LTD
- Filing Date
- 2025-05-16
- Publication Date
- 2026-05-26
AI Technical Summary
Existing GaN semiconductor device packaging is prone to combustion at high temperatures and lacks an effective energy release mechanism, leading to thermal decomposition and combustion of the molding compound.
A material reduction groove is set in the packaging structure. The material reduction groove overlaps with the lead portion along the thickness direction of the semiconductor device, and the bottom wall maintains a minimum distance of more than 0.2 mm from the lead so that energy can be released from the weak point in the event of a short circuit, thus preventing the device from burning.
By setting up a material reduction groove, energy is effectively released during short circuits, preventing device combustion, improving safety, and maintaining the heat dissipation performance of the packaging material.
Smart Images
Figure CN224290614U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, specifically to a semiconductor device. Background Technology
[0002] The current packaging of GaN semiconductor devices is basically based on Si-Mos without optimization according to the characteristics of GaN. Due to the high temperature resistance of GaN devices, the surface temperature of the device will be much higher than the limit temperature that the molding compound can withstand before the device completely loses its function. The molding compound is prone to combustion due to thermal decomposition. Utility Model Content
[0003] The purpose of this invention is to provide a semiconductor device that, when a short circuit occurs, ensures that energy is released from the weak point to burn off the semiconductor bonding wire, thereby preventing the device from burning.
[0004] To achieve the above objectives, this utility model provides a semiconductor device, including a chip, a package structure, and electrode pins. The chip is packaged within the package structure, and the electrode pins are electrically connected to the electrode pads of the chip via leads. At least a portion of the electrode pins is exposed outside the package structure. The package structure has a stripping groove that is recessed inward from the outer surface of the package structure. At least a portion of the projection of the stripping groove along the thickness direction of the semiconductor device overlaps with the projection of the leads along the thickness direction. The electrode pins are source pins, drain pins, or gate pins.
[0005] As can be seen from the above scheme, when a short circuit occurs in the device, energy can be released from the weak point to burn off the semiconductor bonding wire, thus preventing the device from burning and improving safety. Furthermore, placing the wire bonding area at the drain pin is even more effective and less likely to expose the lead material.
[0006] A preferred embodiment is that the minimum distance between the bottom wall of the feed trough and the lead wire is greater than 0.2 mm.
[0007] Therefore, by limiting the minimum distance between the bottom wall of the material reduction tank and the lead wire, the impact on device function can be avoided.
[0008] A preferred embodiment is that, in the thickness direction, the material reduction groove is located on the side of the package structure away from the drain pin.
[0009] Therefore, it is evident that when ensuring the soldering of semiconductor devices to the PCB board, the material reduction groove should be located on the side away from the PCB board.
[0010] A preferred embodiment is that when the electrode pin is a gate pin, the semiconductor device is a normally off device.
[0011] A preferred embodiment is that the material reduction groove extends along a first direction, which is perpendicular to the thickness direction.
[0012] A further approach is to have the material reduction groove penetrate the packaging structure along the first direction.
[0013] A preferred embodiment is that the bottom wall of the material reducing trough is flat.
[0014] A preferred embodiment is that the bottom wall of the material reducing trough is an arc-shaped surface, with the bottom wall curving towards the direction of the lead wire.
[0015] In a preferred embodiment, at least a portion of the material reduction groove is located at a first position on the outer surface of the package structure, which is the position with the smallest distance from the lead wire.
[0016] Therefore, this method can achieve energy release during short circuits by removing only the smallest amount of packaging material, while ensuring that the heat dissipation performance of the packaging material is not affected. Attached Figure Description
[0017] Figure 1 This is a perspective view of the first embodiment of the semiconductor device of this utility model.
[0018] Figure 2 This is a cross-sectional view of the first embodiment of the semiconductor device of this utility model.
[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation
[0020] First embodiment of semiconductor device:
[0021] See Figure 1 and Figure 2 The semiconductor device includes a chip 1, a package structure 2, and an electrode pin group. The electrode pin group includes three electrode pins: a source pin 3, a gate pin 4, and a drain pin 5.
[0022] Chip 1 is encapsulated within package structure 2, with at least a portion of drain pin 5, at least a portion of gate pin 4, and at least a portion of source pin 3 exposed outside the package structure. Drain pin 5 is electrically connected to the drain pad of chip 1 via a first lead 6, source pin 3 is electrically connected to the source pad of chip 1 via a second lead 7, and gate pin 4 is electrically connected to the gate pad of chip 1 via a third lead (not shown).
[0023] The packaging structure 2 has a material reduction groove 21. In the thickness direction h of the semiconductor device, the material reduction groove 21 is located on the side of the packaging structure 2 away from the drain pin 5, that is, the material reduction groove 21 is located on the front side 22 of the semiconductor device, and the source pin 3, gate pin 4 and drain pin 5 are all located close to the back side 23 of the semiconductor device.
[0024] The material reduction groove 21 is recessed inward from the front side 22 of the self-encapsulation structure 2. In this embodiment, the bottom wall 211 of the material reduction groove 21 is flat. In other embodiments, the bottom wall 211 of the material reduction groove 21 can also be an arc-shaped surface, and the bottom wall 211 is bent toward the direction of the first lead wire 6.
[0025] The projection of the material stripping groove 21 along the thickness direction h of the semiconductor device overlaps with at least a portion of the projection of the first lead 6 along the thickness direction h of the semiconductor device, such that a portion of the material stripping groove 21 is opposite to the first lead in the thickness direction.
[0026] The minimum distance between the bottom wall 211 of the material reduction groove 21 and the first lead 6 is greater than 0.2 mm. By limiting the minimum distance between the bottom wall 211 of the material reduction groove 21 and the first lead 6, the influence on the function of the device can be avoided.
[0027] At least a portion of the material reduction groove 21 is located at a first position on the packaging structure. The first position is the position on the front side 22 of the packaging structure with the smallest distance from the first lead 6. In this way, it can be ensured that the energy release effect during short circuit can be achieved by removing the minimum amount of packaging material, while ensuring that the heat dissipation performance of the packaging material is not affected.
[0028] The material reduction groove 21 is along the first direction (i.e. Figure 2 The material reduction groove 21 extends through the encapsulation structure 2 in a direction perpendicular to the paper surface. In other embodiments, the material reduction groove 21 may not penetrate the encapsulation structure 2 in the first direction.
[0029] As can be seen above, when a device short-circuits, the material is prone to bursting at its weakest point. The original encapsulation material acts like a "heat sink," quickly dissipating the heat generated by the chip. If part of the encapsulation material is removed, heat will accumulate near the leads, potentially exceeding the leads' heat resistance limit and causing them to burn out. Furthermore, the absence of encapsulation material alters the heat flow path, creating "hot spots" near the leads and accelerating thermal fatigue of the metal wires. Additionally, different materials expand differently when heated; for example, metal wires expand more significantly than plastic casings. Removing part of the encapsulation material concentrates this expansion difference in the lead area, causing repeated stretching and breakage, much like repeatedly bending a wire will break. Moreover, placing the wire bonding area at the drain pin is more effective and less likely to expose the lead material.
[0030] Second embodiment of semiconductor device:
[0031] As a description of the second embodiment of the semiconductor device of this utility model, the following description only focuses on the differences from the first embodiment of the semiconductor device described above.
[0032] In this embodiment, the material reduction groove is disposed in the bonding area of the source pin, that is, the projection of the material reduction groove along the thickness direction overlaps with at least a portion of the projection of the second lead along the thickness direction, and the minimum distance between the bottom wall of the material reduction groove and the second lead is greater than 0.2 mm.
[0033] Furthermore, the stripping groove can also be located in the bonding area of the gate lead, meaning that at least a portion of the projection of the stripping groove along the thickness direction overlaps with at least a portion of the projection of the third lead along the thickness direction, and when the electrode lead is a gate lead, the semiconductor device is a normally off device. These modifications also achieve the objective of this invention.
[0034] Finally, it should be emphasized that the above are only preferred embodiments of the present utility model and are not intended to limit the present utility model. For those skilled in the art, the present utility model can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.
Claims
1. Semiconductor devices, including chips, packaging structures, and electrode leads; The chip is encapsulated within the package structure, and the electrode pins are electrically connected to the electrode pads of the chip via leads, with at least a portion of the electrode pins exposed outside the package structure. Its features are: The packaging structure has a material reduction groove, which is recessed inward from the outer surface of the packaging structure. The projection of the material reduction groove along the thickness direction of the semiconductor device overlaps with at least a portion of the projection of the lead along the thickness direction. The electrode pins are source pins, drain pins, or gate pins.
2. The semiconductor device according to claim 1, characterized in that: The minimum distance between the bottom wall of the material reduction groove and the lead wire is greater than 0.2 mm.
3. The semiconductor device according to claim 1, characterized in that: In the thickness direction, the material reduction groove is located on the side of the packaging structure away from the electrode pin.
4. The semiconductor device according to any one of claims 1 to 3, characterized in that: When the electrode pin is a gate pin, the semiconductor device is a normally off device.
5. The semiconductor device according to any one of claims 1 to 3, characterized in that: The material reduction groove extends along a first direction, which is perpendicular to the thickness direction.
6. The semiconductor device according to claim 5, characterized in that: The material reduction groove extends through the packaging structure along the first direction.
7. The semiconductor device according to any one of claims 1 to 3, characterized in that: The bottom wall of the material reduction trough is flat.
8. The semiconductor device according to any one of claims 1 to 3, characterized in that: The bottom wall of the material reduction groove is an arc-shaped surface, and the bottom wall is bent toward the direction of the lead wire.
9. The semiconductor device according to any one of claims 1 to 3, characterized in that: At least a portion of the material reduction groove is located at a first position on the packaging structure, which is the position on the outer surface of the packaging structure where the distance from the lead wire is the smallest.