Goa driving unit, goa driving circuit and display device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG LAIBAO DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-05-29
AI Technical Summary
In the GOA driver unit, some transistors cannot be fully discharged after the display device is turned off, resulting in a shortened transistor lifespan.
When the display device is powered off, a preset high-level signal and a high-level latch clock signal are individually connected to the pull-down control module, so that the pull-down control module first pulls the target node up to a high level and then pulls it down to a low level, thereby dissipating residual charge.
This extends the lifespan of transistors controlled by the target node and improves the stability of the GOA drive unit and the durability of the transistors.
Smart Images
Figure CN224304338U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, and in particular relates to a GOA driving unit, a GOA driving circuit and a display device. Background Technology
[0002] Integrating gate driver on array (GOA) circuitry onto a glass substrate creates a scanning drive for the display panel. Compared to traditional gate chip-based driving techniques, GOA technology significantly reduces manufacturing costs and allows for smaller left and right bezels on the display panel. A typical GOA driving circuit includes cascaded multi-stage GOA driving units. Each stage drives one row of pixels on the display panel, and the cascading of multiple GOA driving units enables line-by-line scanning of the display panel.
[0003] Typically, when a display device is powered off, all internal nodes in the GOA driver unit used for storing and transmitting voltage levels need to be pulled down to a low level to discharge residual charge. Specifically, when the display device is powered off, each node is first pulled up to a high level and then pulled down to a low level. However, some transistors in the GOA driver unit are diode-connected. The sources and gates of these transistors are synchronously pulled to the same high level after the display device is powered off. This causes these transistors to remain in an off state after the display device is powered off, preventing discharge of the nodes corresponding to their drains. Consequently, other transistors controlled by these nodes remain forward-biased, shortening their lifespan. Summary of the Invention
[0004] In view of this, embodiments of this application provide a GOA driving unit, a GOA driving circuit, and a display device to solve the technical problem of short lifespan of some transistors in the GOA driving unit.
[0005] In a first aspect, embodiments of this application provide a GOA driving unit, including:
[0006] A pull-up control module, connected to a pull-up control node, is used to output a pull-up control signal to the pull-up control node based on a first input signal and a second input signal;
[0007] A pull-up module, connected to the pull-up control node and the output node, is used to output a trigger signal and a gate drive signal from the output node according to the pull-up control signal and the scan clock signal;
[0008] A pull-down module, connected to the pull-up control node, is used to pull the pull-up control node down to a first low level according to a high-level third input signal;
[0009] A pull-down control module, connected to the pull-up control node and the output node, is used to maintain the pull-up control node and the trigger signal at the first low level and pull the output node down to the second low level according to the second input signal and the latch clock signal; the pull-down control module is also used to pull the target node down to the first low level according to the preset high-level signal and the high-level latch clock signal connected when the display device is powered off; the target node includes the pull-down control node;
[0010] A reset module, connected to the pull-up control node, is used to pull down and reset the pull-up control node according to a high-level reset signal.
[0011] In one alternative implementation of the first aspect, the drop-down control module includes:
[0012] The first inverting module is connected to the pull-up control node and the first pull-down control node, and is used to output a first inverted signal to the first pull-down control node according to the preset high-level signal, the first latch clock signal and the second input signal; it is also used to pull down the first pull-down control node to a first low level according to the preset high-level signal and the high-level first latch clock signal connected when the display device is powered off.
[0013] The second inverting module is connected to the pull-up control node and the second pull-down control node, and is used to output a second inverted signal to the second pull-down control node according to the preset high-level signal, the second latch clock signal and the second input signal; it is also used to pull down the second pull-down control node to a first low level according to the preset high-level signal and the high-level second latch clock signal connected when the display device is powered off.
[0014] The first pull-down sustaining module is connected to the pull-up control node, the output node, and the first pull-down control node, and is used to maintain the pull-up control node and the trigger signal at a first low level according to the high-level first inverted signal, and pull down the output node to a second low level;
[0015] The second pull-down sustaining module is connected to the pull-up control node, the output node, and the second pull-down control node, and is used to maintain the pull-up control node and the trigger signal at the first low level according to the high-level second inverted signal, and pull down the output node to the second low level;
[0016] The first latch clock and the second latch clock signal are opposite signals.
[0017] In one alternative implementation of the first aspect, the first inverting module includes a first transistor, a second transistor, and a third transistor;
[0018] The source of the first transistor is used to connect to the preset high-level signal, the gate of the first transistor is used to connect to the first latch clock signal, the drain of the first transistor, the source of the second transistor, and the source of the third transistor are all connected to the first pull-down control node, the gate of the second transistor is used to connect to the second input signal, the gate of the third transistor is connected to the pull-up control node, and the drain of the second transistor and the drain of the third transistor are connected to the first low-level terminal.
[0019] In one alternative implementation of the first aspect, the second inverting module includes a fourth transistor, a fifth transistor, and a sixth transistor;
[0020] The source of the fourth transistor is used to connect to the preset high-level signal, the gate of the fourth transistor is used to connect to the second latch clock signal, the drain of the fourth transistor, the source of the fifth transistor, and the source of the sixth transistor are all connected to the second pull-down control node, the gate of the fifth transistor is used to connect to the second input signal, the gate of the sixth transistor is connected to the pull-up control node, and the drains of the fifth transistor and the sixth transistor are connected to the first low-level terminal.
[0021] In one alternative implementation of the first aspect, the first inverting module includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
[0022] The source of the first transistor and the source of the second transistor are used to connect to the preset high-level signal. The gate of the first transistor is used to connect to the first latch clock signal. The drain of the first transistor, the gate of the second transistor, and the source of the third transistor are all connected to the first intermediate sustaining node. The gate of the third transistor and the gate of the fourth transistor are all connected to the pull-up control node. The drain of the second transistor, the source of the fourth transistor, and the source of the fifth transistor are all connected to the first pull-down control node. The gate of the fifth transistor is used to connect to the second input signal. The drain of the third transistor, the drain of the fourth transistor, and the drain of the fifth transistor are connected to the first low-level terminal.
[0023] In one alternative implementation of the first aspect, the second inverting module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;
[0024] The source of the sixth transistor and the source of the seventh transistor are used to connect to the preset high-level signal. The gate of the sixth transistor is used to connect to the second latch clock signal. The drain of the sixth transistor, the gate of the seventh transistor, and the source of the eighth transistor are all connected to the second intermediate sustaining node. The gate of the eighth transistor and the gate of the ninth transistor are all connected to the pull-up control node. The drain of the seventh transistor, the source of the ninth transistor, and the source of the tenth transistor are all connected to the second pull-down control node. The gate of the tenth transistor is used to connect to the second input signal. The drain of the eighth transistor, the drain of the ninth transistor, and the drain of the tenth transistor are connected to the first low-level terminal.
[0025] In one alternative implementation of the first aspect, the first inverting module further includes a first capacitor;
[0026] The first end of the first capacitor is connected to the first intermediate sustaining node, and the second end of the first capacitor is connected to the first pull-down control node.
[0027] In one alternative implementation of the first aspect, the second inverting module further includes a second capacitor;
[0028] The first end of the second capacitor is connected to the second intermediate sustaining node, and the second end of the second capacitor is connected to the second pull-down control node.
[0029] Secondly, embodiments of this application provide a GOA driving circuit, including multiple cascaded GOA driving units as described in any optional implementation of the first aspect above; the first input signal connected to each GOA driving unit is the gate driving signal output by the upper k-level GOA driving unit, the second input signal connected to each GOA driving unit is the trigger signal output by the upper k-level GOA driving unit, and the third input signal connected to each GOA driving unit is the trigger signal output by the lower j-level GOA driving unit; k and j are positive integers.
[0030] Thirdly, embodiments of this application provide a display device including the GOA driving circuit as described in the second aspect above.
[0031] Implementing the GOA driving unit, GOA driving circuit, and display device provided in the embodiments of this application has the following beneficial effects:
[0032] The GOA driving unit provided in this application embodiment, by separately connecting a preset high-level signal and a high-level latching clock signal to the pull-down control module when the display device is powered off, enables the pull-down control module to first pull up the target node, including the pull-down control node, to a high level and then pull it down to a first low level after the display device is powered off. This achieves the discharge of residual charge on the target node, so that the transistor controlled by the target node will no longer be subjected to voltage stress and thus be forward biased after the display device is powered off, thereby improving the service life of the transistor controlled by the target node. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application;
[0035] Figure 2 A schematic diagram of the structure of a GOA driving unit provided in another embodiment of this application;
[0036] Figure 3 A waveform diagram of each signal accessed when a GOA driving unit is working normally, provided for an embodiment of this application;
[0037] Figure 4 A schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application;
[0038] Figure 5 A schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application;
[0039] Figure 6 A schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application;
[0040] Figure 7 This is a waveform diagram of each node / access signal in the GOA driving unit after the display device is powered off, provided as an embodiment of this application. Detailed Implementation
[0041] The following embodiments are only used to illustrate the technical solutions of this application more clearly, and are therefore only examples and should not be used to limit the scope of protection of this application.
[0042] In the description of the embodiments of this application, the technical terms "comprising," "including," "having," and any variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. In the description of the embodiments of this application, unless otherwise stated, the technical term "multiple" refers to two or more, and the technical terms "at least one" or "one or more" refer to one, two, or more than two. The technical terms "first," "second," etc., are only used to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary / secondary relationship of the indicated technical features. The technical term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0043] This application first provides a GOA driving circuit, which may include cascaded multi-level GOA driving units. Each level of GOA driving unit can be used to drive a row of pixels on the display panel, and the cascading of multiple levels of GOA driving units can realize line-by-line scanning of the display panel.
[0044] This application also provides a GOA driving unit. Multiple levels of this GOA driving unit can be cascaded to obtain the aforementioned GOA driving circuit. Please refer to... Figure 1 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application. Figure 1 As shown, the GOA drive unit may include a pull-up control module 10, a pull-up module 20, a pull-down module 30, a pull-down control module 40, and a reset module 50.
[0045] The pull-up control module 10 can be connected to the pull-up control node Qn. The pull-up control module 10 can receive a first input signal G(nk) and a second input signal ST(nk), and output a pull-up control signal to the pull-up control node Qn based on the first input signal G(nk) and the second input signal ST(nk). For example, the pull-up control module 10 can output a high-level pull-up control signal to the pull-up control node Qn based on a high-level first input signal G(nk) and a high-level second input signal ST(nk).
[0046] Pull-up module 20 can be connected to pull-up control node Qn and output nodes (Rn1 and Rn2). Pull-up module 20 can be used to receive scan clock signal CLK, and output trigger signal ST(n) and gate drive signal G(n) according to the pull-up control signal and scan clock signal CLK. For example, pull-up module 20 can output high-level trigger signal ST(n) and high-level gate drive signal G(n) according to high-level pull-up control signal and high-level scan clock signal CLK.
[0047] The pull-down module 30 can be connected to the pull-up control node Qn. The pull-down module 30 can be used to receive the third input signal ST(n+j), and the high-level third input signal ST(n+j) pulls the pull-up control node Qn down to the first low level VSSQ.
[0048] The pull-down control module 40 can be connected to the pull-up control node Qn and the output nodes (Rn1 and Rn2). The pull-down control module 40 can be used to receive the second input signal ST(nk) and the latch clock signal LC, and based on the high-level second input signal ST(nk) and the high-level latch clock signal LC, it maintains the pull-up control node Qn at the first low level VSSQ and pulls the output nodes (Rn1 and Rn2) down to the second low level VSSG. The first low level VGGQ can be less than the second low level VGGS.
[0049] Furthermore, the pull-down control module 40 is also used to pull the target node down to a first low level VSSQ based on the preset high-level signal VGH and the high-level latch clock signal LC that are connected when the display device is powered off. For example, the target node may include an intermediate sustaining node and a pull-down control node.
[0050] The reset module 50 can be connected to the pull-up control node Qn. The reset module 50 can be used to receive the reset signal Reset, and pull down the pull-up control node Qn to the first level VSSQ according to the high-level reset signal Reset, so as to perform pull-down reset on the pull-up control node Qn.
[0051] The first input signal G(nk) can be the gate drive signal output by the k-th level GOA drive unit. The second input signal ST(nk) can be the trigger signal output by the k-th level GOA drive unit, and the third input signal ST(n+j) can be the trigger signal output by the j-th level GOA drive unit. Both k and j are positive integers, and j can be greater than k. k and j can be determined based on the number of cycles of the scan clock signal CLK. The second input signal ST(nk) can be used to start the current level GOA drive unit. Based on this, the trigger signal ST(n) output by the upper module 10 can be used to start the G(n+k) level GOA drive units. The third input signal ST(n+j) can be used to perform pull-down control on the current level GOA drive unit. The gate drive signal G(n) output by the pull-up module 20 can be used to drive a row of pixels corresponding to the current level GOA drive unit.
[0052] As can be seen from the above, the GOA driving circuit provided in this embodiment, by separately connecting a preset high-level signal and a high-level latching clock signal to the pull-down control module when the display device is powered off, enables the pull-down control module to first pull up the target node, including the pull-down control node, to a high level and then pull it down to a first low level after the display device is powered off. This achieves the discharge of residual charge on the target node, so that the transistor controlled by the target node will no longer be subjected to voltage stress and thus be forward biased after the display device is powered off, thereby improving the service life of the transistor controlled by the target node.
[0053] Furthermore, by maintaining the pull-up control node at the first low level and pulling the output node down to the second low level through the pull-down control module, and setting the first low level to be less than the second low level, the voltage difference between the pull-up control signal and the gate drive signal can be less than 0, thereby subjecting the pull-up module to negative stress rather than positive bias, thus improving the stability of the high-level gate drive signal.
[0054] Please see Figure 2 This is a schematic diagram of the structure of a GOA driving unit provided in another embodiment of this application. Figure 2 As shown, with Figure 1 Compared to the corresponding embodiments, the pull-down control module 40 in this embodiment may include a first inverting module 401, a second inverting module 402, a first pull-down sustaining module 403, and a second pull-down sustaining module 404.
[0055] The first inverting module 401 can be connected to the pull-up control node Qn and the first pull-down control node Kn. The first inverting module 401 can receive a preset high-level signal VGH, a first latch clock signal LC1, and a second input signal ST(nk), and output a first inverted signal to the first pull-down control node Kn based on the preset high-level signal VGH, the first latch clock signal LC1, and the second input signal ST(nk). For example, the first inverting module 401 can output a first inverted signal corresponding to the pull-up control signal to the pull-down control node Kn based on the preset high-level signal VGH, the high-level first latch clock signal LC1, and the high-level second input signal ST(nk).
[0056] In addition, the first inverting module 401 can also be used to pull down the first pull-down control node Qn to the first low level VSSQ based on the preset high-level signal VGH and the high-level first latch clock signal LC1 that are connected when the display device is powered off.
[0057] The second inverting module 402 can be connected to the pull-up control node Qn and the second pull-down control node Pn. The second inverting module 402 can receive a preset high-level signal VGH, a second latch clock signal LC2, and a second input signal ST(nk), and output a second inverted signal to the second pull-down control node Pn based on these signals. For example, the second inverting module 402 can output a second inverted signal corresponding to the pull-up control signal to the pull-down control node Kn based on the preset high-level signal VGH, the high-level second latch clock signal LC2, and the high-level second input signal ST(nk).
[0058] In addition, the second inverting module 402 can also be used to pull down the second pull-down control node Pn to the first low level VSSQ based on the preset high-level signal VGH and the high-level second latch clock signal LC2 that are connected when the display device is powered off.
[0059] The first pull-down sustaining module 403 can be connected to the pull-up control node Qn, the first output node Rn1, the second output node Rn2, and the first pull-down control node Kn. The first pull-down sustaining module 403 can be used to maintain the pull-up control node Qn and the second output node Rn2 at a first low level VSSQ, and / or pull down the first output node Rn1 to a second low level VSSG, according to a high-level first inverted signal.
[0060] The second pull-down sustaining module 404 can be connected to the pull-up control node Qn, the first output node Rn1, the second output node Rn2, and the second pull-down control node Pn. The second pull-down sustaining module 404 can be used to maintain the pull-up control node Qn and the second output node Rn2 at a first low level VSSQ and / or pull down the first output node Rn1 to a second low level VSSG according to the high-level second inverted signal.
[0061] For example, such as Figure 3 As shown, the first latch clock signal LC1 and the second latch clock signal LC2 can be two opposite clock signals. For example, when the first latch clock signal LC1 is high, the second latch clock signal LC2 can be low; when the first latch clock signal LC1 is low, the second latch clock signal LC2 can be high. By setting the first latch clock signal LC1 and the second latch clock signal LC2 to opposite clock signals, the first inverting module 401 and the first pull-down sustaining module 403 can operate alternately with the second inverting module 402 and the second pull-down sustaining module 403, thereby reducing the forward bias drift problem caused by some transistors in the inverting module and the pull-down sustaining module being constantly in the on state. That is, by setting two inverting modules and pull-down sustaining modules with identical structures in the pull-down control module, and setting the latch clock signals of the two inverting modules to opposite clock signals, the stability of the GOA driving unit can be improved by the alternating operation of the two inverting modules and the pull-down sustaining module.
[0062] Please see Figure 4 This is a schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application. Figure 4 As shown, in one optional implementation, the first inverting module 401 may include a first transistor T1, a second transistor T2, and a third transistor T3. The source of the first transistor T1 can be connected to a preset high-level signal VGH, and the gate of the first transistor T1 can be connected to a first latch clock signal terminal LC1. The drain of the first transistor T1, the source of the second transistor T2, and the source of the third transistor T3 can all be connected to a first pull-down control node Kn. The gate of the second transistor T2 can be connected to a second input signal ST(nk), and the gate of the third transistor T3 can be connected to a pull-up control node Qn. The drains of the second transistor T2 and the third transistor T3 can be connected to a first low-level terminal.
[0063] The second inverting module 402 may include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The source of the fourth transistor T4 can be connected to a preset high-level signal VGH, and the gate of the fourth transistor T4 can be connected to a second latch clock signal terminal LC2. The drain of the fourth transistor T4, the source of the fifth transistor T5, and the source of the sixth transistor T6 can all be connected to a second pull-down control node Pn. The gate of the fifth transistor T5 can be connected to a second input signal ST(nk), and the gate of the sixth transistor T6 can be connected to a pull-up control node Qn. The drains of the fifth transistor T5 and the sixth transistor T6 can be connected to a first low-level terminal.
[0064] The first pull-down sustaining module 403 may include a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The source of the seventh transistor T7 may be connected to the pull-up control node Qn, the source of the eighth transistor T8 may be connected to the first output terminal of the pull-up module 20, and the source of the ninth transistor T9 may be connected to the second output terminal of the pull-up module 20. The gates of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may be shared by the first pull-down control node Kn. The drains of the seventh transistor T7 and the eighth transistor T8 may be connected to a first low-level terminal, and the drain of the ninth transistor T9 may be connected to a second low-level terminal.
[0065] The second pull-down sustaining module 404 may include a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The source of the tenth transistor T10 may be connected to the pull-up control node Qn, the source of the eleventh transistor T11 may be connected to the first output terminal of the pull-up module 20, and the source of the twelfth transistor T12 may be connected to the second output terminal of the pull-up module 20. The gates of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 may be connected to the second pull-down control node Pn. The drains of the tenth transistor T10 and the eleventh transistor T11 may be connected to the first low-level terminal, and the drain of the twelfth transistor T12 may be connected to the second low-level terminal.
[0066] The first output terminal of the pull-up module 20 can be used to output a trigger signal ST(n), and the second output terminal of the pull-up module 20 can be used to output a gate drive signal G(n). The first low-level terminal is used to provide a first low level VSSQ, and the second low-level terminal is used to provide a second low level VSSG.
[0067] Optionally, the pull-up control module 10 may include a seventeenth transistor T17. The source of the seventeenth transistor T17 can be used to connect to the first input signal G(nk), the gate of the seventeenth transistor T17 can be used to connect to the second input signal ST(nk), and the drain of the seventeenth transistor T17 can be connected to the pull-up control node Qn.
[0068] The pull-up module 20 may include an eighteenth transistor T18, a nineteenth transistor T19, and a third capacitor C3. The source of the eighteenth transistor T18 and the source of the nineteenth transistor T19 can be used to connect to the scan clock signal CLK. The gate of the eighteenth transistor T18, the first terminal of the third capacitor C3, and the gate of the nineteenth transistor T19 can be connected to the pull-up control node Qn. The drain of the eighteenth transistor T18 can be connected to the second output node Rn2, and the second terminal of the third capacitor C3 and the drain of the nineteenth transistor T19 can be connected to the first output node Rn1.
[0069] The pull-down module 30 may include a twentieth transistor T20. The source of the twentieth transistor T20 may be connected to the pull-up control node Qn, the gate of the twentieth transistor T20 may be used to connect to the third input signal ST(n+j), and the drain of the twentieth transistor T20 may be connected to the first low-level terminal.
[0070] The reset module 50 may include a twenty-first transistor T21. The source of the twenty-first transistor T21 may be connected to the pull-up control node Qn, the gate of the twenty-first transistor T21 may be used to receive the reset signal Reset, and the drain of the twenty-first transistor T21 may be connected to the first low-level terminal.
[0071] according to Figure 4 It is known that when the display device is powered off, the gate and source of the first transistor T1 in the first inverter module 401 are respectively connected to the first latch clock signal LC1 and the preset high-level signal VGH, thus pulling the gate and source of the first transistor T1 to high levels respectively. Since the source of the first transistor T1 discharges faster after being pulled up to a high level, while the gate discharges slower, the first transistor T1 can be forward-biased, allowing the first pull-down control node Kn to fully discharge. After the first pull-down control node Kn is fully discharged, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9, controlled by the first pull-down control node Kn, are no longer forward-biased due to voltage stress, thus extending their lifespan.
[0072] Similarly, since the structure of the second inverter module 402 is the same as that of the first inverter module 401, it can also extend the service life of the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 based on the same principle as the first inverter module 401.
[0073] Please see Figure 5 This is a schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application. Figure 5 As shown, in another optional implementation, the first inverting module 401 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The source of the first transistor T1 and the source of the second transistor T2 can be used to connect to a preset high-level signal VGH. The gate of the first transistor T1 can be used to connect to a first latching clock signal LC1. The drain of the first transistor T1, the gate of the second transistor T2, and the source of the third transistor T3 can be connected to a first intermediate sustaining node Sn. The gate of the third transistor T3 and the gate of the fourth transistor T4 can be connected to a pull-up control node Qn. The drain of the second transistor T2, the source of the fourth transistor T4, and the source of the fifth transistor T5 can be connected to a first pull-down control node Kn. The gate of the fifth transistor T5 can be used to connect to a second input signal ST(nk). The drains of the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can all be connected to a first low-level terminal.
[0074] The second inverting module 402 may include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The source of the sixth transistor T6 and the source of the seventh transistor T7 can be connected to a preset high-level signal VGH. The gate of the sixth transistor T6 can be connected to a second latch clock signal LC2. The drain of the sixth transistor T6, the gate of the seventh transistor T7, and the source of the eighth transistor T8 can be connected to a second intermediate sustaining node Tn. The gate of the eighth transistor T8 and the gate of the ninth transistor T9 can be connected to a pull-up control node Qn. The drain of the seventh transistor T7, the source of the ninth transistor T9, and the source of the tenth transistor T10 can be connected to a second pull-down control node Pn. The gate of the tenth transistor T10 can be connected to a second input signal ST(nk). The drains of the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can all be connected to a first low-level terminal.
[0075] The first pull-down sustaining module 403 may include an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The source of the eleventh transistor T11 can be connected to the pull-up control node Qn, the source of the twelfth transistor T12 can be connected to the second output node Rn2, and the source of the thirteenth transistor T13 can be connected to the first output node Rn1. The gates of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 can be shared by the first pull-down control node Kn. The drains of the eleventh transistor T11 and the twelfth transistor T12 can be connected to a first low-level terminal, and the drain of the thirteenth transistor T13 can be connected to a second low-level terminal.
[0076] The second pull-down sustaining module 404 may include a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16. The source of the fourteenth transistor T14 can be connected to the pull-down control node Qn, the source of the fifteenth transistor T15 can be connected to the second output node Rn2, and the source of the sixteenth transistor T6 can be connected to the first output node Rn1. The gates of the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 can be shared by the second pull-down control node Pn. The drains of the fourteenth transistor T14 and the fifteenth transistor T15 can be connected to a first low-level terminal, and the drain of the sixteenth transistor T16 can be connected to a second low-level terminal.
[0077] according to Figure 5 It is known that when the display device is powered off, the gate and source of the first transistor T1 in the first inverter module 401 are respectively connected to the first latch clock signal LC1 and the preset high-level signal VGH, thus pulling the gate and source of the first transistor T1 to a high level. Since the source of the first transistor T1 discharges quickly after being pulled to a high level, while the gate discharges slowly after being pulled to a high level, the first transistor T1 can be forward-biased, thereby maintaining the first intermediate holding node Sn at a high level for a period of time, and consequently, the second transistor T2 is also forward-biased. Thus, the first intermediate holding node Sn and the first pull-down control node Kn can be completely discharged. After the first pull-down control node Kn is completely discharged, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13, whose gates are connected to the first pull-down control node Kn, are no longer forward-biased due to voltage stress, thereby extending the lifespan of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13.
[0078] Similarly, since the structure of the second inverter module 402 is the same as that of the first inverter module 401, it can also extend the service life of the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 based on the same principle as the first inverter module 401.
[0079] Please see Figure 6 This is a schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application. Figure 6 As shown, with Figure 5 Compared to the corresponding embodiments, the first inverting module 401 in this embodiment may further include a first capacitor C1. The first end of the first capacitor C1 may be connected to the first intermediate holding node Sn, and the second end of the first capacitor C1 may be connected to the first pull-down control node Kn.
[0080] The second inverting module 402 may further include a second capacitor C2. The first terminal of the second capacitor C2 may be connected to the second intermediate holding node Tn, and the second terminal of the second capacitor C2 may be connected to the second pull-down control node Pn.
[0081] according to Figure 6 It is understood that by connecting a first capacitor between the first intermediate sustaining node Sn and the first pull-down control node Kn, and connecting a second capacitor between the second intermediate sustaining node Tn and the second pull-down control node Pn, the completeness of the discharge of the first pull-down control node Kn and the second pull-down control node Pn after the display device is powered off can be further improved, thereby further extending the service life of the transistor whose gate is connected to the first pull-down control node Kn and the second pull-down control node Pn.
[0082] For example, please refer to Figure 7 This is a waveform diagram of each node / access signal in the GOA driving unit after the display device is powered off, provided in an embodiment of this application.
[0083] like Figure 7 As shown, the GOA driving unit provided in this application embodiment can pull all signals connected to the GOA driving unit and all nodes in the GOA driving unit to a high level after the display device is turned off, and then slowly drop to a low level.
[0084] This application also provides a display device, which includes the above-described GOA driving circuit.
[0085] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units is merely an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the GOA driver unit can be divided into different functional units to complete all or part of the functions described above. Furthermore, the specific names of each functional unit are only for easy differentiation and are not intended to limit the scope of protection of this application.
[0086] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.
[0087] It should be noted that, unless otherwise specified, all technical terms used in the embodiments of this application have the same meaning as commonly understood by those skilled in the art to which this application belongs. The technical terms used in the embodiments of this application are only used to explain specific embodiments of this application and are not intended to limit this application.
[0088] The term "embodiment" as used in the description of embodiments in this application means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0089] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0090] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A GOA driving unit, characterized in that, include: A pull-up control module, connected to a pull-up control node, is used to output a pull-up control signal to the pull-up control node based on a first input signal and a second input signal; A pull-up module, connected to the pull-up control node and the output node, is used to output a trigger signal and a gate drive signal from the output node according to the pull-up control signal and the scan clock signal; A pull-down module, connected to the pull-up control node, is used to pull the pull-up control node down to a first low level according to a high-level third input signal; A pull-down control module, connected to the pull-up control node and the output node, is used to maintain the pull-up control node and the trigger signal at the first low level and pull the output node down to the second low level according to the second input signal and the latch clock signal; the pull-down control module is also used to pull the target node down to the first low level according to the preset high-level signal and the high-level latch clock signal connected when the display device is powered off; the target node includes the pull-down control node; A reset module, connected to the pull-up control node, is used to pull down and reset the pull-up control node according to a high-level reset signal.
2. The GOA driving unit according to claim 1, characterized in that, The drop-down control module includes: The first inverting module is connected to the pull-up control node and the first pull-down control node, and is used to output a first inverted signal to the first pull-down control node according to the preset high-level signal, the first latch clock signal and the second input signal; it is also used to pull down the first pull-down control node to a first low level according to the preset high-level signal and the high-level first latch clock signal connected when the display device is powered off. The second inverting module is connected to the pull-up control node and the second pull-down control node, and is used to output a second inverted signal to the second pull-down control node according to the preset high-level signal, the second latch clock signal and the second input signal; it is also used to pull down the second pull-down control node to a first low level according to the preset high-level signal and the high-level second latch clock signal connected when the display device is powered off. The first pull-down sustaining module is connected to the pull-up control node, the output node, and the first pull-down control node, and is used to maintain the pull-up control node and the trigger signal at a first low level according to the high-level first inverted signal, and pull down the output node to a second low level; The second pull-down sustaining module is connected to the pull-up control node, the output node, and the second pull-down control node, and is used to maintain the pull-up control node and the trigger signal at the first low level according to the high-level second inverted signal, and pull down the output node to the second low level; The first latch clock and the second latch clock signal are opposite signals.
3. The GOA driving unit according to claim 2, characterized in that, The first inverting module includes a first transistor, a second transistor, and a third transistor; The source of the first transistor is used to connect to the preset high-level signal, the gate of the first transistor is used to connect to the first latch clock signal, the drain of the first transistor, the source of the second transistor, and the source of the third transistor are all connected to the first pull-down control node, the gate of the second transistor is used to connect to the second input signal, the gate of the third transistor is connected to the pull-up control node, and the drain of the second transistor and the drain of the third transistor are connected to the first low-level terminal.
4. The GOA driving unit according to claim 2 or 3, characterized in that, The second inverting module includes a fourth transistor, a fifth transistor, and a sixth transistor; The source of the fourth transistor is used to connect to the preset high-level signal, the gate of the fourth transistor is used to connect to the second latch clock signal, the drain of the fourth transistor, the source of the fifth transistor, and the source of the sixth transistor are all connected to the second pull-down control node, the gate of the fifth transistor is used to connect to the second input signal, the gate of the sixth transistor is connected to the pull-up control node, and the drains of the fifth transistor and the sixth transistor are connected to the first low-level terminal.
5. The GOA driving unit according to claim 2, characterized in that, The first inverting module includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; The source of the first transistor and the source of the second transistor are used to connect to the preset high-level signal. The gate of the first transistor is used to connect to the first latch clock signal. The drain of the first transistor, the gate of the second transistor, and the source of the third transistor are all connected to the first intermediate sustaining node. The gate of the third transistor and the gate of the fourth transistor are all connected to the pull-up control node. The drain of the second transistor, the source of the fourth transistor, and the source of the fifth transistor are all connected to the first pull-down control node. The gate of the fifth transistor is used to connect to the second input signal. The drain of the third transistor, the drain of the fourth transistor, and the drain of the fifth transistor are connected to the first low-level terminal.
6. The GOA driving unit according to claim 2 or 5, characterized in that, The second inverting module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The source of the sixth transistor and the source of the seventh transistor are used to connect to the preset high-level signal. The gate of the sixth transistor is used to connect to the second latch clock signal. The drain of the sixth transistor, the gate of the seventh transistor, and the source of the eighth transistor are all connected to the second intermediate sustaining node. The gate of the eighth transistor and the gate of the ninth transistor are all connected to the pull-up control node. The drain of the seventh transistor, the source of the ninth transistor, and the source of the tenth transistor are all connected to the second pull-down control node. The gate of the tenth transistor is used to connect to the second input signal. The drain of the eighth transistor, the drain of the ninth transistor, and the drain of the tenth transistor are connected to the first low-level terminal.
7. The GOA driving unit according to claim 5, characterized in that, The first inverting module also includes a first capacitor; The first end of the first capacitor is connected to the first intermediate sustaining node, and the second end of the first capacitor is connected to the first pull-down control node.
8. The GOA driving unit according to claim 6, characterized in that, The second inverting module also includes a second capacitor; The first end of the second capacitor is connected to the second intermediate sustaining node, and the second end of the second capacitor is connected to the second pull-down control node.
9. A GOA driving circuit, characterized in that, The system includes cascaded multi-stage GOA driving units as described in any one of claims 1-8; the first input signal connected to each stage of the GOA driving unit is the gate driving signal output by the GOA driving unit of the previous k stages, the second input signal connected to each stage of the GOA driving unit is the trigger signal output by the GOA driving unit of the previous k stages, and the third input signal connected to each stage of the GOA driving unit is the trigger signal output by the GOA driving unit of the next j stages; k and j are positive integers.
10. A display device, characterized in that, Includes the GOA driving circuit as described in claim 9.