Goa driving unit, goa driving circuit and display device
By incorporating multiple signal combinations into the inverting module of the GOA driver unit to control the level change of the pull-down control node, the short lifespan problem caused by the transistor being normally on is solved, thereby extending the transistor's lifespan and improving the durability of the GOA driver unit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG LAIBAO DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-05-29
AI Technical Summary
In existing GOA driver units, because the inverting module is connected to the pull-up control node and the inverting module is only connected to a preset high-level signal, the transistor in the pull-down holding module is in a normally open state, which shortens the lifespan of the transistor and thus the lifespan of the entire GOA driver unit is relatively short.
By connecting the second scan clock signal and a preset high-level signal, or the third scan clock signal, or the first scan clock signal and a preset high-level signal to the inverting module, the inverting signal level of the pull-down control node is controlled, so that it follows the level change of the scan clock signal. This allows the pull-down sustaining module to alternate between normal operation and stop operation, reducing the forward bias speed of the transistor.
This extends the lifespan of the transistors in the pull-down sustain module, thereby extending the lifespan of the entire GOA drive unit.
Smart Images
Figure CN224304342U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, and in particular relates to a GOA driving unit, a GOA driving circuit and a display device. Background Technology
[0002] Integrating gate driver on array (GOA) circuitry onto a glass substrate involves integrating the gate driver circuitry of the display panel onto the glass substrate, forming a scanning drive for the display panel. Compared to traditional gate chip-based driving technologies, GOA driving technology can significantly reduce manufacturing costs and reduce the left and right bezels of the display panel. A GOA driving circuit typically includes cascaded multi-stage GOA driving units. Each stage of the GOA driving unit drives one row of pixel units on the display panel. By cascading multiple stages of GOA driving units, line-by-line scanning of the display panel can be achieved.
[0003] In existing GOA driver units, since the inverting module is connected to the pull-up control node and the inverting module is only connected to a preset high-level signal, when the pull-up control node is low, some transistors in the inverting module will be in a normally open state under the control of the preset high-level signal. This causes the transistors in the pull-down sustaining module to always be in a forward-biased state, thereby shortening the lifespan of the transistors in the pull-down sustaining module and resulting in a shorter lifespan for the entire GOA driver unit. Summary of the Invention
[0004] In view of this, embodiments of this application provide a GOA driving unit, a GOA driving circuit, and a display device to solve the technical problem of the short service life of existing GOA drivers.
[0005] In a first aspect, embodiments of this application provide a GOA driving unit, including:
[0006] A pull-up control module, connected to a pull-up control node, is used to output a high-level pull-up control signal to the pull-up control node based on a high-level first input signal;
[0007] A pull-up module, connected to the pull-up control node and the output node, is used to output a gate drive signal from the output node according to the pull-up control signal and the first scan clock signal;
[0008] A pull-down module, connected to the pull-up control node, is used to pull the pull-up control node down to a low level according to a high-level second input signal;
[0009] An inverting module, connected to the pull-up control node and the pull-down control node, is used to receive a second scan clock signal and a preset high-level signal, or a third scan clock signal, or the third scan clock signal and the preset high-level signal, or the first scan clock signal and the preset high-level signal, and outputs an inverted signal of the pull-up control signal to the pull-down control node according to the received signal; the level of the inverted signal follows the level of the scan clock signal received by the inverting module.
[0010] A pull-down sustaining module, connected to the pull-up control node, the pull-down control node, and the output node, is used to maintain the pull-up control node and the output node at a low level according to the high-level inverted signal;
[0011] A reset module, connected to the pull-up control node and the output node, is used to pull the pull-up control node and the output node down to a low level according to a high-level reset signal.
[0012] In one alternative implementation of the first aspect, the pull-up control module includes a first transistor;
[0013] The gate and source of the first transistor are used to receive the first input signal, and the drain of the first transistor is connected to the pull-up control node.
[0014] In one alternative implementation of the first aspect, the pull-up module includes a second transistor and a first capacitor;
[0015] The gate of the second transistor and the first terminal of the first capacitor are both connected to the pull-up control node, the source of the second transistor is used to connect to the first scan clock signal, and the drain of the second transistor and the second terminal of the first capacitor are both connected to the output node.
[0016] The pull-down module includes a third transistor;
[0017] The gate of the third transistor is used to receive the second input signal, the source of the third transistor is connected to the pull-up control node, and the drain of the third transistor is connected to the low-level terminal.
[0018] In one optional implementation of the first aspect, when the inverting module is connected to a second scan clock signal and a preset high-level signal, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.
[0019] The gate and source of the fourth transistor are used to connect to the preset high-level signal. The drain of the fourth transistor, the source of the fifth transistor, and the gate of the sixth transistor are all connected to the intermediate sustaining node. The source of the sixth transistor is used to connect to the second scan clock signal. The gate of the fifth transistor and the gate of the seventh transistor are all connected to the pull-up control node. The drain of the sixth transistor and the source of the seventh transistor are all connected to the pull-down control node. The drain of the fifth transistor and the drain of the seventh transistor are connected to the low-level terminal.
[0020] In one alternative implementation of the first aspect, the inverting module further includes a second capacitor connected between the intermediate sustaining node and the pull-down control node.
[0021] In one alternative implementation of the first aspect, when the inverting module is connected to a third scan clock signal, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.
[0022] The gate, source, and source of the fourth transistor are used to receive the third scan clock signal. The drain, gate, and source of the fourth transistor are connected to the intermediate sustain node. The drain and source of the sixth transistor are connected to the pull-down control node. The gate and gate of the fifth transistor are connected to the pull-up control node. The drain and drain of the fifth transistor are connected to the low-level terminal.
[0023] In an optional implementation of the first aspect, when the inverting module is connected to the first scan clock signal and the preset high-level signal, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.
[0024] The gate and source of the fourth transistor are used to connect to the first scan clock signal, the source of the sixth transistor is used to connect to the preset high-level signal, the drain of the fourth transistor, the source of the fifth transistor, and the gate of the sixth transistor are all connected to the intermediate sustaining node, the drain of the sixth transistor and the source of the seventh transistor are all connected to the pull-down control node, the gate of the fifth transistor and the gate of the seventh transistor are all connected to the pull-up control node, and the drain of the fifth transistor and the drain of the seventh transistor are connected to the low-level terminal.
[0025] In one optional implementation of the first aspect, when the inverting module is connected to the third scan clock signal and the preset high-level signal, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.
[0026] The gate of the fourth transistor and the source of the sixth transistor are used to connect to the preset high-level signal. The source of the fourth transistor is used to connect to the third scan clock signal. The drain of the fourth transistor, the source of the fifth transistor, and the gate of the sixth transistor are all connected to the intermediate sustaining node. The drain of the sixth transistor and the source of the seventh transistor are all connected to the pull-down control node. The gate of the fifth transistor and the gate of the seventh transistor are all connected to the pull-up control node. The drain of the fifth transistor and the drain of the seventh transistor are connected to the low-level terminal.
[0027] The GOA driving unit also includes a node control module;
[0028] The node control module is connected to the pull-down control node and is used to receive the fourth scan clock signal, and pull the pull-down control node down to a low level according to the high level of the fourth scan clock signal.
[0029] Secondly, embodiments of this application provide a GOA driving circuit, including cascaded multi-stage GOA driving units as described in any optional implementation of the first aspect; the first input signal connected to each stage of the GOA driving unit is the gate driving signal output by the upper k-stage GOA driving unit, the second input signal connected to each stage of the GOA driving unit is the gate driving signal output by the lower j-stage GOA driving unit, the first scan clock signal connected to each stage of the GOA driving unit is the scan clock signal corresponding to the current stage of the GOA driving unit, the second scan clock signal connected to each stage of the GOA driving unit is the scan clock signal corresponding to the upper 1-stage GOA driving unit, and the third scan clock signal connected to each stage of the GOA driving unit is the scan clock signal corresponding to the upper 2-stage GOA driving unit; k and j are positive integers.
[0030] Thirdly, embodiments of this application provide a display device including the GOA driving circuit described in the second aspect.
[0031] Implementing the GOA driving unit, GOA driving circuit, and display device provided in the embodiments of this application has the following beneficial effects:
[0032] The GOA driving unit provided in this application embodiment, by connecting a second scan clock signal and a preset high-level signal, or a third scan clock signal, or the third scan clock signal and the preset high-level signal, or the first scan clock signal and the preset high-level signal to the inverting module, enables the level of the inverted signal at the pull-down control node to follow the level of the connected scan clock signal. Since the scan clock signal periodically alternates between high and low levels, the level of the pull-down control node also periodically alternates between high and low levels. This causes the pull-down sustaining module to alternate between normal operation and shutdown, thereby reducing the forward bias speed of the transistors in the pull-down sustaining module, extending the lifespan of the transistors in the pull-down sustaining module, and thus extending the lifespan of the entire GOA driving unit. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application;
[0035] Figure 2 A schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application;
[0036] Figure 3 A waveform diagram of each node and the access signal when a GOA driving unit is working normally, provided for an embodiment of this application;
[0037] Figure 4 A schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application;
[0038] Figure 5 A schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application;
[0039] Figure 6 A schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application;
[0040] Figure 7 A schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application;
[0041] Figure 8This is a schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application. Detailed Implementation
[0042] The following embodiments are only used to illustrate the technical solutions of this application more clearly, and are therefore only examples and should not be used to limit the scope of protection of this application.
[0043] In the description of the embodiments of this application, the technical terms "comprising," "including," "having," and any variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. In the description of the embodiments of this application, unless otherwise stated, the technical term "multiple" refers to two or more, and the technical terms "at least one" or "one or more" refer to one, two, or more than two. The technical terms "first," "second," etc., are only used to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary / secondary relationship of the indicated technical features. The technical term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0044] This application first provides a GOA driving circuit, which may include cascaded multi-level GOA driving units. Each level of GOA driving unit can be used to drive a row of pixels on the display panel. The cascading of multiple levels of GOA driving units enables line-by-line scanning of the display panel.
[0045] This application also provides a GOA driving unit. Multiple levels of this GOA driving unit can be cascaded to obtain the aforementioned GOA driving circuit. Please refer to... Figure 1 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application. Figure 1 As shown, in one optional implementation, the GOA driver unit may include a pull-up control module 10, a pull-up module 20, a pull-down module 30, an inverting module 40, a pull-down sustaining module 50, and a reset module 60. Wherein:
[0046] The pull-up control module 10 can be connected to the pull-up control node Qn. The pull-up control module 10 can be used to receive the first input signal G(nk) and output a high-level pull-up control signal to the pull-up control node Qn according to the high-level first input signal G(nk).
[0047] Pull-up module 20 can be connected to pull-up control node Qn. Pull-up module 20 can be used to receive the first scan clock signal CLK(n) and output gate drive signal G(n) from output node Rn according to the pull-up control signal and the first scan clock signal CLK(n). For example, pull-up control module 20 can output high-level gate drive signal G(n) from output node Rn according to the high-level pull-up control signal and the high-level first scan clock signal CLK(n). Gate drive signal G(n) can be used to drive a row of pixel units corresponding to the current GOA driving unit, or it can be used as an input signal for other GOA driving units.
[0048] The pull-down module 30 can be connected to the pull-up control node Qn. The pull-down module 30 can be used to receive a second input signal G(n+j) and, based on the second input signal G(n+j), to pull down the pull-up control node Qn. For example, the pull-down module 30 can be used to pull the pull-up control node Qn down to a low level VSS based on the high-level second input signal G(n+j).
[0049] The inverting module 40 can be connected to the pull-up control node Qn and the pull-down control node Kn. The inverting module 40 can be used to receive the second scan clock signal CLK(n-1) and a preset high-level signal VGH, or it can be used to receive the third scan clock signal CLK(n-2) and the preset high-level signal VGH, or it can be used to receive the first scan clock signal CLK(n) and the preset high-level signal VGH. Based on the received signals, it outputs an inverted pull-up control signal to the pull-down control node Kn. The level of the inverted signal follows the level of the scan clock signal received by the inverting module 40.
[0050] The pull-down sustaining module 50 can be connected to the pull-up control node Qn, the pull-down control node Kn, and the output node Rn. The pull-down sustaining module 50 can be used to maintain the pull-up control node Qn and the output node Rn at a low level VSS based on an inverted high signal. For example, the pull-down sustaining module 50 can maintain the pull-up control node Qn and the output node Rn at a low level VSS based on an inverted high-level signal.
[0051] The reset module 60 can be connected to the pull-up control node Qn and the output node Rn. The reset module 60 can be used to reset the pull-up control node Qn and the output node Rn according to the reset signal Reset. For example, the reset module 60 can pull down the pull-up control node Qn and the output node Rn to a low level VSS according to the high-level reset signal Reset.
[0052] Wherein, the first input signal G(nk) is the gate drive signal output by the upper k-stage GOA drive unit, and the second input signal G(n+j) is the gate drive signal output by the lower j-stage GOA drive unit, where k and j are positive integers. k and j can be determined based on the number of cycles of the first scan clock signal connected to the pull-up module 20.
[0053] The first scan clock signal CLK(n) is the scan clock signal of the current level GOA driver unit, the second scan clock signal CLK(n-1) is the scan clock signal of the previous level GOA driver unit, and the third scan clock signal CLK(n-2) is the scan clock signal of the previous two levels GOA driver units.
[0054] As can be seen from the above, the embodiments of this application, by connecting a second scan clock signal and a preset high-level signal, or a third scan clock signal, or the third scan clock signal and the preset high-level signal, or the first scan clock signal and the preset high-level signal to the inverting module, enable the level of the inverted signal at the pull-down control node to follow the level of the connected scan clock signal. Since the scan clock signal periodically alternates between high and low levels, the level of the pull-down control node also periodically alternates between high and low levels. This causes the pull-down sustaining module to alternate between normal operation and shutdown, thereby reducing the forward bias speed of the transistors in the pull-down sustaining module, extending the lifespan of the transistors in the pull-down sustaining module, and consequently extending the lifespan of the entire GOA driving unit.
[0055] Please see Figure 2 This is a schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown, and are described in detail below:
[0056] like Figure 2 As shown, the pull-up control module 10 may include a first transistor T1. The gate and source of the first transistor T1 can be used to connect to the first input signal G(nk), and the drain of the first transistor T1 can be connected to the pull-up control node Qn.
[0057] The pull-up module 20 may include a second transistor T2 and a first capacitor C1. The gate of the second transistor T2 and the first terminal of the first capacitor C1 may be connected to the pull-up control node Qn. The source of the second transistor T2 may be used to connect to the first scan clock signal CLK(n). The drain of the second transistor T2 and the second terminal of the first capacitor C1 may be connected to the output node Rn. For example, the first capacitor C1 may be a bootstrap capacitor.
[0058] The pull-down module 30 may include a third transistor T3. The gate of the third transistor T3 can be used to connect to the second input signal G(n+j), the source of the third transistor T3 can be connected to the pull-up control node Qn, and the drain of the third transistor T3 can be connected to a low-level terminal. The low-level terminal is used to provide a low level VSS.
[0059] In one alternative implementation, when the inverting module 40 is connected to the second scan clock signal CLK(n-1) and the preset high-level signal VGH, such as Figure 2 As shown, the inverter module 40 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate and source of the fourth transistor T4 can be connected to a preset high-level signal VGH. The drain of the fourth transistor T4, the source of the fifth transistor T5, and the gate of the sixth transistor T6 can be connected to an intermediate sustaining node Sn. The source of the sixth transistor T6 can be connected to a second scan clock signal CLK(n-1). The gates of the fifth transistor T5 and the seventh transistor T7 can be connected to a pull-up control node Qn. The drain of the sixth transistor T6 and the source of the seventh transistor T7 can be connected to a pull-down control node Kn. The drains of the fifth transistor T5 and the seventh transistor T7 can be connected to a low-level terminal.
[0060] The pull-down sustaining module 50 may include an eighth transistor T8 and a ninth transistor T9. The gate of the eighth transistor T8 and the gate of the ninth transistor T9 may be connected to the pull-down control node Kn, the source of the eighth transistor T8 may be connected to the pull-up control node Qn, the source of the ninth transistor T9 may be connected to the output node Rn, and the drain of the eighth transistor T8 and the drain of the ninth transistor T9 may be connected to a low-level terminal.
[0061] The reset module 60 may include a tenth transistor T10 and an eleventh transistor T11. The source of the tenth transistor T10 may be connected to the pull-up control node Qn, and the source of the eleventh transistor T11 may be connected to the output node Rn. The gates of the tenth transistor T10 and the eleventh transistor T11 may be used to receive the reset signal Reset, and the drains of the tenth transistor T10 and the eleventh transistor T11 may be connected to a low-level terminal.
[0062] The following combination Figure 3 ,right Figure 2 The specific working principle of the GOA driving unit in the corresponding embodiment is explained in detail. Please refer to [link / reference]. Figure 3 This is a waveform diagram of each node and the access signal when a GOA driving unit is working normally, provided in an embodiment of this application.
[0063] like Figure 3As shown, when the first input signal G(nk) is low and the second scan clock signal CLK(n-1) is high (e.g., from stage A to B), the first transistor T1 in the pull-up control module 10 is turned off, making the pull-up control node Qn low. Simultaneously, the fifth transistor T5 and the seventh transistor T7 in the inverter module 40 are turned off. Since the gate and source of the fourth transistor T4 in the inverter module 40 are connected to a preset high-level signal VGH, the fourth transistor T4 is normally open, and the intermediate maintenance node Sn is high, thus turning on the sixth transistor T6. The second scan clock signal CLK(n-1) is directly connected to the pull-down control node Kn, therefore the level of the pull-down control node Kn follows the level of the second scan clock signal CLK(n-1). For example, when the second scan clock signal CLK(n-1) is high, the pull-down control node Kn is high, which turns on the eighth transistor T8 and the ninth transistor T9 in the pull-down sustaining module 50, keeping the pull-up control node Qn and the output node Rn at a low level.
[0064] When the second scan clock signal CLK(n-1) is low, the pull-down control node Kn is low, thereby turning off the eighth transistor T8 and the ninth transistor T9 in the pull-down sustaining module 50, and the pull-down sustaining module 50 stops working. Since the second scan clock signal CLK(n-1) is a periodic signal that alternates between high and low levels, it causes the eighth transistor T8 and the ninth transistor T9 in the pull-down sustaining module 50 to be in a periodic alternation between being on and off, thereby slowing down the forward bias speed of the eighth transistor T8 and the ninth transistor T9 and improving their lifespan.
[0065] In another alternative implementation, when the inverting module 40 is connected to the second scan clock signal CLK(n-1) and the preset high-level signal VGH, such as Figure 4 As shown, in Figure 2 Based on this, the inverting module 40 may further include a second capacitor C2. The second capacitor C2 may be connected between the intermediate sustaining node Sn and the pull-down control node Kn.
[0066] It should be noted that the structure of other modules in this embodiment is similar to... Figure 2 The corresponding embodiments are the same; please refer to them for details. Figure 2 The relevant descriptions in the corresponding embodiments will not be repeated here.
[0067] Understandably, due to Figure 2The intermediate sustaining node Sn is in a floating state. After the second scan clock signal CLK(n-1) is connected to the pull-down control node Kn, when the second scan clock signal CLK(n-1) is high, the pull-down control node Kn is also high. At this time, due to the parasitic capacitance of the sixth transistor T6, the high level of the intermediate sustaining node Sn will be coupled to a very high level (e.g., 40 volts (V)) by the second scan clock signal CLK(n-1) and the pull-down control node Kn due to the capacitive coupling effect. This causes the voltage difference Vds between the drain and source of the fifth transistor T5 to be at a very high level, which can easily cause the fifth transistor T5 to break down, thus causing the entire circuit to fail.
[0068] To address this technical problem, this application also provides another GOA driving circuit. For example... Figure 5 As shown, in another alternative implementation, the inverter module 40 can be used only to access the third scan clock signal CLK(n-2). Based on this, the inverter module 40 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
[0069] Specifically, the gate and source of the fourth transistor T4 and the source of the sixth transistor T6 can be used to connect to the third scan clock signal CLK(n-2). The drain of the fourth transistor T4, the gate of the sixth transistor T6 and the source of the fifth transistor T5 can be connected to the intermediate sustain node Sn. The drain of the sixth transistor T6 and the source of the seventh transistor can be connected to the pull-down control node Kn. The gate of the fifth transistor T5 and the gate of the seventh transistor T7 can be connected to the pull-up control node Qn. The drain of the fifth transistor T5 and the drain of the seventh transistor T7 can be connected to the low-level terminal.
[0070] It should be noted that the structure of other modules in this embodiment is similar to... Figure 2 The corresponding embodiments are the same; please refer to them for details. Figure 2 The relevant descriptions in the corresponding embodiments will not be repeated here.
[0071] Since the inverter module 40 in this embodiment is only connected to the third scan clock signal CLK(n-2), and the fourth transistor T4 in the inverter module 40 is a diode, when the third scan clock signal CLK(n-2) changes from high to low, the fourth transistor T4 is turned off. At this time, the intermediate sustaining node Sn is still at a high level, which causes the sixth transistor T6 to turn on. The level of the pull-down control node Kn decreases with the level of the third scan clock signal CLK(n-2). Due to the parasitic capacitance of the sixth transistor T6, the intermediate sustaining node Sn is coupled to a lower level due to the capacitive coupling effect. When the third scan clock signal CLK(n-2) becomes high again, since the intermediate sustaining node Sn has been coupled down, the fourth transistor T4 turns on and charges the intermediate sustaining node Sn, making the intermediate sustaining node Sn high. This causes the sixth transistor T6 to turn on, which in turn makes the pull-down control node Kn high. This process is repeated, and the level of the intermediate maintenance node Sn will change back and forth between a suitable high level (e.g., 25V) and a low level (e.g., 0V), so that the voltage difference Vds between the drain and source of the fifth transistor T5 is within a suitable range (e.g., 33V), reducing the risk of the fifth transistor T5 being damaged.
[0072] Please see Figure 6 This is a schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application. Figure 6 As shown, in another optional implementation, when the inverting module 40 is connected to the first scan clock signal CLK(n) and the preset high-level signal VGH, the inverting module 40 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.
[0073] In this configuration, the gate and source of the fourth transistor T4 are used to connect to the first scan clock signal CLK(n), the source of the sixth transistor T6 can be used to connect to the preset high-level signal VGH, the drain of the fourth transistor T4, the source of the fifth transistor T5 and the gate of the sixth transistor T6 can be connected to the intermediate sustain node Sn, the drain of the sixth transistor T6 and the source of the seventh transistor T7 can be connected to the pull-down control node Kn, the gate of the fifth transistor T5 and the gate of the seventh transistor T7 can be connected to the pull-up control node Qn, and the drain of the fifth transistor T5 and the drain of the seventh transistor T7 can be connected to the low-level terminal.
[0074] It should be noted that the structure of other modules in this embodiment is similar to... Figure 2 The corresponding embodiments are the same; please refer to them for details. Figure 2 The relevant descriptions in the corresponding embodiments will not be repeated here.
[0075] In this embodiment, since the gate and source of the fourth transistor T4 in the inverting module 40 are used to connect to the first scan clock signal CLK(n) corresponding to the GOA driving unit at this stage (i.e., the fourth transistor T4 is a diode connection), and the source of the sixth transistor T6 is used to connect to the preset high-level signal VGH, the voltage difference Vgs between the gate and source of the fourth transistor T4 is less than the transistor's turn-on voltage, thereby turning off the fourth transistor T4 and keeping the level of the intermediate maintenance node Sn in a floating state. Based on this, when the potential of the first scan clock signal CLK(n) fluctuates, the level of the intermediate maintenance node Sn will be coupled and fluctuate due to the parasitic capacitance of the fourth transistor T4. When the intermediate maintenance node Sn fluctuates to a lower level, the voltage difference Vgs between the gate and source of the sixth transistor T6 is less than 0, thereby subjecting the sixth transistor T6 to negative voltage stress, slowing down the forward bias speed of the sixth transistor T6, and extending the service life of the GOA driving unit.
[0076] Please see Figure 7 This is a schematic diagram of the structure of a GOA driving unit provided in another embodiment of this application. Figure 7 As shown, when the inverting module 40 is connected to the first scan clock signal CLK(n) and the preset high-level signal VGH, the GOA driving unit may also include a node control module 70.
[0077] Node control module 70 can be connected to pull-down control node Kn. Node control module 70 can be used to receive the fourth scan clock signal CLK(n+1) and perform pull-down control on pull-down control node Kn according to the fourth scan clock signal CLK(n+1). For example, node control module 70 can be used to pull down pull-down control node Kn to a low level VSS according to the high level of the fourth scan clock signal CLK(n+1). Here, the fourth scan clock signal CLK(n+1) can be the scan clock signal corresponding to the next stage GOA driver unit.
[0078] Based on this, such as Figure 8 As shown, when the inverter module 40 is connected to the third scan clock signal CLK(n-2) and the preset high-level signal VGH, the inverter module 40 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.
[0079] Specifically, the gate of the fourth transistor T4 and the source of the sixth transistor T6 can be used to connect to a preset high-level signal VGH. The source of the fourth transistor T4 can be used to connect to the third scan clock signal CLK(n-2). The drain of the fourth transistor T4, the source of the fifth transistor T5, and the gate of the sixth transistor T6 can be connected to the intermediate sustaining node Sn. The drain of the sixth transistor T6 and the source of the seventh transistor T7 can be connected to the pull-down control node Kn. The gate of the fifth transistor T5 and the gate of the seventh transistor T7 can be connected to the pull-up control node Qn. The drain of the fifth transistor T5 and the drain of the seventh transistor T7 can be connected to a low-level terminal.
[0080] The node control module 70 may include a twelfth transistor T12. The gate of the twelfth transistor T12 can be used to connect to the fourth scan clock signal CLK(n+1), the source of the twelfth transistor T12 can be connected to the pull-down control node Kn, and the drain of the twelfth transistor T12 can be connected to a low-level terminal.
[0081] It should be noted that the structure of other modules in this embodiment is similar to... Figure 2 The corresponding embodiments are the same; please refer to [link / reference] for details. Figure 2 The relevant descriptions in the corresponding embodiments will not be repeated here.
[0082] In this embodiment, since the fourth transistor T4 in the inverting module 40 is in the normally open state, the level of the intermediate node Sn will change with the level of the third scan clock signal CLK(n-2), and the level of the pull-down control node Kn will change with the switching state of the twelfth transistor T12. At this time, the intermediate sustaining node Sn is not in the floating state, the capacitive coupling effect can be ignored, and the level of the intermediate sustaining node Sn will change back and forth between a suitable high level (e.g., 25V) and a low level (e.g., 0V), so that the voltage difference Vds between the drain and source of the fifth transistor T5 is within a suitable range (e.g., 33V), reducing the risk of the fifth transistor T5 being broken down.
[0083] This application also provides a display device, which includes the above-described GOA driving circuit.
[0084] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units is merely an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the GOA driver circuit can be divided into different functional units to complete all or part of the functions described above. Furthermore, the specific names of each functional unit are only for easy differentiation and are not intended to limit the scope of protection of this application.
[0085] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.
[0086] It should be noted that, unless otherwise specified, all technical terms used in the embodiments of this application have the same meaning as commonly understood by those skilled in the art to which this application belongs. The technical terms used in the embodiments of this application are only used to explain specific embodiments of this application and are not intended to limit this application.
[0087] The term "embodiment" as used in the description of embodiments in this application means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0088] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0089] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A GOA driving unit, characterized in that, include: A pull-up control module, connected to a pull-up control node, is used to output a high-level pull-up control signal to the pull-up control node based on a high-level first input signal; A pull-up module, connected to the pull-up control node and the output node, is used to output a gate drive signal from the output node according to the pull-up control signal and the first scan clock signal; A pull-down module, connected to the pull-up control node, is used to pull the pull-up control node down to a low level according to a high-level second input signal; An inverting module, connected to the pull-up control node and the pull-down control node, is used to receive a second scan clock signal and a preset high-level signal, or a third scan clock signal, or the third scan clock signal and the preset high-level signal, or the first scan clock signal and the preset high-level signal, and outputs an inverted signal of the pull-up control signal to the pull-down control node according to the received signal; the level of the inverted signal follows the level of the scan clock signal received by the inverting module. A pull-down sustaining module, connected to the pull-up control node, the pull-down control node, and the output node, is used to maintain the pull-up control node and the output node at a low level according to the high-level inverted signal; A reset module, connected to the pull-up control node and the output node, is used to pull the pull-up control node and the output node down to a low level according to a high-level reset signal.
2. The GOA driving unit according to claim 1, characterized in that, The pull-up control module includes a first transistor; The gate and source of the first transistor are used to receive the first input signal, and the drain of the first transistor is connected to the pull-up control node.
3. The GOA driving unit according to claim 1, characterized in that, The pull-up module includes a second transistor and a first capacitor; The gate of the second transistor and the first terminal of the first capacitor are both connected to the pull-up control node, the source of the second transistor is used to connect to the first scan clock signal, and the drain of the second transistor and the second terminal of the first capacitor are both connected to the output node. The pull-down module includes a third transistor; The gate of the third transistor is used to receive the second input signal, the source of the third transistor is connected to the pull-up control node, and the drain of the third transistor is connected to the low-level terminal.
4. The GOA driving unit according to claim 1, characterized in that, When the inverting module is connected to a second scan clock signal and a preset high-level signal, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The gate and source of the fourth transistor are used to connect to the preset high-level signal. The drain of the fourth transistor, the source of the fifth transistor, and the gate of the sixth transistor are all connected to the intermediate sustaining node. The source of the sixth transistor is used to connect to the second scan clock signal. The gate of the fifth transistor and the gate of the seventh transistor are all connected to the pull-up control node. The drain of the sixth transistor and the source of the seventh transistor are all connected to the pull-down control node. The drain of the fifth transistor and the drain of the seventh transistor are connected to the low-level terminal.
5. The GOA driving unit according to claim 4, characterized in that, The inverting module also includes a second capacitor; the second capacitor is connected between the intermediate sustaining node and the pull-down control node.
6. The GOA driving unit according to claim 1, characterized in that, When the inverting module is connected to the third scan clock signal, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The gate, source, and source of the fourth transistor are used to receive the third scan clock signal. The drain, gate, and source of the fourth transistor are connected to the intermediate sustain node. The drain and source of the sixth transistor are connected to the pull-down control node. The gate and gate of the fifth transistor are connected to the pull-up control node. The drain and drain of the fifth transistor are connected to the low-level terminal.
7. The GOA driving unit according to claim 1, characterized in that, When the inverting module is connected to the first scan clock signal and the preset high-level signal, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The gate and source of the fourth transistor are used to connect to the first scan clock signal, the source of the sixth transistor is used to connect to the preset high-level signal, the drain of the fourth transistor, the source of the fifth transistor, and the gate of the sixth transistor are all connected to the intermediate sustaining node, the drain of the sixth transistor and the source of the seventh transistor are all connected to the pull-down control node, the gate of the fifth transistor and the gate of the seventh transistor are all connected to the pull-up control node, and the drain of the fifth transistor and the drain of the seventh transistor are connected to the low-level terminal.
8. The GOA driving unit according to claim 1, characterized in that, When the inverting module is connected to the third scan clock signal and the preset high-level signal, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The gate of the fourth transistor and the source of the sixth transistor are used to connect to the preset high-level signal. The source of the fourth transistor is used to connect to the third scan clock signal. The drain of the fourth transistor, the source of the fifth transistor, and the gate of the sixth transistor are all connected to the intermediate sustaining node. The drain of the sixth transistor and the source of the seventh transistor are all connected to the pull-down control node. The gate of the fifth transistor and the gate of the seventh transistor are all connected to the pull-up control node. The drain of the fifth transistor and the drain of the seventh transistor are connected to the low-level terminal. The GOA driving unit also includes a node control module; The node control module is connected to the pull-down control node and is used to receive the fourth scan clock signal, and pull the pull-down control node down to a low level according to the high level of the fourth scan clock signal.
9. A GOA driving circuit, characterized in that, The system includes cascaded multi-stage GOA driving units as described in any one of claims 1-8; the first input signal of each stage of the GOA driving unit is the gate driving signal output by the GOA driving unit of the previous k stage, the second input signal of each stage of the GOA driving unit is the gate driving signal output by the GOA driving unit of the next j stage, the first scan clock signal of each stage of the GOA driving unit is the scan clock signal corresponding to the GOA driving unit of this stage, the second scan clock signal of each stage of the GOA driving unit is the scan clock signal corresponding to the GOA driving unit of the previous 1 stage, and the third scan clock signal of each stage of the GOA driving unit is the scan clock signal corresponding to the GOA driving unit of the previous 2 stages; k and j are positive integers.
10. A display device, characterized in that, Includes the GOA driving circuit as described in claim 9.