A power monitoring system

Abstract

The utility model discloses a kind of power monitoring systems for solving the problems of DC-DC circuit in prior art in voltage dynamic regulation and overvoltage protection, including data acquisition module, communication module, alarm module, load control module, central monitoring platform and power management module, wherein the power management module has four output terminals, four output terminals are respectively connected with the data acquisition module, the communication module, the alarm module, the load control module for power supply with four output terminals.The power management module includes four DC-DC circuits, control submodule, four protection circuits.DC-DC circuit converts the voltage of external power supply into the voltage required by each module, and dynamically adjusts the output voltage through the PWM signal output by control submodule, to ensure the stability of system operation.The protection circuit monitors the output voltage of DC-DC circuit in real time, and can quickly cut off the external power supply when overvoltage is detected.

Description

Technical Field

[0001] This utility model relates to the field of power monitoring technology, and in particular to a power monitoring system. Background Technology

[0002] As power systems evolve towards higher reliability, automation, and informatization, power monitoring systems play a crucial role in power production and supply. Through real-time data acquisition, switch status detection, and remote control, power monitoring systems provide a fundamental platform for the efficient operation of power distribution systems. However, existing power monitoring systems still have shortcomings in power management, especially in complex scenarios with multi-module power supply. Achieving efficient and stable voltage distribution and overvoltage protection has become a key technical challenge.

[0003] In the power management module, the DC-DC circuit is the core component, which converts the input voltage into the voltage required by different loads. Although traditional DC-DC circuits can achieve voltage conversion, they have limitations in terms of dynamic voltage regulation and overvoltage protection. Utility Model Content

[0004] This invention addresses the problems of existing DC-DC circuits in terms of dynamic voltage regulation and overvoltage protection by providing a power monitoring system.

[0005] The technical solution adopted in this utility model is:

[0006] A power monitoring system includes a data acquisition module, a communication module, an alarm module, a load control module, a central monitoring platform, and a power management module. The power management module has four output terminals, which are respectively connected to the data acquisition module, the communication module, the alarm module, and the load control module for power supply. The power management module includes:

[0007] Four DC-DC circuits, each connected to an external power supply, are used to convert the voltage of the external power supply into the voltage required by the data acquisition module, the communication module, the alarm module, and the load control module; wherein the external power supply voltage is V. in ;

[0008] A control submodule is connected to each of the DC-DC circuits; the control submodule is used to output a PWM signal to control the voltage output by each of the DC-DC circuits.

[0009] Four protection circuits are provided, each of which has an input terminal that is also an input terminal of the power management module. Each protection circuit is connected to the DC-DC circuit and the control submodule. Each protection circuit is used to detect the voltage output by the DC-DC circuit. When the voltage output by the DC-DC circuit is too high, the external power supply to the DC-DC circuit is cut off.

[0010] Furthermore, each of the DC-DC circuits includes:

[0011] IGBT1, wherein the gate of IGBT1 is connected to the control submodule, and the collector of IGBT1 is connected to the positive terminal of the external power supply;

[0012] IGBT2, wherein the gate of IGBT2 is connected to the control submodule, the collector of IGBT2 is connected to the emitter of IGBT1, and the emitter of IGBT2 is connected to ground;

[0013] Resistor R1, one end of which is connected to the emitter of IGBT1;

[0014] A filter capacitor C, one end of which is connected to the other end of the resistor R1, and the other end of the filter capacitor C is connected to ground;

[0015] A voltage follower VF is connected, with its non-inverting input connected to the other end of resistor R1. The output of VF is the output of the DC-DC circuit and also serves as the load voltage, denoted as V0. out The load includes the data acquisition module, the communication module, the alarm module, and the load control module.

[0016] Furthermore, the control submodule includes:

[0017] Voltage divider resistor R2, one end of which is connected to the output terminal of voltage follower VF;

[0018] Voltage divider resistor R3, one end of which is connected to the other end of voltage divider resistor R2, and the other end of voltage divider resistor R3 is connected to ground;

[0019] The comparator CMP is connected to the connection point between the voltage divider resistors R2 and R3.

[0020] A digital-to-analog converter (DAC) circuit, wherein the output terminal of the DAC circuit is connected to the inverting input terminal of the comparator (CMP);

[0021] A controller is connected to the input terminal of the digital-to-analog converter (DAC).

[0022] Furthermore, each of the protection circuits includes an IGBT3, the gate of which is connected to the controller, the collector of which is connected to ground, and the emitter of which is connected to the negative terminal of an external power supply. The controller is configured with a proportionally scaled maximum load withstand voltage, the value of which is V. out '*(R3 / (R2+R3)', the controller transmits the maximum load-bearing voltage value to the inverting input of the comparator CMP through the digital-to-analog converter (DAC). The voltage across the voltage divider resistor R3 is the proportionally reduced load voltage, and the proportionally reduced load voltage value is V. out *(R3 / (R2+R3)), the load voltage is input to the non-inverting input of the comparator CMP; when V out * (R3 / (R2+R3)) is greater than V out When *(R3 / (R2+R3)), the comparator CMP output terminal outputs a high level and inputs it to the controller. The pin of the controller connected to the gate of the IGBT3 changes from high level to low level, and the IGBT3 changes from the on state to the off state.

[0023] Among them, V out '*(R3 / (R2+R3)) and V out * (R3 / (R2+R3)) must not exceed the voltage that the comparator CMP input terminal can withstand.

[0024] Furthermore, the controller is an FPGA chip. FPGA chips are flexible in development and can output PWM signals with different duty cycles to precisely control the voltage output by the DC-DC circuit.

[0025] Furthermore, it also includes an alarm device connected to the controller; when the comparator CMP outputs a high level and inputs it to the controller, the pin connected to the alarm device on the controller changes from low level to high level, and the alarm device issues an alarm signal.

[0026] Furthermore, the alarm device includes an LED; when the comparator CMP outputs a high level and this level is transmitted to the controller, the pin of the controller connected to the LED changes from a low level to a high level, and the LED is lit.

[0027] Furthermore, the alarm device also includes a storage chip; the storage chip is connected to the FPGA chip, and the storage chip is used to record V. out * (R3 / (R2+R3)) is greater than V out The time when *(R3 / (R2+R3)) occurs.

[0028] Furthermore, the storage chip is a FLASH chip, because data in a FLASH chip is not lost after power is turned off.

[0029] The beneficial effects of this utility model are:

[0030] The power monitoring system disclosed in this utility model achieves efficient management and stable distribution of external power supply through a power management module. The DC-DC circuit converts the voltage of the external power supply into the voltage required by each module and dynamically adjusts the output voltage through the PWM signal output by the control submodule, ensuring the stability of system operation. The protection circuit monitors the output voltage of the DC-DC circuit in real time. When an overvoltage condition is detected, it can quickly cut off the external power supply to avoid damage to the load modules, significantly improving system safety.

[0031] The control submodule precisely divides and compares the output voltage using voltage divider resistors and comparators, ensuring that the comparator input voltage does not exceed its tolerance range. The FPGA chip offers flexible development, allowing the output of PWM signals with different duty cycles to precisely control the voltage output of the DC-DC circuit. The high input impedance and low output impedance characteristics of the voltage follower further guarantee the safety of the signal source and the stability of the output voltage. An alarm device issues an alert via LED when overvoltage occurs and records the fault time via a memory chip for easy subsequent maintenance. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a power monitoring system.

[0034] Figure 2 This is the circuit diagram for the power management module. Detailed Implementation

[0035] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0036] The following disclosure provides many different embodiments or examples for implementing various structures of this invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this invention.

[0037] The embodiments of the utility model will now be described in detail with reference to the accompanying drawings.

[0038] The power monitoring system disclosed in this embodiment includes the following components: a data acquisition module 2, a communication module 3, an alarm module 5, a load control module 4, a central monitoring platform, and a power management module. The power management module has four output terminals, which are respectively connected to the data acquisition module 2, the communication module 3, the alarm module 5, and the load control module 4 for power supply. The power management module includes: four DC-DC circuits 11, a control submodule 12, and four protection circuits 13. In addition, this embodiment also provides an external power supply. (See attached...) Figure 1 As shown.

[0039] Each DC-DC circuit 11 is connected to an external power supply to convert the voltage of the external power supply into the voltage required by the data acquisition module 2, communication module 3, alarm module 5, and load control module 4; wherein, the external power supply voltage is V. in .

[0040] The control submodule 12 is connected to each DC-DC circuit 11; the control submodule 12 is used to output PWM signals to control the voltage output by each DC-DC circuit 11.

[0041] Each protection circuit 13 is connected to the DC-DC circuit 11 and the control submodule 12; each protection circuit 13 is used to detect the voltage output by the DC-DC circuit 11, and when the voltage output by the DC-DC circuit 11 is too high, the external power supply to the DC-DC circuit 11 is cut off.

[0042] Each DC-DC circuit 11 includes IGBT1, IGBT2, resistor R1, and voltage follower VF. The gate of IGBT1 is connected to the control submodule 12, and the collector of IGBT1 is connected to the positive terminal of the external power supply. The gate of IGBT2 is connected to the control submodule 12, the collector of IGBT2 is connected to the emitter of IGBT1, and the emitter of IGBT2 is connected to ground. One end of resistor R1 is connected to the emitter of IGBT1. One end of filter capacitor C is connected to the other end of resistor R1, and the other end of filter capacitor C is connected to ground. The non-inverting input of voltage follower VF is connected to the other end of resistor R1. The output of voltage follower VF is the output of DC-DC circuit 11, and also the load voltage, denoted as V. out The load comprises the data acquisition module 2, the communication module 3, the alarm module 5, and the load control module 4. (See attached diagram.) Figure 2 As shown.

[0043] The control submodule 12 includes voltage divider resistors R2 and R3, a comparator CMP, a digital-to-analog converter (DAC), and a controller. One end of voltage divider resistor R2 is connected to the output of voltage follower VF; one end of voltage divider resistor R3 is connected to the other end of voltage divider resistor R2, and the other end of voltage divider resistor R3 is connected to ground; the non-inverting input of comparator CMP is connected to the connection point between voltage divider resistors R2 and R3; the output of DAC is connected to the inverting input of comparator CMP; and the controller is connected to the input of DAC.

[0044] Each protection circuit 13 includes an IGBT 3, with its gate connected to the controller, its collector connected to ground, and its emitter connected to the negative terminal of an external power supply. The controller is configured with a proportionally scaled maximum load withstand voltage of V. out *(R3 / (R2+R3)), the controller inputs the maximum load voltage value to the inverting input of the comparator CMP via the digital-to-analog converter (DAC). The voltage across the voltage divider resistor R3 is the proportionally scaled load voltage, and the proportionally scaled load voltage value is V. out *(R3 / (R2+R3)), the load voltage is input to the non-inverting input of the comparator CMP; when V out * (R3 / (R2+R3)) is greater than V out When *(R3 / (R2+R3)), the comparator CMP outputs a high level, which is then fed into the controller. The controller pin connected to the gate of IGBT3 changes from high to low, and IGBT3 changes from the on state to the off state; where V out '*(R3 / (R2+R3)) and V out * (R3 / (R2+R3)) must not exceed the voltage that the comparator CMP input can withstand.

[0045] In this embodiment, the controller is an FPGA chip.

[0046] The alarm device is connected to the controller; when the CMP output terminal outputs a high level and inputs it to the controller, the pin connecting the controller and the alarm device changes from low level to high level, and the alarm device issues an alarm signal.

[0047] The alarm device includes an LED; when the CMP output terminal outputs a high level and sends it to the controller, the pin connected to the LED changes from low level to high level, and the LED is lit.

[0048] The alarm device also includes a memory chip; the memory chip is connected to the FPGA chip and is used to record V. out * (R3 / (R2+R3)) is greater than V out The time when *(R3 / (R2+R3)) occurs.

[0049] The storage chip is a FLASH chip because data in a FLASH chip is not lost after power is turned off.

[0050] The following description uses the circuit that outputs to the data acquisition module 2 as an example to illustrate the working principle of the power monitoring system disclosed in this embodiment.

[0051] In this embodiment, the external power supply voltage V in =48V. The voltage V entering data acquisition module 2. out =12V. The PFGA chip outputs a PWM signal with a duty cycle of 0.25 to the gate of IGBT1, and another signal to the gate of IGBT2. When the gate of IGBT1 is high, the gate of IGBT2 is low, and vice versa, controlling IGBT1 and IGBT2 to conduct alternately. The collector of IGBT2 generates a periodic signal (square wave) with a duty cycle of 0.25. After being filtered by resistor R1 and filter capacitor C, a 12V DC voltage is generated across the filter capacitor C. This 12V DC voltage is output at the output of the voltage follower VF and enters the data acquisition module 2.

[0052] The reasons for choosing a voltage follower VF are as follows: The input impedance of the voltage follower VF is very high, which means that it has very little impact on the load of the preceding circuit and hardly draws current from the signal source, thus protecting the signal source; the output impedance of the voltage follower VF is very low, which means that it can provide a stable output voltage and maintain the stability of the output voltage even when the load changes.

[0053] In this embodiment, the comparator CMP can only withstand a voltage of 5V, and requires a voltage of 12V output from the voltage follower VF (V outTo obtain a 3V voltage input to the non-inverting input of comparator CMP, a voltage divider resistor R2 is used (r = 12V). Therefore, the ratio of the voltage divider resistors R2 and R3 is 3:1. When the voltage across the voltage divider resistor R2 is 3V, it means that the voltage follower VF outputs a 12V voltage (V = 12V). out =12V).

[0054] When V out When V = 13V, V out If the voltage is too high, the FPGA chip outputs 3.25V through the digital-to-analog converter (DAC) circuit, which then inputs it to the inverting input of the comparator CMP. When the voltage across the voltage divider resistor R2 exceeds 3.25V, the comparator CMP outputs a high level, which is then fed into the FPGA chip. The FPGA chip outputs a low level to the gate of IGBT3, causing IGBT3 to disconnect and disconnecting the DC-DC circuit 11 from the external power supply. Simultaneously, the FPGA chip outputs a high level to the LED, illuminating it. The FPGA chip sequentially converts V... out The time of the excessive event is stored in the FLASH chip.

[0055] The power monitoring system disclosed in this embodiment achieves efficient management and stable distribution of external power supply through the optimized design of the power management module 1. Each DC-DC circuit 11 in the system can accurately convert the voltage of the external power supply into the voltage required by each module, and dynamically adjust the output voltage through the PWM signal output by the control submodule 12 to ensure the stability of system operation. Specifically, the data acquisition module 2, communication module 3, alarm module 5, and load control module 4 obtain the required voltage (V of data acquisition module 2) through the four output terminals of the power management module 1. out =12V).

[0056] The protection circuit 13 is designed to monitor the output voltage of the DC-DC circuit 11 in real time. When an overvoltage condition is detected, it can quickly cut off the external power supply to prevent damage to the load module, significantly improving the safety and reliability of the system. For example, when the output voltage V of the data acquisition module 2... out When the voltage exceeds the set value (13V), the protection circuit 13 cuts off the power supply through IGBT3 and issues an alarm through the alarm device (LED), while recording the fault time in the memory chip (FLASH chip).

[0057] Furthermore, the control submodule 12 precisely divides and compares the output voltage using voltage divider resistors R2 and R3 and comparator CMP, ensuring that the comparator input voltage does not exceed its tolerance range. The high input impedance and low output impedance characteristics of the voltage follower VF further guarantee the safety of the signal source and the stability of the output voltage. The FPGA chip offers flexible development capabilities, allowing it to output PWM signals with different duty cycles to precisely control the voltage output by the DC-DC circuit.

Claims

1. A power monitoring system, comprising a data acquisition module, a communication module, an alarm module, a load control module, a central monitoring platform, and a power management module, wherein the power management module has four output terminals, which are respectively connected to the data acquisition module, the communication module, the alarm module, and the load control module for power supply, characterized in that, The power management module includes: Four DC-DC circuits, each connected to an external power supply, are used to convert the voltage of the external power supply into the voltage required by the data acquisition module, the communication module, the alarm module, and the load control module; wherein the external power supply voltage is V. in ; A control submodule is connected to each of the DC-DC circuits; the control submodule is used to output a PWM signal to control the voltage output by each of the DC-DC circuits. Four protection circuits are provided, each of which has an input terminal that is also an input terminal of the power management module. Each protection circuit is connected to the DC-DC circuit and the control submodule. Each protection circuit is used to detect the voltage output by the DC-DC circuit. When the voltage output by the DC-DC circuit is too high, the external power supply to the DC-DC circuit is cut off.

2. The power monitoring system according to claim 1, characterized in that, Each of the DC-DC circuits includes: IGBT1, wherein the gate of IGBT1 is connected to the control submodule, and the collector of IGBT1 is connected to the positive terminal of the external power supply; IGBT2, wherein the gate of IGBT2 is connected to the control submodule, the collector of IGBT2 is connected to the emitter of IGBT1, and the emitter of IGBT2 is connected to ground; Resistor R1, one end of which is connected to the emitter of IGBT1; A filter capacitor C, one end of which is connected to the other end of the resistor R1, and the other end of the filter capacitor C is connected to ground; A voltage follower VF is connected, with its non-inverting input connected to the other end of resistor R1. The output of VF is the output of the DC-DC circuit and also serves as the load voltage, denoted as V0. out The load includes the data acquisition module, the communication module, the alarm module, and the load control module.

3. The power monitoring system according to claim 2, characterized in that, The control submodule includes: Voltage divider resistor R2, one end of which is connected to the output terminal of voltage follower VF; Voltage divider resistor R3, one end of which is connected to the other end of voltage divider resistor R2, and the other end of voltage divider resistor R3 is connected to ground; The comparator CMP is connected to the connection point between the voltage divider resistors R2 and R3. A digital-to-analog converter (DAC) circuit, wherein the output terminal of the DAC circuit is connected to the inverting input terminal of the comparator (CMP); A controller is connected to the input terminal of the digital-to-analog converter (DAC).

4. The power monitoring system according to claim 3, characterized in that, Each of the protection circuits includes an IGBT3, the gate of which is connected to the controller, the collector of which is connected to ground, and the emitter of which is connected to the negative terminal of an external power supply. The controller is configured with a proportionally scaled maximum load withstand voltage, the value of which is... The controller transmits the maximum load voltage value to the inverting input of the comparator CMP via the digital-to-analog converter (DAC). The voltage across the voltage divider resistor R3 is the proportionally reduced load voltage, and the proportionally reduced load voltage value is... The load voltage is input to the non-inverting input of the comparator CMP; when Greater than When the comparator CMP outputs a high level, it is transmitted to the controller. The pin of the controller connected to the gate of the IGBT3 changes from high level to low level, and the IGBT3 changes from the on state to the off state. in, and None of them can exceed the voltage that the input terminal of the comparator CMP can withstand.

5. The power monitoring system according to claim 3 or 4, characterized in that, The controller is an FPGA chip.

6. The power monitoring system according to claim 5, characterized in that, It also includes an alarm device, which is connected to the controller; when the comparator CMP outputs a high level and inputs it to the controller, the pin of the controller connected to the alarm device changes from low level to high level, and the alarm device issues an alarm signal.

7. The power monitoring system according to claim 6, characterized in that, The alarm device includes an LED; when the comparator CMP outputs a high level and passes it to the controller, the pin of the controller connected to the LED changes from low level to high level, and the LED is lit.

8. The power monitoring system according to claim 6, characterized in that, The alarm device further includes a storage chip; the storage chip is connected to the FPGA chip and is used to record... Greater than The time when it happened.

9. The power monitoring system according to claim 8, characterized in that, The storage chip is a FLASH chip because data in a FLASH chip is not lost after power is turned off.

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