High electron mobility transistor
By employing a multilayer composite functional layer and isolation region structure in high electron mobility transistors, the electric field distribution is optimized, solving the problems of local breakdown and current collapse in the device, and improving the device's withstand voltage and conduction stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- INNOSCIENCE (SUZHOU) SEMICON CO LTD
- Filing Date
- 2025-05-22
- Publication Date
- 2026-05-29
AI Technical Summary
Existing high electron mobility transistors are prone to local breakdown and current collapse under high drain voltage, which leads to a decrease in the device's withstand voltage and unstable switching speed.
A multi-layer composite functional layer structure is adopted, and an isolation region is set in the uppermost composite functional layer. Through-channels are formed by ion implantation or etching to optimize the electric field distribution and reduce the electric field peak value to avoid breakdown and current collapse.
This improves the voltage withstand capability of high electron mobility transistors, reduces resistance, and enhances the conduction stability and switching speed of the device.
Smart Images
Figure CN224306188U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a high electron mobility transistor. Background Technology
[0002] HEMT (High Electron Mobility Transistor) devices, as typical representatives of third-generation wide bandgap semiconductor materials, have a series of material performance advantages such as large bandgap, strong breakdown electric field, high electron saturation drift velocity and good chemical stability, making them a popular material for developing high-performance power electronic devices.
[0003] To optimize the electric field distribution under high drain voltage, multilayer field plate structures are typically incorporated into the gate and drain regions. By modulating the additional electric field induced by charge, the peak electric field intensity at the gate and drain edges is reduced, thereby improving the device's breakdown voltage. However, when the device is subjected to high drain voltage, the lateral electric field intensity at the drain edge region increases significantly, leading to a sharp rise in the electron temperature within the channel. High-energy electrons accelerate due to thermal motion, significantly increasing the probability of tunneling into the barrier and buffer layers. Electron tunneling causes abnormal accumulation of carrier concentration at the interface between the barrier and buffer layers, accelerating local breakdown of the device. Furthermore, tunneled electrons form trapped states in the dielectric layer, inducing current collapse effects and significantly reducing the device's switching speed and conduction stability. Utility Model Content
[0004] This invention provides a high electron mobility transistor to solve the defects of existing devices that are prone to local breakdown and current collapse effect.
[0005] This invention provides a high electron mobility transistor, comprising: a substrate; a plurality of composite functional layers stacked on the substrate, wherein the plurality of composite functional layers are stacked sequentially, each composite functional layer comprising a stacked channel layer and a barrier layer, the channel layer being disposed adjacent to the substrate; a gate electrode stacked on the composite functional layers; a drain electrode stacked on the composite functional layers; and an isolation region disposed on a composite functional layer other than the bottommost layer, wherein the isolation region is located between the gate electrode and the drain electrode.
[0006] According to the present invention, a high electron mobility transistor is provided in which a composite functional layer stacked with the gate is provided with a through-slot, the extension direction of the through-slot is perpendicular to the line connecting the gate and the drain, and the through-slot forms the isolation region.
[0007] According to the present invention, a high electron mobility transistor is provided in a composite functional layer stacked with the gate, wherein an ion implantation region is provided, and the ion implantation region forms the isolation region.
[0008] According to the present invention, a high electron mobility transistor is provided, wherein the ion implantation region is implanted with F ions or N ions.
[0009] According to the present invention, a high electron mobility transistor is provided, wherein the number of isolation regions is multiple.
[0010] According to the present invention, in a high electron mobility transistor, the extension direction of the isolation region is consistent with the extension direction of the drain electrode, and extends through the composite functional layer in the extension direction.
[0011] According to the present invention, a high electron mobility transistor comprises a plurality of composite functional layers including: a first composite functional layer stacked with the substrate; a second composite functional layer stacked with the first composite functional layer; the gate and the drain stacked on the second composite functional layer; and the isolation region disposed on the second composite functional layer.
[0012] According to the present invention, in a high electron mobility transistor, the channel layer in each of the composite functional layers is a GaN channel layer.
[0013] According to the high electron mobility transistor provided by this utility model, the barrier layer in the first composite functional layer is an AlGaN barrier layer.
[0014] A high electron mobility transistor according to the present invention further includes: a nucleation layer stacked with the substrate; a buffer layer stacked with the nucleation layer; and a high-resistivity layer disposed between the buffer layer and the composite functional layer.
[0015] The high electron mobility transistor provided by this invention increases the channel electron mobility and reduces the resistance of the high electron mobility transistor by stacking multiple composite functional layers; by setting an isolation region in the uppermost composite functional layer, the electric field distribution of the drift region is optimized, the withstand voltage capability of the high electron mobility transistor is improved, local breakdown of the high electron mobility transistor is avoided, and the possibility of current collapse effect in the high electron mobility transistor is reduced. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the high electron mobility transistor provided by this utility model.
[0018] Figure 2 This is a top view of the high electron mobility transistor provided by this utility model.
[0019] Figure label:
[0020] 10. Substrate; 21. First channel layer; 22. First barrier layer; 31. Second channel layer; 32. Second barrier layer; 33. Isolation region; 40. Gate; 50. Drain; 60. Source. Detailed Implementation
[0021] The embodiments of this utility model will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of this utility model.
[0022] In the description of the embodiments of this utility model, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this utility model. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0023] In the description of the embodiments of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this utility model based on the specific circumstances.
[0024] In this embodiment of the utility model, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0025] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0026] The following is combined with Figure 1 and Figure 2 This invention describes a high electron mobility transistor.
[0027] like Figure 1 As shown, in an embodiment of this invention, the high electron mobility transistor includes: a substrate 10, multiple composite functional layers, a gate 40, and a drain 50. The multiple composite functional layers are stacked on the substrate 10, and are stacked sequentially. The gate 40 and drain 50 are both stacked on top of the composite functional layers. An isolation region 33 is disposed on a composite functional layer other than the bottommost layer, and is located between the gate 40 and the drain 50.
[0028] Specifically, each composite functional layer includes a stacked channel layer and a barrier layer, wherein the channel layer is disposed adjacent to the substrate 10, and the barrier layer is disposed away from the substrate 10, so as to... Figure 1 As shown in the example, the barrier layer is disposed above the channel layer. Multiple composite functional layers are sequentially stacked on the substrate 10, with the composite functional layer immediately adjacent to the substrate 10 being the bottommost layer, named the first composite functional layer. The isolation region 30 can then be disposed on any composite functional layer other than the first composite functional layer. Figure 1 In the embodiment shown, the isolation region 30 is disposed on the composite functional layer stacked with the gate 40. That is, the isolation region 33 is located in the channel layer and barrier layer of the composite functional layer. The isolation region 33 can block channel electrons or form a floating field plate structure. The floating field plate structure can form an additional electric field on the surface of the high electron mobility transistor. After the additional electric field is superimposed with the original electric field of the main structure, the electric field peak can be significantly reduced, thereby avoiding local breakdown of the device.
[0029] In this embodiment, by stacking multiple composite functional layers, the channel electron mobility can be further increased, thereby reducing the resistance of the high electron mobility transistor.
[0030] Optionally, the number of isolation regions 33 can be one or more. When there are multiple isolation regions 33, the peak electric field can be significantly reduced, effectively preventing local breakdown of the device.
[0031] Optionally, the isolation region 33 can be an ion implantation region to block the flow of electrons in the channel; the isolation region 33 can also be a through-slot to form a floating field plate structure to optimize the electric field distribution in the drift region.
[0032] Optionally, the substrate 10 can be a silicon substrate, a sapphire substrate, a GaN substrate, or a silicon carbide substrate.
[0033] The high electron mobility transistor provided in this embodiment increases the channel electron mobility and reduces the resistance of the high electron mobility transistor by stacking multiple composite functional layers; by setting an isolation region in the uppermost composite functional layer, the electric field distribution of the drift region is optimized, the withstand voltage capability of the high electron mobility transistor is improved, local breakdown of the high electron mobility transistor is avoided, and the possibility of current collapse effect in the high electron mobility transistor is reduced.
[0034] Further, in an embodiment of this utility model, there are two composite functional layers. For ease of description, the two composite functional layers are named the first composite functional layer and the second composite functional layer. The first composite functional layer includes a first channel layer 21 and a first barrier layer 22. The first channel layer 21 is stacked with the substrate 10, and the first barrier layer 22 is stacked with the first channel layer 21. The second composite functional layer includes a second channel layer 31 and a second barrier layer 32. The second channel layer 31 is stacked with the first barrier layer 22, and the second barrier layer 32 is stacked with the second channel layer 31. A gate 40 and a drain 50 are disposed on the second barrier layer 32. The second barrier layer 32 and the second channel layer 31 are provided with a plurality of isolation regions 33.
[0035] Optionally, in one embodiment of the present invention, the second barrier layer 32 is provided with a through-slot extending to the second channel layer 31, and the depth of the through-slot is the same as the thickness of the second barrier layer 32 and the second channel layer 31. The length direction of the through-slot is perpendicular to the line connecting the gate 40 and the drain 50, and the through-slot forms an isolation region 33.
[0036] Specifically, in this embodiment, after the second channel layer 31 and the second barrier layer 32 are formed, multiple through-slots can be etched in the second barrier layer 32 and the second channel layer 31 through an etching process to form an intermittent floating field plate structure. For example... Figure 2 As shown, the extension direction of the isolation region 30 is consistent with the extension direction of the drain 50, and it extends through the end face of the second barrier layer 32 and the end face of the second channel layer 31 in the extension direction.
[0037] Optionally, in another embodiment of the present invention, the second barrier layer 32 and the second channel layer 31 are provided with a plurality of ion implantation regions, which form an isolation region 33.
[0038] Specifically, in this embodiment, after the second channel layer 31 and the second barrier layer 32 are formed, ions can be injected into the second barrier layer 32 and the second channel layer 31. The location of the ions forms an ion implantation region, which can block the flow of channel electrons.
[0039] Alternatively, F ions or N ions may be implanted into the ion implantation region.
[0040] In embodiments of this invention, the first channel layer 21 and the second channel layer 31 can be GaN channel layers. The first barrier layer 22 can be an AlGaN barrier layer.
[0041] In embodiments of this invention, the high electron mobility transistor further includes a nucleation layer, a buffer layer, and a high-resistivity layer. The nucleation layer is stacked with the substrate 10, the buffer layer is stacked with the nucleation layer, the high-resistivity layer is stacked with the buffer layer, and the first channel layer 21 is stacked with the high-resistivity layer.
[0042] In embodiments of this invention, a nucleation layer, a buffer layer, a high-resistivity layer, a first channel layer 21, a first barrier layer 22, a second channel layer 31, and a second barrier layer 32 are grown on the substrate 10 in a single step using metal-organic chemical vapor deposition or molecular beam epitaxy. Because the second channel layer 31 and the second barrier layer 32 are grown using metal-organic chemical vapor deposition or molecular beam epitaxy, crystal quality can be improved, drift region traps can be reduced, and the dynamic characteristics of high electron mobility transistors can be enhanced.
[0043] The high electron mobility transistor also includes a source 60, which is stacked with a second barrier layer 32, and the distance between the source 60 and the gate 40 is smaller than the distance between the gate 40 and the drain 50.
[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.
Claims
1. A high electron mobility transistor, characterized in that, include: Substrate; Multiple composite functional layers are stacked with the substrate, and the multiple composite functional layers are stacked sequentially. Each composite functional layer includes a stacked channel layer and a barrier layer, and the channel layer is disposed adjacent to the substrate. The gate is stacked with the composite functional layer; The drain electrode is stacked with the composite functional layer; An isolation region is disposed on a composite functional layer other than the bottom layer, and the isolation region is located between the gate and the drain.
2. The high electron mobility transistor according to claim 1, characterized in that, The composite functional layer stacked with the gate is provided with a through-slot, the extension direction of the through-slot is perpendicular to the line connecting the gate and the drain, and the through-slot forms the isolation region.
3. The high electron mobility transistor according to claim 1, characterized in that, The composite functional layer stacked with the gate has an ion implantation region, which forms the isolation region.
4. The high electron mobility transistor according to claim 3, characterized in that, The ion implantation region is filled with F ions or N ions.
5. The high electron mobility transistor according to claim 1, characterized in that, There are multiple isolation zones.
6. The high electron mobility transistor according to claim 1, characterized in that, The isolation region extends in the same direction as the drain electrode and penetrates the composite functional layer in that direction.
7. The high electron mobility transistor according to claim 1, characterized in that, The plurality of the composite functional layers include: A first composite functional layer is stacked with the substrate; A second composite functional layer is stacked on top of the first composite functional layer, the gate and the drain are stacked on the second composite functional layer, and the isolation region is disposed on the second composite functional layer.
8. The high electron mobility transistor according to claim 7, characterized in that, The channel layer in each of the aforementioned composite functional layers is a GaN channel layer.
9. The high electron mobility transistor according to claim 7, characterized in that, The barrier layer in the first composite functional layer is an AlGaN barrier layer.
10. The high electron mobility transistor according to claim 1, characterized in that, Also includes: A nucleation layer is stacked with the substrate; A buffer layer is stacked on top of the nucleation layer; A high-resistivity layer is disposed between the buffer layer and the composite functional layer.