Semiconductor device with air gap

Abstract

Embodiments of the present disclosure provide a semiconductor device with air gaps, the semiconductor device including a pair of channel regions in a substrate and a source / drain (S / D) region formed between the channel regions, a metal gate on each of the channel regions, and an interlayer dielectric layer (ILD) over the metal gate. An S / D metal contact is formed on the S / D region and extends between the pair of metal gates. The S / D metal contact is spaced apart from the metal gate and the ILD by an air gap structure. The air gap structure includes a sealed portion extending from a top surface of the first ILD to a bottom surface level and an unsealed portion extending from the bottom surface of the ILD to a top surface level of the S / D region.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device with an air gap. Background Technology

[0002] Integrated circuits (ICs) typically comprise multiple semiconductor devices, such as field-effect transistors (FETs) and metal interconnect layers formed on a semiconductor substrate. Interconnect layers, designed to connect semiconductor devices to power supplies, input / output signals, and interconnect with each other, can include signal lines and power rails. The semiconductor industry has experienced sustained rapid growth due to the ever-improving performance of various electronic components, including metal contacts and interconnect layers. In most cases, low capacitance and low resistance are desirable in interconnect layers. However, due to current technologies used to form interconnect features, interconnect features may have higher capacitance and / or resistance than desired. Therefore, these issues need to be addressed. Utility Model Content

[0003] According to one embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a channel region in a substrate and a source / drain region formed adjacent to the channel region, a metal gate on the channel region, and a first interlayer dielectric layer above the metal gate. Source / drain metal contacts are formed on the source / drain regions, which are adjacent to the metal gate and spaced apart from the metal gate and the first interlayer dielectric layer by an air gap structure. The air gap structure includes a sealed portion extending from the top surface of the first interlayer dielectric layer to a bottom surface level and an unsealed portion extending from the bottom surface level of the first interlayer dielectric layer to the top surface level of the source / drain regions.

[0004] According to another embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a channel region in a substrate and a source / drain region formed adjacent to the channel region, a metal gate on the channel region, and a first interlayer dielectric layer above the metal gate. Source / drain metal contacts are formed on the source / drain region, which is adjacent to the metal gate and spaced from the metal gate and the first interlayer dielectric layer by an air gap structure. The air gap structure includes a sealed portion extending from the top surface of the first interlayer dielectric layer to a bottom surface level and an unsealed portion extending from the bottom surface level of the first interlayer dielectric layer to the top surface level of the source / drain region. The sealed portion includes a first ion implantation layer and a second ion implantation layer.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a channel region in a substrate and a source / drain region formed adjacent to the channel region, a metal gate on the channel region, and a first interlayer dielectric layer above the metal gate. Source / drain metal contacts are formed on the source / drain regions, which are adjacent to the metal gate and spaced apart from the metal gate and the interlayer dielectric layer by an air gap structure. The air gap structure includes a sealed portion extending from the top surface of the first interlayer dielectric layer to a bottom surface level and an unsealed portion extending from the bottom surface level of the first interlayer dielectric layer to the top surface level of the source / drain regions. The sealed portion includes a dopant. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1 to 19B The illustrations schematically depict various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0008] Figure 20 This is a flowchart of various operations according to the method disclosed herein.

[0009] [Symbol Explanation]

[0010] 10:Substrate

[0011] 12: Semiconductor layer

[0012] 14: Semiconductor layer

[0013] 16: Padding layer

[0014] 18: Hard Mask

[0015] 20: Fin structure

[0016] 22: Isolation layer

[0017] 24: Sacrificial gate dielectric layer

[0018] 26: Sacrificial gate electrode layer

[0019] 28: Padding layer

[0020] 30: Masking layer

[0021] 32: Sacrificial gate structure

[0022] 34: Sidewall spacers

[0023] 35: Internal spacers

[0024] 36: Source / Drain (S / D) Characteristics

[0025] 38:CESL

[0026] 39: Silicon spacers

[0027] 40:ILD

[0028] 42: Gate dielectric layer

[0029] 44: Gate electrode layer / metal gate

[0030] 48:ILD

[0031] 50:ILD

[0032] 50': Implantation area / sealing portion

[0033] 50”: Sealed section

[0034] 51: Contact hole

[0035] 52: Silicide layer

[0036] 53: Ions

[0037] 54: Lining layer

[0038] 55: Conductive materials

[0039] 56: Source / Drain (S / D) metal contacts

[0040] 58: Air gap

[0041] 60:ILD

[0042] 62: Ions

[0043] 64: Ions

[0044] 66: Dielectric Layer / ILD

[0045] 72:VG

[0046] 74:VD

[0047] 100: Semiconductor Device Structure

[0048] 102~122: Operation

[0049] T1: Thickness

[0050] a, b: height

[0051] c, d: Thickness

[0052] θ, θ1, θ2: Inclination angles Detailed Implementation

[0053] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0054] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “top,” “upper,” and similar terms are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0055] In current technology, interconnect structures, such as vias and conductive lines, are formed above electronic components to provide connections between electronic components (such as transistors, capacitors, or the like) formed on a substrate, and to provide connections to external devices. To reduce parasitic capacitance C... eff Interconnect structures can be formed in low-k dielectric materials. However, even with low-k dielectrics, parasitic capacitances can still exceed acceptable limits as device dimensions continue to shrink in advanced technology nodes. Therefore, air gaps formed between conductive structures have been developed to further reduce capacitance.

[0056] Although the embodiments disclosed herein are described in the context of nanosheet channel FETs, some implementations of these embodiments can be used in other processes and / or other devices, such as planar FETs, FinFETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. Those skilled in the art will readily understand that other modifications can be made within the scope of this disclosure.

[0057] Figures 1 to 19B The illustrations schematically depict various stages of manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. Figure 20This is a flowchart of a method for manufacturing a semiconductor device structure according to embodiments of the present disclosure. Additional embodiments of the method may provide additional operations before, during, and after the operation / process of the method, and some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0058] like Figure 1 As shown, a fin structure 20 is formed over a semiconductor substrate 10. The substrate 10 is provided for forming semiconductor devices thereon. The substrate 10 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate 10 may include various doping configurations depending on the circuit design. For example, different doping profiles, such as n-wells and p-wells, may be formed in regions of the substrate 10 designed for different device types (e.g., nFETs and pFETs). In some embodiments, the substrate 10 may be a silicon-on-insulator (SOI) substrate including an insulator structure (not shown) for enhancement.

[0059] To form the fin structure 20, one or more pairs of first semiconductor layers 12 and second semiconductor layers 14 are formed over the substrate 10. The first and second semiconductor layers 12, 14 can be formed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the second semiconductor layer 14 comprises the same material as the substrate 10. In some embodiments, the first and second semiconductor layers 12 and 14 comprise materials different from the substrate 10. In some embodiments, the first and second semiconductor layers 12 and 14 are made of materials with different lattice constants. The first semiconductor layer 12 in the channel region can eventually be removed and used to define the vertical distance between adjacent channel regions for subsequent formation of multi-gate devices. In some embodiments, the first semiconductor layer 12 comprises an epitaxially grown silicon-germanium (SiGe) layer, and the second semiconductor layer 14 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the first and second semiconductor layers 12 and 14 may comprise other materials, such as Ge; compound semiconductors, such as SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof.

[0060] The fin structure 20 is formed by patterning a pad layer 16 and a hard mask 18 on a pair of first and second semiconductor layers 12 and 14, and then etching through a portion of the pair of first and second semiconductor layers 12 and 14 and the substrate 10.

[0061] exist Figure 2 In the process, the sacrificial gate structure 32 is formed above the fin structure 20, and the sidewall spacers 34 are formed on the side of the sacrificial gate structure 32.

[0062] After the fin structure 20 is formed, an isolation layer 22 is formed in the grooves between the fin structures 20, such as Figure 3 As shown. An isolation layer 22 is formed over a substrate 10, followed by etching back to expose paired first and second semiconductor layers 12, 14. In some embodiments, the isolation layer 22 may include silicon oxide, silicon nitride, silicon oxynitride, fluorosilicone glass (FSG), a low-k dielectric, or a combination thereof.

[0063] The sacrificial gate structure 32 may include a sacrificial gate dielectric layer 24, a sacrificial gate electrode layer 26, a pad layer 28, and a mask layer 30. The sacrificial gate dielectric layer 24 may include one or more layers of dielectric material, such as SiO2, SiN, high-k dielectric material, and / or other suitable dielectric material. The sacrificial gate electrode layer 26 may include silicon, such as polycrystalline silicon or amorphous silicon. The pad layer 28 may include silicon nitride. The mask layer 30 may include silicon oxide. Next, a patterning operation is performed on the mask layer 30, the pad layer 28, the sacrificial gate electrode layer 26, and the sacrificial gate dielectric layer 24 to form the sacrificial gate structure 32.

[0064] Sidewall spacers 34 are formed on the sidewalls of each sacrificial gate structure 32. The sidewall spacers 34 may be formed of a dielectric material such as SiO, SiN, SiC, SiCN, SiOC, SiON, SiOCN, or combinations thereof. In some embodiments, the insulating material of the sidewall spacers 34 is a silicon nitride-based material such as SiN, SiON, SiOCN, or SiCN, or combinations thereof. In some embodiments, the thickness T1 of the sidewall spacers 34 is in the range of about 0.5 nm to about 10 nm.

[0065] exist Figure 3 In this process, source / drain features 36 are formed on opposite sides of the sacrificial gate structure 32. The formation of source / drain features 36 may include etching back the portion of the fin structure 20 exposed to the outside of the sacrificial gate structure 32, etching back the first semiconductor layer 12 from below the sidewall spacers 34 to form an internal spacer cavity, and forming internal spacers 35 (e.g., ...) within the internal spacer cavity. Figure 5 (as shown), and source / drain features 36 epitaxially grown from the exposed surface of substrate 10 and the second semiconductor layer 14.

[0066] The internal spacers 35 may be formed of dielectric materials such as SiO, SiN, SiC, SiCN, SiOC, SiON, SiOCN, or combinations thereof. In some embodiments, the internal spacers 35 may include one of silicon nitride (SiN) and silicon oxide (SiO2), SiONC, or combinations thereof.

[0067] Depending on the device type, the source / drain feature 36 may include one or more semiconductor materials. The source / drain feature 36 may be an epitaxially grown material with a thickness ranging from about 0.5 nm to about 30 nm.

[0068] For an n-type device, the source / drain feature 36 may include one or more layers of Si, SiP, SiC, SiCP, or III-V group materials (InP, GaAs, AlAs, InAs, InAlAs, and InGaAs). In some embodiments, the source / drain feature 36 may be doped with an n-type dopant, such as phosphorus (P) or arsenic (As) for n-type devices.

[0069] For a p-type device, the source / drain feature 36 may include one or more layers of Si, SiGe, SiGeB, Ge, or group III-V materials (InSb, GaSb, InGaSb). In some embodiments, the source / drain feature 36 may be doped with a p-type dopant, such as boron (B).

[0070] exist Figure 4 In this process, a contact etch stop layer (CESL) 38 and an interlayer dielectric layer (ILD) 40 are formed above the exposed surface. In an example, the CESL 38 is formed on the source / drain features 36, the sidewall spacers 34, and the isolation layer 22. The CESL 38 may include Si3N4, SiON, SiCN, or any other suitable material and may be formed by CVD, PVD, or ALD. In some embodiments, the CESL 38 may be formed of a material different from that of the sidewall spacers 34, such that the sidewall spacers 34 may be selectively etched back in a subsequent process to form a SAC layer.

[0071] An interlayer dielectric layer (ILD) 40 is formed over a contact etch stop layer (CESL) 38. Materials used for ILD 40 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for ILD 40. ILD 40 protects the source / drain features 36 during the removal of the sacrificial gate structure 32. A planarization operation such as CMP is performed to expose the sacrificial gate electrode layer 26 for subsequent removal of the sacrificial gate structure 32.

[0072] Figures 5 to 19B It is along each stage of the method for manufacturing the semiconductor device structure 100. Figure 4 A cross-sectional view of the AA line device.

[0073] Perform a gate replacement step to form gate dielectric layer 42 and gate electrode layer 44, such as Figure 5 As shown. The gate replacement step may include removing the sacrificial gate electrode layer 26 and the sacrificial gate dielectric layer 24 to expose the fin structure 20 beneath the sacrificial gate structure 32. Subsequently, the first semiconductor layer 12 is removed to form a nanosheet of the second semiconductor layer 14.

[0074] Next, a gate dielectric layer 42 is deposited on the exposed surfaces of each nanosheet of the second semiconductor layer 14, the exposed surfaces of the internal spacers 35, and the exposed surfaces of the sidewall spacers 34. The gate dielectric layer 42 may comprise one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 42 has a dielectric constant of about 7.

[0075] Next, a gate electrode layer 44 is formed above the gate dielectric layer 42. The gate electrode layer 44 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. After forming the gate electrode layer 44, a planarization process, such as CMP, is performed to remove excess deposits of the gate electrode material and expose the top surface of the ILD 40.

[0076] like Figure 5As shown, one or more second semiconductor layers 14 connect source / drain features 36 on opposite sides of one or more second semiconductor layers 14 to form a multichannel transistor. The one or more second semiconductor layers 14 serve as channel regions between the source / drain features 36 of the multichannel transistor. The connection between the source / drain features 36 can be controlled by a voltage applied to the gate electrode layer 44. Alternatively, the channel region may be a single-channel transistor having a single-channel finned channel region or a planar channel region.

[0077] exist Figure 6 In this process, a chemical mechanical polishing (CMP) process is performed to remove portions of the gate dielectric layer 42, the gate electrode layer 44, the sidewall spacers 34, the ILD 40, and the CESL 38.

[0078] exist Figure 7 In this configuration, an interlayer dielectric layer (ILD) 48 is formed over the gate structure (the remaining sidewall spacers 34, the gate dielectric layer 42, and the gate electrode layer 44) and the remaining CESL 38 and ILD 40. ILD 48 can be formed using suitable deposition processes such as CVD, PVD, or ALD. ILD 48 can be made from materials similar to CESL 38, including SiN or any other suitable material.

[0079] Another ILD 50 is formed on ILD 48. ILD 50 may be any dielectric layer that can be used as an etch stop layer during subsequent trench and via patterning for metal contacts. In some embodiments, ILD 50 may be a dielectric layer including, but not limited to, tetraethyl orthosilicate (TEOS) oxide, silicon-free glass, or doped silicon oxide such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), SiN, and / or other suitable dielectric materials. ILD 50 may be formed by FCVD, PECVD, or other suitable methods. ILD 50 may have a thickness ranging from about 0.5 nm to about 30 nm.

[0080] exist Figure 8A In the middle, contact holes 51 are formed through ILDs 40, 48, and 50, and then filled with conductive material to form source / drain metal contacts 56 (see...). Figure 12Suitable optical lithography and etching techniques are used to form contact holes 51 through each layer to expose the top surface of the source / drain features 36. In some embodiments, contact holes 51 may be formed over all source / drain features 36 to form source / drain metal contacts 56 thereon, thereby achieving structural balance. In other embodiments, contact holes 51 are formed over selected source / drain features 36 to connect from the top side to a power supply or signal line. Figure 8A In the illustrated embodiment, the remaining CESL 38 may have a thinner upper portion and a thicker lower portion. In some embodiments, the top of one or more of the CESL 38 in the contact holes 51 may be removed to expose the top portion of the sidewall spacer 34, such as Figure 8B As shown. Therefore, the top portion of the subsequently formed silicon spacer 39 can directly contact the apex corner of the sidewall spacer 34 (see...). Figure 9B ).

[0081] After forming the contact hole 51, as Figure 9A As shown, silicon spacers 39 are conformally formed on the sidewalls of contact hole 51. Besides Si, other materials such as germanium (Ge), silicon-germanium (SiGe), or other suitable materials with higher etch selectivity than the surrounding materials (including ILD layers 48 and 50) can be used to form the spacers. Silicon spacers 39 can be formed by one or more methods, such as PECVD, ALD, and / or other suitable deposition processes. Silicon spacers 39 can have a width of about 1 nm to about 3 nm, such as about 1 nm to about 5 nm. The depth of silicon spacers 39 can range from about 1 nm to about 60 nm, depending on the depth of contact hole 51.

[0082] In some embodiments, the silicon spacer 39 deposited on the sidewall of the contact hole 51 may have a thicker upper portion and a thinner lower portion. Or more specifically, the thickness of the silicon spacer 39 may gradually decrease toward the bottom of the contact hole 51. As a result, the air gap formed by subsequently removing the silicon spacer 39 may have a gradually decreasing thickness.

[0083] Next, a liner layer 54 is formed on the surface of the silicon spacer 39, such as Figure 10 As shown. The liner layer 54 may include carbon-doped SiN, high-density SiN, and / or other suitable materials with low etch selectivity in subsequent etch processes for removing silicon spacers 39. The liner layer 54 may be formed by one or more methods, such as PECVD, ALD, and / or other suitable deposition processes.

[0084] The silicide layer 52 may also be selectively formed above the top surface of the source / drain feature 36 exposed by the contact hole 51, such as... Figure 10As shown. The silicide layer 52 electrically couples the source / drain feature 36 to an interconnect structure, for example, an S / D metal contact subsequently formed in the contact via 51. The silicide layer 52 can be formed by depositing a metal source layer to cover the exposed surface including the epitaxial source / drain feature 36 and performing a rapid thermal annealing process. In some embodiments, the metal source layer includes a metal layer selected from, but not limited to, Ti, Co, Ni, NiCo, Pt, Ni(Pt), Ir, Pt(Ir), Er, Yb, Pd, Rh, Nb, or TiSiN. After forming the metal source layer, a rapid thermal annealing process is performed, for example, rapid annealing at a temperature between about 700°C and about 900°C. During the rapid annealing process, a portion of the metal source above the source / drain feature 36 reacts with the silicon in the source / drain feature 36 to form the silicide layer 52. The unreacted portion of the metal source layer is then removed. In some embodiments, the silicide layer 52 has a thickness in the range of about 0.5 nm to 10 nm.

[0085] Conductive material to be formed 55 (see Figure 11 To fill the contact hole 51 and form the source / drain (S / D) metal contact 56 (see...) Figure 12 However, during the process of growing the S / D metal contact 56, the conductive material 55 can grow rapidly on the exposed portion of the silicon spacer 39 at the top of the contact hole 51. The rapidly growing conductive material 55 may coalesce at the top of the contact hole 51 before the lower portion of the contact hole 51 is properly filled with the conductive material 55. This results in voids within the S / D metal contact 56 and significant metal loss that severely degrades device performance. To address this issue, at least the top portion of the silicon spacer 39 can be treated to reduce the growth rate of the conductive material 55 thereon.

[0086] According to some embodiments, an ion implantation process may be performed to treat the silicon spacer 39 before the conductive material 55 is formed. For example... Figure 9A and Figure 9BAs shown, ions 53 are implanted into at least the upper portion of the silicon spacer 39 at an angle θ. Implantation conditions can be controlled to adjust the depth of the silicon spacer 39 to be processed. For example, the processing depth can be in the range of about 1 nm to about 30 nm. When nitrogen is used to perform the ion implantation process, at least the upper portion of the silicon spacer 39 having a depth of about 1 nm to about 30 nm undergoes a nitriding process and is transformed into a nitrogen-containing barrier layer to reduce the growth rate of the conductive material 55 thereon. The reduced growth rate of the conductive material 55 on the upper portion of the silicon spacer 39 prevents early coalescence of the conductive material 55 at the top portion of the contact hole 51. Therefore, the lower portion of the contact hole 51 can be adequately filled with conductive material 55 without significant metal loss. In addition to nitrogen, ion species such as Ge, Xe, Ar, Si, P, B, or O can also be used in the ion implantation process. According to some embodiments, the ion implantation process can be performed at temperatures ranging from approximately -100°C to approximately 500°C with implantation energies from approximately 1 keV to approximately 50 keV and an implantation density of approximately 1 E14 atoms / cm². 2 Approximately 1E19 atoms / cm 2 The nitrogen dosage and tilt angle of approximately 0° to approximately 90° are used. Under these conditions, the nitrogen concentration introduced into the upper portion can be approximately 1E19 atoms / cm³. 3 Approximately 1E23 atoms / cm 3 Within this range, the nitrogen concentration that can be introduced into the lower portion of the silicon spacer 39 is controlled to be below approximately 1E18 atoms / cm³. 3 .

[0087] Following the ion implantation process, S / D metal contacts 56 are formed to fill individual contact holes 51. For example... Figure 11 As shown, the S / D metal contact 56 can be formed by depositing conductive material 55 into the contact hole 51 and above the top surface of the ILD 50. Suitable deposition processes, such as CVD, PVD, electroplating, ALD, or other suitable techniques, can be used to form the conductive layer material. The conductive material may include, but is not limited to, W, Co, Ru, Ti, Ni, Cu, Au, Ag, Pt, Pd, Ir, Os, Rh, Al, Mo, or the like.

[0088] Subsequently, a planarization process, such as a CMP process, is performed on the conductive material 55 until the ILD 50 is exposed. According to... Figure 12 In the embodiment shown, after the CMP process, the S / D metal contact 56 is formed with a top surface flush with the top surface of the ILD 50.

[0089] exist Figure 13AIn this process, silicon spacers 39 are removed to form air gaps 58 between each pair of adjacent metal gates 44 and S / D metal contacts. Silicon spacers 39 can be removed by an etching process. As previously described, silicon spacers 39 are formed of a material with a different etch selectivity than the surrounding structure (including the ILD 50 and liner layer 54). For example, silicon spacers 39 made of Si or other materials such as Ge, SiGe can be removed by an etching process at a removal rate at least 10 times faster than removing materials from the liner layer 54 made of high-density SiN and the ILD 50 made of SiO2. Selective etching processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, dry etching processes can be performed using oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases, and / or plasma, and / or combinations thereof. Plasma etching processes can also be performed at flow rates from about 500 standard cubic centimeters per minute (sccm) to about 2000 sccm. In some other embodiments, wet etching processes can be performed using diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; solutions containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. Wet etching processes can be performed in any suitable manner, such as by immersing the semiconductor device structure 100 in a wet etchant for a period of time (e.g., less than 1 hour).

[0090] Because the silicon spacer 39 has a width of about 1 nm to about 3 nm, or 1 nm to about 5 nm, along the x-direction, the air gap 58 created by removing the silicon spacer 39 has a thickness of about 1 nm to about 3 nm or about 1 nm to about 5 nm. In some embodiments, when used to form such Figure 13B After the etching process of the air gap 58 shown, a portion of the silicon spacer 39 may be retained on the bottom portion of the sidewall spacer 34.

[0091] according to Figure 8B and Figure 9B In the illustrated embodiment, because the top of some of the CESL 38 in the contact holes 51 can be etched to expose the apex of the sidewall spacer 34, the top portion of the air gap 58 can be formed directly adjacent to the top portion of the sidewall spacer 34, such as... Figure 13B As shown.

[0092] After forming the air gap 58, an ILD 60 is formed to cover the ILD 50, the air gap 58, and the S / D metal contact 56, as shown. Figure 14 As shown. ILD 60 can be formed by a suitable deposition process, such as CVD, PVD, or ALD. ILD 60 may be a dielectric layer, including but not limited to tetraethyl orthosilicate (TEOS) oxide, silicon-free glass, or doped silicon oxide such as borosilicate glass (BPSG), fused silicon glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), SiN, and / or other suitable dielectric materials. Because the air gap 58 is formed with a very small width, there is no risk of ILD 60 penetrating deep into the air gap 58.

[0093] As described later, contact structures can be formed to provide electrical connection between the metal gate 44 and the S / D feature 36. For example, a via or contact plug (VG) can be formed to extend through the ILD 50 to connect to the metal gate 44, and a via or contact plug (VD) can be formed to extend through the ILD 60 to connect to the S / D metal contact 56. During the formation of the VD, conductive material may leak into the air gap 58 and diffuse across the ILD 50 toward the VG, resulting in a short circuit between adjacent S / D metal contacts 56 and the metal gate 44. To address the leakage problem, the air gap 58 can be sealed by forming a low-k material prior to forming the contact structure. However, the sealing capability and uniformity of low-k sealing materials are often unsatisfactory. Therefore, ion implantation is introduced to cause dielectric expansion of the ILD 50 across the air gap 58, thereby preventing leakage of conductive material during subsequent processes used to form the conductive structure. However, during the ion implantation process, ions implanted into the air gap 58 may damage the S / D feature 36, or even the channel region 14, thereby reducing device performance. The amount of implanted ions that pass through the air gap 58 to reach and collide with the S / D feature 36 may damage the S / D feature or even the adjacent channel region 14.

[0094] In some cases, during the CMP process used to grind the conductive material 55 to form the S / D metal contact 56, the material of the ILD 50 has a faster removal rate than the conductive material 55. As a result, the top surface of the ILD 50 is ground down to a lower level than the top surface of the S / D metal contact 56. For example, the ILD 50 may be recessed from the S / D metal contact 56 by a height “a”, such as... Figure 15A As shown. In this case, the height of the gas gap 58 through which ions can pass is "b". (As shown...) Figure 15B As shown, by controlling the removal rate of ILD 50 and conductive material 55, ILD 50 can be ground to a top surface flush with the top surface of S / D metal contact 56 after the CMP process. Figure 15BIn the illustrated embodiment, the height of the air gap 58 through which ions can pass is increased from "b" to "a+b". When ions are implanted into the air gap 58 at an angle θ, Figure 15A The shorter path "b" allows ions to reach the bottom of the air gap 58 to impact the surface of the S / D feature 36, or even the channel region 14. Conversely, as Figure 15B As shown, for a longer height “a+b”, ions may strike the liner layer 54 before reaching the surface of the S / D feature 36. This reduces the number of ions reaching the surface of the S / D feature 36, thereby mitigating damage to the S / D feature 36 and the channel region 14 caused by subsequent ion implantation processes.

[0095] Figure 16 and Figure 17 One embodiment illustrates a two-step ion implantation process to seal the air gap 58, further suppressing implanted ions from penetrating into the S / D feature 36, thereby minimizing damage to the S / D feature 36 and the channel region 14. In some embodiments, more than two ion implantation steps may also be employed. Figure 16 In this process, the first step of ion implantation is performed on ILD 60 and ILD 50. The implantation depth or thickness of ILD 50 can be adjusted by controlling implantation conditions (such as implantation energy). For example, at a temperature of approximately -100°C to approximately 500°C, the implantation energy is controlled from approximately 1 keV to approximately 10 keV and approximately 1 E14 atoms / cm². 2 Approximately 1E16 atoms / cm 2 The ion dose allows for the implantation of the upper portion of the implantation region 50' with a thickness or depth "c" ranging from approximately 1 nm to approximately 15 nm. Ions 62 can be implanted into ILD 60 and ILD 50 at a tilt angle θ1 of approximately 45° to approximately 60°. Under these implantation conditions, the dopant concentration of the implantation region 50' of ILD 50 is approximately 1E18 atoms / cm². 3 Approximately 1E23 atoms / cm 3 Nitrogen gas can be used in the first step of ion implantation. Other species such as Ge, Xe, Ar, Si, P, B, or O can also be used in the first step of the ion implantation process. The first step of ion implantation causes the material of the ILD 50 in the implantation region 50' to expand across the transected air gap 58, thereby partially sealing the air gap 58. For example... Figure 16 As shown, the portion of the air gap 58 with a thickness or depth of “c” has been sealed by the ILD 50, which has been expanded by the first step of ion implantation.

[0096] The first step of controlled ion implantation, sealing the shallow region of air gap 58 with a relatively large tilt angle, effectively suppresses ion penetration into deeper regions of air gap 58. However, the sealed portion of air gap 58 is too thin to effectively prevent conductive material from penetrating during the subsequent formation of conductive structures such as VD. Therefore, according to some embodiments, a second step of ion implantation is introduced to increase the thickness of the sealed portion of air gap 58 to further suppress conductive material penetration into the unsealed portion of air gap 58. Figure 17 As shown, through the second step of ion implantation depth, the sealing portion can extend from "c" to "d". In some embodiments, the thickness "d" can be approximately the same as the thickness of ILD 50. Because the thickness of ILD 50 is from about 1 to about 60 nm, the thickness "d" of the sealing portion of the air gap 58 can extend to a depth of about 60 nm. According to some embodiments, the "c / d" ratio can be in the range of from about 1 / 4 to about 1 / 2.

[0097] In some embodiments, the second step of ion implantation can be performed at a temperature of about -100°C to about 500°C with an implantation energy of about 15 keV to about 20 keV and about 1 E14 atoms / cm². 2 Approximately 1E16 atoms / cm 2 The nitrogen dosage is adjusted accordingly. Forming a seal at the upper portion of the air gap 58 effectively reduces ion permeation into the S / D feature 36 during the second step of ion implantation. Therefore, ions 64 can be implanted at an angle θ2 smaller than the angle θ1 used in the first step of ion implantation. For example, the angle θ2 can be in the range of about 15° to about 20°. Under such implantation conditions, the portion of the air gap 58 sealed by the second step of ion implantation can have about 1E18 atoms / cm². 2 Approximately 1E23 atoms / cm 2 The dopant concentration. Nitrogen can be used in the second step of ion implantation, while other species such as Ge, Xe, Ar, Si, P, B, or O can also be used in the second step of ion implantation. According to some embodiments, the dopant concentration of the sealing portion 50' is higher than that of the sealing portion 50".

[0098] Following multiple steps in the ion implantation process, a dielectric layer 66 is formed on ILD 60, such as... Figure 18 As shown. The dielectric layer 66 may be an ILD made of materials containing Si, O, C, and / or H (such as SiO2, SiCOH, and SiOC). Organic materials such as polymers may also be used to form ILD 66.

[0099] exist Figure 19AIn this process, a conductive structure is formed, comprising contacts (VD) 74 for contacting the S / D metal contacts 56 and contacts (VG) 72 for contacting the metal gate. VD 74 is formed by patterning ILD 60 and ILD 66 to expose the openings of the S / D metal contacts 56, and then filling the openings with a conductive material such as W, Co, Ru, Ti, Ni, Cu, Au, Ag, Pt, Pd, Ir, Os, Rh, Al, Mo, or the like through appropriate processes such as CVD, PVD, electroplating, or ALD. VG 72 can be formed by patterning ILD60, ILD66, and ILD50 to expose openings in the metal gate 44, and then filling the openings with a conductive material such as W, Co, Ru, Ti, Ni, Cu, Au, Ag, Pt, Pd, Ir, Os, Rh, Al, Mo, or the like using suitable processes such as CVD, PVD, electroplating, or ALD. Figure 19A As shown, the portion of the air gap 58 extending between the adjacent metal gate 44 and the S / D metal contact 56 remains unsealed, thereby effectively reducing parasitic capacitance. At the same time, the S / D feature 36 and the channel region 14 are protected by the sealed portion to prevent damage by implanted ions during each step of the ion implantation process. Figure 19A This indicates that VD 74 forms a well-controlled overlay (OVL). When the OVL is not properly controlled, VD 74 may shift to a misalignment with the S / D metal contact 56, such as... Figure 19B As shown. Therefore, the sealing portions 50' and 50" play a more important role in preventing leakage, which is more likely to occur because a portion of VD 74 is directly above the air gap 58.

[0100] Figure 20 This invention discloses a method for manufacturing a semiconductor device structure 100, the semiconductor device structure having an air gap to minimize the parasitic capacitance C between adjacent conductive structures, such as adjacent metal gates and metal layers (MD) above diffusion layers, for example, S / D metal contacts. eff The method employs a multi-step ion implantation process to seal the air gap, minimizing damage to the S / D features and channel regions. The method further includes an additional ion implantation process prior to the formation of the S / D metal contacts to avoid metal loss.

[0101] The method begins with operation 102, in which a plurality of stacks of channel regions 14 and S / D features 36 are inserted into substrate 10, and metal gates 44 are formed on each of the stacks of channel regions 14. The semiconductor device structure fabricated by operation 102 can be referenced as follows: Figures 1 to 5 The semiconductor device structure 100 is shown. At operation 104, refer to... Figure 6 and Figure 7An ILD 50 is formed above the metal gate 44. For example... Figure 8A As shown, at operation 106, a contact hole 51 is formed to expose the S / D feature 36. At operation 108, as... Figure 9A As shown, silicon spacers 39 are conformally formed on the sidewalls of the contact holes, and a liner layer 54 is formed on the silicon spacers 39. At operation 110, an ion implantation process is performed to treat the silicon spacers 39. The silicon spacers 39 can be treated by implanting nitrogen thereon. At least a portion of the silicon spacers 39 thus undergoes a nitriding process and is transformed into a barrier layer. Figure 12 As shown, during the formation of the S / D metal contact 56, the growth rate of the conductive material 55 used to form the S / D metal contact 56 is reduced to prevent the conductive material 55 from coalescing at the top portion of the contact hole 51 before the lower portion of the contact hole 51 is properly filled with the conductive material 55. This prevents metal loss of the S / D metal contact. According to some embodiments of this disclosure, the S / D metal contact 56 has a top surface flush with the top surface of the ILD 50.

[0102] At operation 114 and in Figure 13A In the process, silicon spacer 39 is removed to form an air gap 58 between the S / D metal contact 56 and the metal gate 44. At operation 116 and in Figure 14 In this process, an ILD 60 is formed on the semiconductor device structure 100. (Referring to a reference...) Figure 16 and Figure 17 At operations 118 and 120, a two-step ion implantation process is performed. As discussed at operation 112, the top surface of the ILD 50 is at the same level as the top surface of the S / D metal contact 56. This reduces the amount of implanted ions reaching the bottom of the contact hole 51 and damaging the S / D feature 36. Therefore, damage to the S / D feature 36 and even the channel region 14 caused by a multi-step ion implantation process can be suppressed. In the first step of ion implantation at operation 118, ions are implanted with a large tilt angle and low implantation energy to control the dielectric expansion of the ILD 50 across the air gap 58 in the shallow top region. The large tilt angle and shallow implantation depth prevent ions from implanting towards the deeper levels of the air gap 58. Therefore, operation 118 creates a shallow sealing portion at the top portion of the air gap 58 to delay ion penetration into the deeper levels of the air gap 58, for example, the portion of the air gap 58 at the same level as the metal gate 44 and directly above the S / D feature 36. The second step of ion implantation can then be performed at operation 120 with higher implantation energy and a smaller tilt angle, because ion penetration toward the deeper level is delayed by the shallow seal at the top of the air gap 58. This second step of ion implantation causes the deeper region of the ILD 50 to expand across the air gap 58, thickening the seal of the air gap 58. At operation 122, an ILD 66 can be formed, and a conductive structure VD is formed through the ILD 66. Figure 19AIn section 74), an electrical connection to the S / D metal contacts is provided. At operation 122, a conductive structure VG also extends through ILDs 66, 60, and 50 to provide an electrical connection to the metal gate 44. Because the top of the air gap 58 is sealed with sufficient depth or thickness, the penetration of VD 74 material is appropriately blocked. This avoids short circuits between the metal gate 44 and the S / D metal contacts 56 caused by leakage of conductive material due to the formation of VD 74.

[0103] According to one embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a channel region in a substrate and a source / drain region formed adjacent to the channel region, a metal gate on the channel region, and an interlayer dielectric layer above the metal gate. Source / drain metal contacts are formed on the source / drain regions, which are adjacent to the metal gate and spaced apart from the metal gate and the interlayer dielectric layer by an air gap structure. The air gap structure includes a sealed portion extending from a top surface level of the interlayer dielectric layer to a bottom surface level and an unsealed portion extending from a bottom surface level of the interlayer dielectric layer to a top surface level of the source / drain regions. The interlayer dielectric layer has a depth of about 1 nm to about 30 nm, such that the sealed portion of the air gap has a depth of about 1 nm to about 30 nm. The air gap structure has a width of about 1 nm to about 3 nm; or about 1 nm to about 5 nm. In some embodiments, the source / drain metal contacts have a top surface flush with the top surface of the first interlayer dielectric layer. In some embodiments, the air gap has a gradient thickness. In some embodiments, the sealing portion of the air gap structure is filled with the material of the first interlayer dielectric layer by dielectric expansion. In some embodiments, the sealing portion of the air gap structure has a depth of about 1 nm to about 30 nm. In some embodiments, the air gap structure has a width of about 1 nm to about 5 nm. In some embodiments, the sealing portion includes a first ion implantation layer and a second ion implantation layer, and the depth ratio of the first ion implantation layer to the second ion implantation layer is about 1 / 4 to about 1 / 2. In some embodiments, the sealing portion of the air gap structure has about 1E18 atoms / cm² from the ion implantation process. 3 Approximately 1E23 atoms / cm 3 The dopant concentration. In some embodiments, the air gap is formed to directly contact a apex of a sidewall spacer formed on the side of the metal gate.

[0104] In another embodiment of this disclosure, a method for fabricating a semiconductor device is provided. The method includes forming a channel region in a substrate, forming source / drain features adjacent to the channel region in the substrate, forming a metal gate on the channel region, forming an interlayer dielectric layer on the metal gate, and forming source / drain metal contacts on the source / drain features. The source / drain metal contacts extend from a bottom surface level of the metal gate to a top surface level of the interlayer dielectric layer. An air gap structure is formed to surround the source / drain metal contacts and isolate them from the metal gate and the first interlayer dielectric layer. The method seals a first portion of the air gap by performing a first ion implantation process with a first implantation energy and a first implantation angle, and seals a second portion of the air gap by performing a second ion implantation process with a second implantation energy and a second implantation angle. The first implantation energy differs from the second implantation energy, and the first implantation angle differs from the second implantation angle. In some embodiments, the method further includes forming a contact hole to expose source / drain features; forming a spacer on the sidewall of the contact hole; treating the spacer with ion implantation prior to forming source / drain metal contacts; filling the contact hole with a conductive material to form source / drain metal contacts; and selectively removing the spacer to form an air gap. In some embodiments, the method further includes performing ion implantation on the spacer prior to forming source / drain metal contacts. In some embodiments, the method further includes performing ion implantation at -100°C to about 500°C with an implantation energy of about 1 keV to about 50 keV and an implantation angle of about 0° to about 90°. In some embodiments, ion implantation is performed at about 1 E14 atoms / cm². 2 Approximately 1E16 atoms / cm 2 The ion dose is administered. In some embodiments, after treatment by ion implantation, the spacer comprises having a density of about 1E19 atoms / cm². 3 Approximately 1E23 atoms / cm 3 The first part of the dopant concentration and having a dopant concentration of less than about 1E18 atoms / cm 3 The second portion of the dopant concentration. In some embodiments, the first implantation energy is about 10 keV and the second implantation energy is about 15 keV to about 20 keV. In some embodiments, the first implantation angle is about 45° and the second implantation angle is about 15° to about 45°. In some embodiments, the sealing portion of the air gap has about 1E19 atoms / cm². 3 Approximately 1E23 atoms / cm 3 The dopant concentration.

[0105] In yet another embodiment of this disclosure, a method is provided for sealing an air gap formed between source / drain metal contacts and a metal gate. The air gap extends from the bottom surface level of the source / drain metal contacts to the top surface level of an interlayer dielectric layer formed on the metal gate. The method includes performing a first ion implantation to seal a first portion of the air gap by dielectric expansion of the interlayer dielectric layer, and performing a second ion implantation to seal a second portion of the air gap by dielectric expansion of the interlayer dielectric layer, the second portion being deeper than the first portion. The first ion implantation process is performed at a first tilt angle, different from the second tilt angle in the second ion implantation process. The method also includes forming a spacer on the sidewall of a contact hole to be filled with the source / drain metal contacts to be formed, treating at least a portion of the spacer with ion implantation, and selectively removing the treated spacer after the source / drain metal contacts are formed. In some embodiments, the method further includes forming a spacer on the sidewall of a contact hole to be filled with a source / drain metal contact to be formed; treating at least a portion of the spacer with ion implantation; and selectively removing the treated spacer after the source / drain metal contact has been formed.

[0106] According to one embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a channel region in a substrate and a source / drain region formed adjacent to the channel region, a metal gate on the channel region, and an interlayer dielectric layer above the metal gate. Source / drain metal contacts are formed on the source / drain region, which is adjacent to the metal gate and spaced from the metal gate and the interlayer dielectric layer by an air gap structure. The air gap structure includes a sealed portion extending from the top surface of the interlayer dielectric layer to a bottom surface level and an unsealed portion extending from the bottom surface level of the interlayer dielectric layer to the top surface level of the source / drain region. The sealed portion includes a first ion implantation layer and a second ion implantation layer.

[0107] According to one embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a channel region in a substrate and a source / drain region formed adjacent to the channel region, a metal gate on the channel region, and an interlayer dielectric layer above the metal gate. Source / drain metal contacts are formed on the source / drain regions, which are adjacent to the metal gate and spaced apart from the metal gate and the interlayer dielectric layer by an air gap structure. The air gap structure includes a sealed portion extending from the top surface of the interlayer dielectric layer to a bottom surface level and an unsealed portion extending from the bottom surface level of the interlayer dielectric layer to the top surface level of the source / drain regions. The sealed portion includes a dopant.

[0108] It should be understood that not all advantages have been discussed in this document, no particular advantage is required for all embodiments or instances, and other embodiments or instances may offer different advantages.

[0109] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A channel region in a substrate and a source / drain region adjacent to the channel region; A metal gate on the channel region and a first interlayer dielectric layer above the metal gate; and A source / drain metal contact on the source / drain region and adjacent to the metal gate and the first interlayer dielectric layer; An air gap structure is disposed between the source / drain metal contact, the metal gate, and the first interlayer dielectric layer, wherein the air gap structure includes: A sealing portion extending from a top surface of the first interlayer dielectric layer to a bottom surface; and An unsealed portion extending from a bottom surface level of the interlayer dielectric layer to a top surface level of the source / drain region.

2. The semiconductor device as claimed in claim 1, characterized in that, The source / drain metal contact has a top surface that is flush with the top surface of the first interlayer dielectric layer.

3. The semiconductor device as claimed in claim 1, characterized in that, The air gap has a gradually varying thickness.

4. The semiconductor device as claimed in claim 3, characterized in that, The sealed portion of the air gap structure is filled with the material of the first interlayer dielectric layer by dielectric expansion.

5. The semiconductor device as claimed in claim 3, characterized in that, The sealing portion of the air gap structure has a depth of 1 nm to 30 nm.

6. The semiconductor device as claimed in claim 1, characterized in that, The air gap structure has a width of 1 nm to 5 nm.

7. The semiconductor device as claimed in claim 1, characterized in that, The sealing portion includes a first ion implantation layer and a second ion implantation layer, and the depth ratio of the first ion implantation layer to the second ion implantation layer is 1 / 4 to 1 / 2.

8. The semiconductor device as claimed in claim 1, characterized in that, The air gap is formed to directly contact a apex of a sidewall spacer formed on the side of the metal gate.

9. A semiconductor device, characterized in that, Include: A channel region in a substrate and a source / drain region adjacent to the channel region; A metal gate on the channel region and a first interlayer dielectric layer above the metal gate; and A source / drain metal contact on the source / drain region and adjacent to the metal gate and the first interlayer dielectric layer; An air gap structure is disposed between the source / drain metal contact, the metal gate, and the first interlayer dielectric layer, wherein the air gap structure includes: A sealing portion extending from a top surface of the first interlayer dielectric layer to a bottom surface, wherein the sealing portion includes a first ion implantation layer and a second ion implantation layer; and An unsealed portion extending from a bottom surface level of the interlayer dielectric layer to a top surface level of the source / drain region.

10. A semiconductor device, characterized in that, Include: A channel region in a substrate and a source / drain region adjacent to the channel region; A metal gate on the channel region and a first interlayer dielectric layer above the metal gate; and A source / drain metal contact on the source / drain region and adjacent to the metal gate and the first interlayer dielectric layer; An air gap structure is disposed between the source / drain metal contact, the metal gate, and the first interlayer dielectric layer, wherein the air gap structure includes: A sealing portion extending from a top surface of the first interlayer dielectric layer to a bottom surface, wherein the sealing portion of the air gap structure has a dopant; and An unsealed portion extending from a bottom surface level of the interlayer dielectric layer to a top surface level of the source / drain region.

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