A multilayer package-on-package structure
By using a multi-layer stacked packaging structure, replacing HBM chips with DRAM chips and combining them with heat sinks and flexible silicon interconnect layers, the high cost and high process difficulty issues in AI chip packaging are solved, achieving low-cost, high-efficiency chip connection and heat dissipation effects, which is suitable for the high-end packaging needs of small and medium-sized enterprises.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- AMQ INTELLIGENT TECH LTD
- Filing Date
- 2025-06-05
- Publication Date
- 2026-05-29
AI Technical Summary
Existing AI chip packaging technologies are characterized by high costs and complex processes, especially the TSV-interposer process, which is complex and costly. EMIB technology suffers from limited interconnect density, difficulty in thermal management, and challenges that traditional air cooling cannot meet.
It adopts a multi-layer stacked packaging structure, uses DRAM chips to replace HBM chips, combines vertical stacking and heat sinks, and achieves chip connection and heat dissipation through a flexible silicon interconnect layer, reducing packaging costs and technical difficulty.
It achieves low-cost, high-efficiency chip connection and heat dissipation, suitable for the high-end packaging needs of small and medium-sized enterprises, reducing packaging costs and technical barriers, and improving the miniaturization and heat dissipation efficiency of the packaging structure.
Smart Images
Figure CN224306302U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor packaging, and in particular to a multilayer stacked packaging structure. Background Technology
[0002] Currently, the packaging technology for AI chip products mainly focuses on 2.5D / 3D packaging, such as CoWoS (chip-on-wafer-on-substrate). CoWoS utilizes TSV interposers and RDL (ReDistribution Layer) to achieve vertical stacking of HBMs and interconnection of multiple chips. This packaging technology can achieve high-density interconnection within a relatively small space, integrating SoC chips, HBM chips, etc. However, the TSV interposer process in CoWoS packaging is complex, and the high cost of equipment and materials significantly increases packaging costs, especially given the low utilization rate of large-size silicon interposers.
[0003] EMIB (Embedded Multi-Die Interconnect Bridge) high-end packaging technology does not use TSV for vertical stacking of HBMs. Instead, it embeds silicon bridges into the substrate to achieve chip interconnection, eliminating the need for a full silicon interposer. This significantly reduces costs compared to the CoWoS full silicon interposer. It also employs high-precision silicon bridge embedding technology, avoiding wafer-level packaging steps and resulting in higher yields. However, this approach limits its interconnect density. Both of these high-end packaging technologies aim to stack HBMs to achieve greater bandwidth, but they are both costly and technologically challenging, with significant challenges in thermal management. Traditional air cooling is insufficient, making liquid cooling the mainstream solution.
[0004] To address the aforementioned shortcomings, this application provides a packaging structure that reduces packaging costs and simplifies packaging technology. Utility Model Content
[0005] This invention provides a multi-layer stacked packaging structure, the purpose of which is to provide a new packaging structure to solve the packaging difficulties of existing AI chips in the packaging process.
[0006] To achieve the above objectives, embodiments of this utility model provide a multi-layer stacked packaging structure, comprising:
[0007] The first unit includes a first substrate, the upper surface of which is an active surface, and a first SoC chip and a plurality of first DRAM chips are flip-chip mounted on the upper surface of the first substrate; the lower surface of the first substrate has solder balls and first LGA pads, and the first LGA pads are located on both sides of the solder balls.
[0008] A heat sink is disposed above a first substrate. The lower surface of the heat sink is recessed upward to form a space for accommodating a first SoC chip and a first DRAM chip. The space has a top surface that contacts the surfaces of the first SoC chip and the first DRAM chip. The heat sink also contacts the surface of the first substrate.
[0009] The second unit includes a second substrate disposed above the first unit. The lower surface of the second substrate is an active surface. A second SoC chip and several second DRAM chips are flip-chip mounted on the lower surface of the second substrate. The second SoC chip and several second DRAM chips are in contact with the heat sink surface. The upper surface of the second substrate has a second LGA pad. A flexible silicon interconnect layer is soldered on the second LGA pad. The middle part of the flexible silicon interconnect layer is soldered to the second LGA pad, and the two ends of the flexible silicon interconnect layer are soldered to the first LGA pad.
[0010] The first unit and the second unit are respectively provided at least one, and the first unit and the second unit are alternately arranged from bottom to top. The solder balls of the first unit are used to electrically connect to the flexible silicon interconnect layer of the second unit on the PCB system or adjacent to the first unit.
[0011] Preferably, the first SoC chip and the first DRAM chip are electrically connected to the first substrate via a first bump.
[0012] Preferably, an underfill is provided between the first SoC chip and the first substrate, and between the first DRAM chip and the first substrate.
[0013] Preferably, a first thermal interface layer is filled between the first SoC chip and the top surface, between the first DRAM chip and the top surface, and between the heat sink and the first substrate.
[0014] Preferably, the second SoC chip and the second DRAM chip are electrically connected to the second substrate via the second bump, respectively.
[0015] Preferably, an underfill is provided between the second SoC chip and the second substrate, and between the second DRAM chip and the second substrate.
[0016] Preferably, a second thermal interface layer is provided between the lower surface of the second SoC chip and the second DRAM chip and the heat sink, respectively.
[0017] Preferably, one first unit and one second unit are provided, with the second unit located above the first unit, and the solder balls of the first unit are used for electrical connection to the PCB system.
[0018] Preferably, the first unit and the second unit are provided in two or more, and the number of the first unit and the second unit are the same. The first unit and the second unit are arranged alternately from bottom to top. The solder balls of the first unit at the bottom are used for electrical connection to the PCB system, and the solder balls of the remaining first units are used for electrical connection to the flexible silicon interconnect layer of the second unit below the corresponding first unit.
[0019] Preferably, at least one first unit and at least one second unit are provided, and the number of first units is one more than the number of second units. The first units and the second units are arranged alternately from bottom to top. The solder balls of the first unit located at the bottom are used for electrical connection to the PCB system, and the solder balls of the remaining first units are used for electrical connection to the flexible silicon interconnect layer of the second unit below the corresponding first unit.
[0020] The above-mentioned solution of this utility model has the following beneficial effects:
[0021] First, this application, as a form of 2D / 2.5D packaging, uses DRAM chips to replace HBM chips, and utilizes multiple DRAM chips to achieve the same bandwidth as HBM.
[0022] Secondly, the vertical stacking method solves the problem of large package size caused by horizontal connection of multiple SoC chips and DRAM chips. In addition, the heat sink between the first unit and the second unit can alleviate the heat dissipation problem of SoC chips and DRAM chips in the first unit and the second unit to a certain extent, and provide mechanical support and fixation for the first unit and the second unit.
[0023] Third, the flexible silicon interconnect layer can not only connect the first and second units to serve as a connection path for the SoC chip and DRAM chip on them, but also provide a heat dissipation path and mechanical support for the heat sink.
[0024] Other features and advantages of this invention will be described in detail in the following detailed description section. Attached Figure Description
[0025] Figure 1 This is a cross-sectional view of the first embodiment;
[0026] Figure 2 This is a sectional view of the first unit;
[0027] Figure 3 This is a cross-sectional view of the second unit (with the flexible silicon interconnect layer hidden);
[0028] Figure 4 This is a cross-sectional view of the second embodiment;
[0029] Figure 5 This is a cross-sectional view of the third embodiment.
[0030] [Explanation of Labels in the Attached Image]
[0031] 10-First unit, 11-First substrate, 12-First SoC chip, 13-First DRAM chip, 14-Heat sink, 15-Solder ball, 16-First LGA pad, 17-First bump, 18-First thermal interface layer
[0032] 20 - Second unit, 21 - Second substrate, 22 - Second SoC chip, 23 - Second DRAM chip, 24 - Second LGA pad, 25 - Flexible silicon interconnect layer, 26 - Second bump, 27 - Second thermal interface layer
[0033] 30-PCB system. Detailed Implementation
[0034] To make the technical problems, technical solutions and advantages of this utility model clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.
[0035] Definitions:
[0036] SoC chip: System on Chip;
[0037] DRAM chip: Dynamic Random Access Memory chip;
[0038] LGA pads: Land Grid Array, also known as pad grid array;
[0039] Flexible Silicon Interconnect Layer.
[0040] like Figure 1-3 As shown, an embodiment of this utility model provides a multi-layer stacked package structure, including a first unit 10, a heat sink 14, and a second unit 20, which are stacked vertically. Specifically, the first unit 10 includes a first substrate 11, on which a first SoC chip 12 and a first DRAM chip 13 are flip-chip mounted on the upper surface (i.e., the active surface) of the first substrate 11, and a plurality of first DRAM chips 13 are arranged around the first SoC chip 12. The lower surface of the first substrate 11 has a first LGA pad 16 and solder balls 15 soldered thereon, with the first LGA pad 16 located on both sides of the solder balls 15.
[0041] The multilayer stacked package structure also includes a heat sink 14, which is disposed above the first substrate 11. The lower surface of the heat sink 14 is recessed upwards at its center to form a space for accommodating the first SoC chip 12 and the first DRAM chip 13. This space has a top surface that contacts the first SoC chip 12 and the first DRAM chip 13, allowing the heat generated by the first SoC chip 12 and the first DRAM chip 13 during operation to be dissipated through the heat sink 14. The lower end of the heat sink 14 also makes surface contact with the first substrate 11.
[0042] The multilayer stacked package structure also includes a second unit 20 including a second substrate 21, which is located above the first unit 10, i.e. above the first substrate 11. A second SoC chip 22 and several second DRAM chips 23 are flip-chip mounted on the lower surface (i.e., the active surface) of the second substrate 21. Similarly, several second DRAM chips 23 are arranged around the second SoC chip 22. The lower surfaces of the second SoC chip 22 and the second DRAM chips 23 are in surface contact with the heat sink 14, so that the heat generated by the second SoC chip 22 and the second DRAM chips 23 during operation is dissipated through the heat sink 14. A second LGA pad 24 is provided on the upper surface of the second substrate 21. A flexible silicon interconnect layer 25 is soldered on the second LGA pad 24. The middle part of the flexible silicon interconnect layer 25 is soldered to the second LGA pad 24, and the two ends are soldered to the first LGA pad 16.
[0043] The multilayer stacked package structure has at least one first unit 10 and at least one second unit 20, the first unit 10 and the second unit 20 are alternately arranged from bottom to top, and the first unit 10 is located at the bottom of the multilayer stacked package structure. The solder balls 15 of the first unit 10 are used for electrical connection to the PCB system 30 or the flexible silicon interconnect layer 25 of the second unit 20 located below the first unit 10 and adjacent to the first unit 10.
[0044] In this application, a first DRAM chip 13 and a second DRAM chip 23 are used to replace the HBM chip, and the length and width of each substrate in the horizontal direction are reduced by using a multi-layer vertical stacking method, which can realize the miniaturization of the package structure. At the same time, considering that the individual chips inside the package structure are difficult to dissipate heat, on the one hand, the heat sink 14 is set to provide mechanical support for the first unit 10 and the second unit 20, while dissipating the heat of each chip through the heat sink 14. On the other hand, the flexible silicon interconnect layer 25 realizes the electrical connection between the SoC chip and the DRAM chip in the first unit 10 and the second unit 20, which can also be used in conjunction with the heat sink 14 for heat dissipation.
[0045] This application has low packaging costs and low technical barriers, which can alleviate the high costs and technical difficulties faced by most small and medium-sized enterprises in developing high-end packaging technologies, and provide them with transitional products in the high-end packaging technology business segment.
[0046] In this application, the circuit-containing sides of the first SoC chip 12 and the first DRAM chip 13 are flip-chip mounted on the first substrate 11 via the first bump 17, thereby realizing that the first SoC chip 12 and the first DRAM chip 13 are electrically connected to the first substrate 11 respectively. The first SoC chip 12 and the first DRAM chip 13 are connected by flip-chip technology, which can not only shorten the interconnection path, but also improve the signal arrangement.
[0047] An underfill is filled between the first SoC chip 12 and the first substrate 11, and between the first DRAM chip 13 and the first substrate 11. The function of the underfill is to cover the gaps between the first SoC chip 12 and the first substrate 11, and between the first DRAM chip 13 and the first substrate 11.
[0048] The lower surface of the aforementioned heat sink 14 is recessed upwards at its center to form a space for accommodating the first SoC chip 12 and the first DRAM chip 13. A bottom surface is formed around this space, which is lower than the top surface. The upper surfaces (i.e., the silicon side) of the first SoC chip 12 and the first DRAM chip 13 are coated with a thermal interface material to form a first thermal interface layer 18. The first SoC chip 12 and the first DRAM chip 13 form surface contact with the top surface through the first thermal interface layer 18, thereby allowing the heat from the first SoC chip 12 and the first DRAM chip 13 to be transferred to the heat sink 14 through the first thermal interface layer 18. Similarly, a thermal interface material is coated on the lower surface of the heat sink 14 to form a first thermal interface layer 18 between the lower surface of the heat sink 14 and the first substrate 11, allowing the heat transferred from the first SoC chip 12 and the first DRAM chip 13 to the first substrate 11 to be dissipated through the heat sink 14.
[0049] Similarly, the second SoC chip 22 and the second DRAM chip 23 are flip-mounted onto the second substrate 21 via the second bump 26, thereby realizing that the second SoC chip 22 and the second DRAM chip 23 are electrically connected to the second substrate 21 respectively. Underfill is filled between the second SoC chip 22 and the second substrate 21, and between the second DRAM chip 23 and the second substrate 21. The function of the underfill is to cover the gap between the second SoC chip 22 and the second substrate 21, and between the second DRAM chip 23 and the second substrate 21.
[0050] Thermal interface materials are coated on the lower surface of the second SoC chip 22 and the lower surface of the second DRAM chip 23 to form a second thermal interface layer 27 that contacts the heat sink 14, so that the heat generated by the second SoC chip 22 and the second DRAM chip 23 is discharged through the heat sink 14.
[0051] Solder paste is applied to the second LGA pad 24 of the aforementioned second substrate 21 and soldered to the solder joint in the middle of the flexible silicon interconnect layer 25. Solder paste is also applied to the first LGA pad 16 of the first substrate 11 and soldered to the solder joints at both ends of the flexible silicon interconnect layer 25.
[0052] In this application, there are multiple ways to arrange the first unit 10 and the second unit 20. In this embodiment, one first unit 10 and one second unit 20 are each provided. The second unit 20 is located above the first unit 10, and the second SoC chip 22 and the second DRAM chip 23 are connected to the heat sink 14 through the second thermal interface layer 27. The solder balls 15 of the first unit 10 are used for electrical connection with the PCB system 30.
[0053] like Figure 4 In another embodiment of this application, at least one first unit 10 and one second unit 20 are provided, and the first unit 10 has one more than the second unit 20. Starting from the first unit 10, the units are stacked vertically layer by layer, alternating upwards. The solder ball 15 on the bottommost first unit 10 is used for electrical connection to the PCB system 30, and the solder balls 15 on the remaining first units 10 are used to connect the middle part of the flexible silicon interconnect layer 25 of the second unit 20 adjacent to the first unit 10 below the first unit 10.
[0054] like Figure 5 In another embodiment of this application, two or more first units 10 and second units 20 are provided respectively, and the number of first units 10 and second units 20 is the same. Starting from the first unit 10, they are stacked layer by layer and alternately along the vertical direction. The solder balls 15 on the bottom first unit 10 are used for electrical connection to the PCB system 30, and the solder balls 15 on the remaining first units 10 are used to connect the middle part of the flexible silicon interconnect layer 25 of the second unit 20 below the first unit 10 and adjacent to the first unit 10.
[0055] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.
Claims
1. A multi-layer stacked packaging structure, characterized in that, include: The first unit (10) includes a first substrate (11), the upper surface of the first substrate (11) is an active surface, and a first SoC chip (12) and a plurality of first DRAM chips (13) are flip-chip mounted on the upper surface of the first substrate (11); the lower surface of the first substrate (11) has solder balls (15) and first LGA pads (16), and the first LGA pads (16) are located on both sides of the solder balls (15); A heat sink (14) is disposed above the first substrate (11). The lower surface of the heat sink (14) is recessed upward to form a space for accommodating the first SoC chip (12) and the first DRAM chip (13). The space has a top surface that contacts the surfaces of the first SoC chip (12) and the first DRAM chip (13). The heat sink (14) also contacts the surface of the first substrate (11). The second unit (20) includes a second substrate (21) disposed above the first unit (10). The lower surface of the second substrate (21) is an active surface. A second SoC chip (22) and a plurality of second DRAM chips (23) are flip-chip mounted on the lower surface of the second substrate (21). The second SoC chip (22) and the plurality of second DRAM chips (23) are in contact with the heat sink (14). The upper surface of the second substrate (21) has a second LGA pad (24). A flexible silicon interconnect layer (25) is soldered on the second LGA pad (24). The middle part of the flexible silicon interconnect layer (25) is soldered to the second LGA pad (24). The two ends of the flexible silicon interconnect layer (25) are soldered to the first LGA pad (16). The first unit (10) and the second unit (20) are respectively provided with at least one, and the first unit (10) and the second unit (20) are alternately arranged from bottom to top. The solder ball (15) of the first unit (10) is used to electrically connect to the flexible silicon interconnect layer (25) of the second unit (20) adjacent to the first unit (10) on the PCB system (30).
2. The multilayer stacked packaging structure according to claim 1, characterized in that: The first SoC chip (12) and the first DRAM chip (13) are electrically connected to the first substrate (11) through the first bump (17).
3. The multilayer stacked packaging structure according to claim 2, characterized in that: The first SoC chip (12) and the first substrate (11) are filled with underfill adhesive, and the first DRAM chip (13) and the first substrate (11) are filled with underfill adhesive.
4. The multilayer stacked packaging structure according to claim 1, characterized in that: A first thermal interface layer (18) is filled between the first SoC chip (12) and the top surface, between the first DRAM chip (13) and the top surface, and between the heat sink (14) and the first substrate (11).
5. The multilayer stacked packaging structure according to claim 1, characterized in that: The second SoC chip (22) and the second DRAM chip (23) are electrically connected to the second substrate (21) via the second bump (26).
6. The multilayer stacked packaging structure according to claim 5, characterized in that: The space between the second SoC chip (22) and the second substrate (21), and between the second DRAM chip (23) and the second substrate (21) are filled with underfill adhesive.
7. The multilayer stacked packaging structure according to claim 1, characterized in that: A second thermal interface layer (27) is provided between the lower surface of the second SoC chip (22) and the second DRAM chip (23) and the heat sink (14).
8. The multilayer stacked packaging structure according to claim 1, characterized in that: One first unit (10) and one second unit (20) are provided. The second unit (20) is located above the first unit (10). The solder balls (15) of the first unit (10) are used for electrical connection to the PCB system (30).
9. The multilayer stacked packaging structure according to claim 1, characterized in that: The first unit (10) and the second unit (20) are provided in two or more, and the number of the first unit (10) and the second unit (20) is the same. The first unit (10) and the second unit (20) are arranged alternately from bottom to top. The solder ball (15) of the first unit (10) at the bottom is used for electrical connection to the PCB system (30), and the solder balls (15) of the other first units (10) are used for electrical connection to the flexible silicon interconnect layer (25) of the second unit (20) below the corresponding first unit (10).
10. The multilayer stacked packaging structure according to claim 1, characterized in that: The first unit (10) and the second unit (20) are respectively provided at least one, and the number of the first unit (10) is one more than the number of the second unit (20). The first unit (10) and the second unit (20) are arranged alternately from bottom to top. The solder ball (15) of the first unit (10) located at the bottom is used for electrical connection to the PCB system (30), and the solder balls (15) of the remaining first units (10) are used for electrical connection to the flexible silicon interconnect layer (25) of the second unit (20) below the corresponding first unit (10).