Electromagnetic shielded package structure

Abstract

The utility model relates to an electromagnetic shielding packaging structure, the electromagnetic shielding packaging structure includes: adapter plate, including substrate and multiple recesses in the substrate, and multiple recesses are independent of one another, wiring layer is located on the adapter plate, multiple first chips are located in multiple recesses respectively, and multiple first chips all are connected with wiring layer electricity, electromagnetic shielding layer covers on the inner wall of recess, second chip is located above the adapter plate and is connected with wiring layer electricity, the utility model can integrate radio frequency chip and other multiple types of chips in recess, and has simplified the manufacturing process of packaging structure, reduced the manufacturing cost and manufacturing difficulty of packaging structure.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor manufacturing technology, and in particular to an electromagnetic shielding packaging structure. Background Technology

[0002] As various technology industries place increasingly higher demands on the integration and electrical performance of semiconductor devices, packaging technology also needs to adapt and continuously evolve and innovate. When integrating multiple chips using traditional 2D packaging technologies, such as fan-out packaging structures, the size of the package structure (e.g., volume or surface area) increases, limiting its application in products with size constraints. To address this issue, 3D packaging structures have emerged. Current advanced 3D packaging structures increasingly employ die-to-die mounting, with the base die often being an active silicon interposer, and using TMV (Through Molding Via) technology to connect the upper and lower packages. However, this three-dimensional packaging structure has at least the following problems: (1) The base chip is an active chip formed by TSV (Through Silicon Via) process, which has a high processing cost; (2) It does not have electromagnetic shielding function, so it is not suitable for integrating radio frequency chips inside the packaging structure; (3) The chip-to-chip bonding process is a high-cost process, which leads to a significant increase in the manufacturing cost of the packaging structure; (4) The use of TMV process results in a limited number of I / O interfaces, which is not suitable for interconnection that requires a high number of I / O interfaces; (5) The thickness of the entire three-dimensional packaging structure is large, which is not conducive to the miniaturization of the packaging structure.

[0003] Therefore, how to simplify the manufacturing process of packaging structures and reduce their manufacturing costs while expanding their functionality so that they can integrate multiple types of chips is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This invention provides an electromagnetic shielding packaging structure that simplifies the manufacturing process and reduces the manufacturing cost of the packaging structure while expanding its functionality, enabling the packaging structure to integrate multiple types of chips.

[0005] According to some embodiments, this utility model provides an electromagnetic shielding packaging structure, including:

[0006] An adapter plate includes a substrate and a plurality of grooves located within the substrate, wherein the plurality of grooves are independent of each other;

[0007] The wiring layer is located on the adapter board;

[0008] Multiple first chips are respectively located in multiple grooves, and all multiple first chips are electrically connected to the wiring layer;

[0009] An electromagnetic shielding layer covers the inner wall of the groove;

[0010] The second chip is located above the adapter board and is electrically connected to the wiring layer.

[0011] In some embodiments, the electromagnetic shielding layer covers the entire inner wall of the groove; or,

[0012] The electromagnetic shielding layer covers the inner wall of a portion of the grooves.

[0013] In some embodiments, each of the first chips includes a functional surface and a back surface that are relatively distributed;

[0014] The functional surface of the first chip faces the wiring layer, and the back surface of the first chip is bonded to the surface of the electromagnetic shielding layer by an adhesive layer.

[0015] In some embodiments, the adapter board includes an upper surface and a lower surface that are oppositely distributed, and the second chip is located above the upper surface of the adapter board;

[0016] The plurality of grooves are arranged at intervals along a direction parallel to the upper surface of the adapter plate.

[0017] In some embodiments, the adapter board includes an upper surface and a lower surface that are oppositely distributed, and the second chip is located above the upper surface of the adapter board;

[0018] The plurality of grooves are arranged at intervals along a direction perpendicular to the upper surface of the adapter plate.

[0019] In some embodiments, the adapter board includes an upper surface and a lower surface that are oppositely distributed, and the second chip is located above the upper surface of the adapter board;

[0020] A portion of the grooves are spaced apart along a direction parallel to the upper surface of the adapter plate, and at least two of the grooves are spaced apart along a direction perpendicular to the upper surface of the adapter plate.

[0021] In some embodiments, a portion of the grooves are bottom grooves and another portion of the grooves are top grooves. The bottom grooves extend from the lower surface of the adapter plate toward the interior of the adapter plate, and a plurality of the bottom grooves are spaced apart in a direction parallel to the upper surface of the adapter plate. The top grooves extend from the upper surface of the adapter plate toward the interior of the adapter plate.

[0022] In some embodiments, the projection of the top groove onto the upper surface of the adapter plate is greater than the projection of the bottom groove onto the upper surface of the adapter plate.

[0023] In some embodiments, a plurality of top grooves are distributed one-to-one above a plurality of bottom grooves, and the width of each top groove is the same as the width of its corresponding bottom groove.

[0024] In some embodiments, the wiring layer includes:

[0025] A top wiring layer is located on the upper surface of the adapter board, and the second chip and the first chip located in the top groove are both electrically connected to the top wiring layer;

[0026] A bottom wiring layer is located on the lower surface of the adapter board. The first chip located in the bottom groove is electrically connected to the bottom wiring layer, and the top wiring layer is electrically connected to the bottom wiring layer.

[0027] In some embodiments, the adapter plate further includes:

[0028] A first conductive connection post penetrates the substrate, with one end of the first conductive connection post electrically connected to the top wiring layer and the other end electrically connected to the bottom wiring layer.

[0029] In some embodiments, the electromagnetic shielding layer includes a top electromagnetic shielding layer and a bottom electromagnetic shielding layer that are independent of each other;

[0030] The top electromagnetic shielding layer covers the inner wall of the top groove and is electrically connected to the top wiring layer, and the bottom electromagnetic shielding layer covers the inner wall of the bottom groove and is electrically connected to the bottom wiring layer.

[0031] In some embodiments, the electromagnetic shielding layer includes a top electromagnetic shielding layer and a bottom electromagnetic shielding layer electrically connected to the top electromagnetic shielding layer;

[0032] The top electromagnetic shielding layer covers the inner wall of the top groove, and the bottom electromagnetic shielding layer covers the inner wall of the bottom groove and is electrically connected to the bottom wiring layer.

[0033] In some embodiments, it also includes:

[0034] A second conductive connection post is located within the substrate, with one end of the second conductive connection post electrically connected to the top electromagnetic shielding layer and the other end electrically connected to the bottom electromagnetic shielding layer.

[0035] In some embodiments, the bottom electromagnetic shielding layer continuously covers the inner walls of the plurality of bottom grooves and the surface of the bottom wiring layer between adjacent bottom grooves;

[0036] The second conductive connection post extends between adjacent bottom grooves and is electrically connected to the bottom electromagnetic shielding layer located between adjacent bottom grooves.

[0037] In some embodiments, it also includes:

[0038] A first molding layer is filled in the plurality of said grooves, and the first molding layer covers the surface of the electromagnetic shielding layer and molds the plurality of the first chips;

[0039] A second molding layer is located above the adapter board, and the second molding layer encapsulates the second chip.

[0040] The electromagnetic shielding packaging structure provided by this utility model forms multiple independent grooves within an adapter board, and mounts multiple first chips into these grooves. An electromagnetic shielding layer is formed within each groove, at least covering the inner wall of the groove. A wiring layer is formed on the adapter board, and a second chip is mounted onto the wiring layer. Both the first and second chips are electrically connected to the wiring layer. The electromagnetic shielding layer provides electromagnetic shielding to the grooves, enabling the integration of various types of chips, such as radio frequency chips, within the grooves. This expands the functionality and application areas of the packaging structure. The multiple discrete grooves isolate the first chips within different grooves, preventing mutual interference between first chips integrated within the adapter board. The wiring layer enables electrical connections between the second chip and the adapter board, as well as between the second chip and the first chip, eliminating the need for chip-to-chip bonding. This simplifies the manufacturing process, significantly reduces manufacturing costs, and helps reduce the overall thickness of the packaging structure, promoting miniaturization. By providing multiple independent grooves within the adapter board, and using these grooves to accommodate the first chip, combined with the wiring layer, a large number of I / O interface interconnects can be provided, making it suitable for fabricating package structures requiring a high number of I / O interfaces. This invention eliminates the need for processes such as TMV, thereby further reducing manufacturing costs and complexity. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0042] Figure 1 This is a cross-sectional schematic diagram of the electromagnetic shielding packaging structure in a specific embodiment of this utility model;

[0043] Figure 2 This is a schematic diagram showing the relative positional relationship between the adapter board and the first chip in a specific embodiment of this utility model;

[0044] Figure 3 This is a cross-sectional schematic diagram of the adapter plate in a specific embodiment of this utility model;

[0045] Figure 4 This is another cross-sectional schematic diagram of the electromagnetic shielding packaging structure in a specific embodiment of this utility model;

[0046] Figure 5 This is a schematic diagram showing another relative positional relationship between the adapter board and the first chip in a specific embodiment of this utility model;

[0047] Figure 6 This is another cross-sectional schematic diagram of the electromagnetic shielding packaging structure in a specific embodiment of this utility model;

[0048] Figure 7 This is a schematic diagram showing another relative positional relationship between the adapter board and the first chip in a specific embodiment of this utility model;

[0049] Figure 8 This is another cross-sectional schematic diagram of the adapter plate in a specific embodiment of this utility model;

[0050] Figure 9 This is another cross-sectional schematic diagram of the electromagnetic shielding packaging structure in a specific embodiment of this utility model;

[0051] Figure 10 This is a schematic diagram showing another relative positional relationship between the adapter board and the first chip in a specific embodiment of this utility model. Detailed Implementation

[0052] The specific embodiments of the electromagnetic shielding packaging structure provided by this utility model will be described in detail below with reference to the accompanying drawings.

[0053] This specific embodiment provides an electromagnetic shielding packaging structure. Figure 1 This is a first cross-sectional schematic diagram of the electromagnetic shielding packaging structure in a specific embodiment of this utility model. Figure 2 This is a schematic diagram showing the relative positional relationship between the adapter board and the first chip in a specific embodiment of this utility model. Figure 3 This is a cross-sectional schematic diagram of the adapter plate in a specific embodiment of this utility model. For example... Figure 1 , Figure 2 and Figure 3 As shown, the electromagnetic shielding encapsulation structure includes:

[0054] The adapter plate includes a substrate 10 and a plurality of grooves 30 located within the substrate 10, wherein the plurality of grooves 30 are independent of each other;

[0055] The wiring layer is located on the adapter board;

[0056] Multiple first chips 11 are respectively located in multiple grooves 30, and all multiple first chips 11 are electrically connected to the wiring layer;

[0057] An electromagnetic shielding layer 15 covers the inner wall of the groove 30;

[0058] The second chip 12 is located above the adapter board and is electrically connected to the wiring layer.

[0059] Specifically, the substrate 10 in the adapter plate can be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. By etching the substrate 10, multiple independent grooves 30 can be formed in the substrate 10. The grooves 30 are used to accommodate the first chip 11. The multiple grooves 30 are independent of each other, that is, the first chips 11 in different grooves 30 are isolated from each other by dividing the space into cavities. This ensures that while multiple first chips 11 are integrated in the adapter plate, mutual interference between the first chips 11 in adjacent grooves 30 is avoided, for example, signal crosstalk between the first chips 11 in adjacent grooves 30 is avoided. In one example, none of the grooves 30 penetrate the substrate 10. The electromagnetic shielding layer 15 covers at least the inner wall of one groove 30, so that at least one groove 30 has electromagnetic shielding function. This allows radio frequency chips to be mounted in the groove 30 with the electromagnetic shielding layer 15, thereby expanding the types of chips that can be integrated into the packaging structure and broadening the application field of the packaging structure. In one example, the first chips 11 disposed in different recesses 30 are of the same type (e.g., have the same function and structure). In another example, the first chips 11 disposed in at least two recesses 30 are of different types (e.g., have different functions or structures).

[0060] The wiring layer is disposed on the adapter board. In one example, the wiring layer is a high-density wiring layer, and the wiring layer includes a dielectric layer and high-density metal traces located within the dielectric layer. The wiring layer is electrically connected to the adapter board. Multiple first chips 11 and second chips 12 are all electrically connected to the wiring layer, thereby achieving electrical connections between the second chip 12 and the adapter board, between the second chip 12 and the first chip 11, and between multiple first chips 11 through the wiring layer. This eliminates the need for chip-to-chip bonding, simplifying the packaging structure manufacturing process, significantly reducing the manufacturing cost of the packaging structure, and helping to reduce the overall thickness of the packaging structure, promoting the miniaturization of the packaging structure. By providing multiple independent recesses 30 within the adapter board, and utilizing the recesses 30 to accommodate the first chips 11, combined with the wiring layer, a large number of I / O interface interconnections can be provided for the adapter board, suitable for the fabrication of packaging structures requiring a high number of I / O interfaces. In this specific embodiment, processes such as TMV are not required, further reducing manufacturing costs and difficulty. In this specific embodiment, "multiple" refers to two or more.

[0061] In some embodiments, the electromagnetic shielding layer 15 covers the entire inner wall of the groove 30; or,

[0062] The electromagnetic shielding layer 15 covers a portion of the inner walls of the grooves 30.

[0063] In one example, the inner wall of each groove 30 (including the sidewalls and bottom wall of the groove 30) is covered with the electromagnetic shielding layer 15, thereby enabling electromagnetic shielding of the first chip 11 in each groove 30. This achieves cavity-based electromagnetic shielding within the adapter plate, ensuring that the first chip 11 is protected from electromagnetic interference from the external environment and also achieving electromagnetic shielding between the first chips 11 in adjacent grooves 30, thus ensuring the stability and reliability of the electromagnetic shielding packaging structure.

[0064] In another example, only a portion of the inner walls of the grooves 30 are covered with the electromagnetic shielding layer 15, while the inner walls of another portion of the grooves 30 are not covered with the electromagnetic shielding layer 15. This allows different types of chips to be mounted in different grooves 30 according to actual needs (e.g., radio frequency chips are mounted in grooves 30 with the electromagnetic shielding layer 15, and non-radio frequency chips are mounted in grooves 30 without the electromagnetic shielding layer 15). This further improves the flexibility of chip integration within the electromagnetic shielding package structure and helps to further reduce the manufacturing cost of the electromagnetic shielding package structure.

[0065] In some embodiments, each of the first chips 11 includes a functional surface and a back surface that are relatively distributed;

[0066] The functional surface of the first chip 11 faces the wiring layer, and the back surface of the first chip 11 is bonded to the surface of the electromagnetic shielding layer 15 by the adhesive layer 23.

[0067] For example, each of the first chips 11 includes a functional surface and a back surface that are relatively distributed, and a first conductive bump 13 is provided on the functional surface of the first chip 11. The functional surface of the first chip 11 located in the groove 30 faces the wiring layer, and the first chip 11 is electrically connected to the wiring layer through the first conductive bump 13. The back surface of the first chip 11 is covered with the adhesive layer 23, and the first chip 11 is bonded to the surface of the electromagnetic shielding layer 15 on the bottom wall of the groove through the adhesive layer 23, so as to stably fix the first chip 11 in the groove 30. In one example, the adhesive layer 23 is an insulating adhesive layer.

[0068] In some embodiments, the adapter board includes an upper surface and a lower surface that are oppositely distributed, and the second chip 12 is located above the upper surface of the adapter board;

[0069] A number of the grooves 30 are spaced apart along a direction parallel to the upper surface of the adapter plate, and at least two of the grooves 30 are spaced apart along a direction perpendicular to the upper surface of the adapter plate.

[0070] In some embodiments, a portion of the grooves 30 are bottom grooves, and another portion of the grooves 30 are top grooves. The bottom grooves extend from the lower surface of the adapter plate toward the interior of the adapter plate, and a plurality of the bottom grooves are spaced apart in a direction parallel to the upper surface of the adapter plate. The top grooves extend from the upper surface of the adapter plate toward the interior of the adapter plate.

[0071] In some embodiments, the projection of the top groove onto the upper surface of the adapter plate is greater than the projection of the bottom groove onto the upper surface of the adapter plate.

[0072] For example, the substrate 10 includes a top surface and a bottom surface that are relatively distributed, with the top surface of the substrate 10 serving as the upper surface of the adapter plate and the bottom surface of the substrate 10 serving as the lower surface of the adapter plate. A portion of the grooves 30 serve as bottom grooves, and each bottom groove extends from the bottom surface of the substrate 10 in a direction perpendicular to the top surface of the substrate 10 toward the interior of the substrate 10. The number of bottom grooves can be one or more. When there are multiple bottom grooves, the multiple bottom grooves are spaced apart in a direction parallel to the top surface of the substrate 10. The bottom grooves do not penetrate the substrate 10 in a direction perpendicular to the top surface of the substrate 10. The grooves 30 other than the bottom grooves serve as top grooves, and each top groove extends from the top surface of the substrate 10 in a direction perpendicular to the top surface of the substrate 10 toward the interior of the substrate 10. The number of top grooves can be one or more. When there are multiple top grooves, the multiple top grooves are spaced apart in a direction parallel to the top surface of the substrate 10. Figure 1 , Figure 2 and Figure 3 The following description uses an example where the substrate 10 includes two bottom recesses and one top recess. The projection of the top recess onto the upper surface of the adapter plate is greater than the projection of the bottom recess onto the upper surface of the adapter plate. This allows the first chip 11 of different sizes to be mounted in the top and bottom recesses, thereby further improving the manufacturing flexibility of the electromagnetic shielding packaging structure and further expanding its application areas.

[0073] Figure 4 This is another cross-sectional schematic diagram of the electromagnetic shielding packaging structure in a specific embodiment of this utility model. Figure 5 This is a schematic diagram illustrating another relative positional relationship between the adapter board and the first chip in a specific embodiment of this utility model. In other embodiments, multiple top grooves are distributed one-to-one above multiple bottom grooves, and the width of each top groove is the same as the width of its corresponding bottom groove.

[0074] In one example, such as Figure 4 and Figure 5 As shown, the substrate 10 includes a plurality of (e.g., two) bottom recesses and a plurality of top recesses corresponding one-to-one with the plurality of bottom recesses, thereby further increasing the number of the first chips integrated within the adapter board. This improves the integration density of the electromagnetic shielding packaging structure, provides the adapter board with a greater number of I / O interfaces, and simplifies the manufacturing process of the adapter board. In one example, as... Figure 4 and Figure 5As shown, the size of the top recess (e.g., the width of the top recess along the direction parallel to the top surface of the substrate 10) is the same as the size of the bottom recess (e.g., the width of the bottom recess along the direction parallel to the top surface of the substrate 10).

[0075] Figure 6 This is another cross-sectional schematic diagram of the electromagnetic shielding encapsulation structure in a specific embodiment of this utility model. Figure 7 This is a schematic diagram illustrating another relative positional relationship between the adapter board and the first chip in a specific embodiment of this utility model. Figure 8 This is another cross-sectional schematic diagram of the adapter plate in a specific embodiment of the present invention. In some other embodiments, the adapter plate includes an upper surface and a lower surface that are distributed opposite to each other, and the second chip 12 is located above the upper surface of the adapter plate;

[0076] The plurality of grooves 30 are arranged at intervals along a direction perpendicular to the upper surface of the adapter plate.

[0077] For example, such as Figure 6 , Figure 7 and Figure 8 As shown, the substrate 10 includes a top surface and a bottom surface that are distributed opposite to each other, with the top surface of the substrate 10 serving as the upper surface of the adapter plate and the bottom surface of the substrate 10 serving as the lower surface of the adapter plate. The substrate 10 has two grooves 30 spaced apart along a direction perpendicular to the top surface of the substrate 10, thereby making the lateral dimension of each groove 30 relatively large, facilitating the integration of a large-sized first chip 11 within the substrate 10.

[0078] In some other embodiments, the adapter board includes an upper surface and a lower surface that are oppositely distributed, with the second chip 12 located above the upper surface of the adapter board;

[0079] The plurality of grooves 30 are arranged at intervals along a direction parallel to the upper surface of the adapter plate.

[0080] For example, the substrate 10 includes a top surface and a bottom surface that are distributed opposite to each other, with the top surface of the substrate 10 serving as the upper surface of the adapter plate and the bottom surface of the substrate 10 serving as the lower surface of the adapter plate. A plurality of grooves 30 extend from the top surface of the substrate 10 into the interior of the substrate, or a plurality of grooves 30 extend from the bottom surface of the substrate 10 into the interior of the substrate, and the plurality of grooves 30 are spaced apart along a direction parallel to the top surface of the substrate 10. This helps to further simplify the manufacturing process of the adapter plate and facilitates the integration of a plurality of small-sized first chips 11 within the substrate 10.

[0081] In some embodiments, such as Figure 1 , Figure 2 and Figure 3 As shown, the wiring layer includes:

[0082] A top wiring layer 21 is located on the upper surface of the adapter board, and the second chip 12 and the first chip 11 located in the top groove are both electrically connected to the top wiring layer 21.

[0083] Bottom wiring layer 22 is located on the lower surface of the adapter board. The first chip 11 located in the bottom groove is electrically connected to the bottom wiring layer 22, and the top wiring layer 21 is electrically connected to the bottom wiring layer 22.

[0084] In some embodiments, the adapter plate further includes:

[0085] A first conductive connection post 20 penetrates the substrate 10, and one end of the first conductive connection post 20 is electrically connected to the top wiring layer 21 and the other end is electrically connected to the bottom wiring layer 22.

[0086] For example, the second chip 12 is located above the upper surface of the adapter plate, the top wiring layer 21 is disposed between the second chip 12 and the substrate 10 of the adapter plate, and the bottom wiring layer 22 is located on the lower surface of the adapter plate. In one example, the top wiring layer 21 includes a top dielectric layer covering the upper surface of the adapter plate and a top high-density metal trace located inside the top dielectric layer, and the bottom wiring layer 22 includes a bottom dielectric layer covering the lower surface of the adapter plate and a bottom high-density metal trace located inside the bottom dielectric layer. The functional surface of the first chip 11 located in the bottom recess faces the bottom wiring layer 22 and is electrically connected to the bottom wiring layer 22 through the first conductive bump 13 on the first chip 11. The functional surface of the first chip 11 located in the top recess faces the top wiring layer 21 and is electrically connected to the top wiring layer 21 through the first conductive bump 13 on the first chip 11. Along a direction perpendicular to the upper surface of the adapter plate, the first conductive connection post 20 penetrates the substrate 10, and one end of the first conductive connection post 20 is electrically connected to the top high-density metal trace in the top wiring layer 21, and the other end is electrically connected to the bottom high-density metal trace in the bottom wiring layer 22. In one example, the substrate 10 includes a recessed region and a peripheral region distributed around the outer periphery of the recessed region, all of the recesses are located within the recessed region, and a plurality of the first conductive connection posts 20 are located in the peripheral region and distributed around the outer periphery of the recessed region.

[0087] In one example, a plurality of solder balls 14 are spaced apart on the surface of the bottom wiring layer 22 facing away from the substrate 10, and the solder balls 14 are electrically connected to the bottom wiring layer 22. The bottom wiring layer 22 can be electrically connected to the packaging substrate (e.g., a PCB circuit board) through the solder balls 14, so as to enable the output of signals from the bottom wiring layer 22 and the top wiring layer 21 through the solder balls 14, or to transmit control signals to the bottom wiring layer 22 and the top wiring layer 21 through the solder balls 14.

[0088] In some embodiments, the electromagnetic shielding layer 15 includes a top electromagnetic shielding layer and a bottom electromagnetic shielding layer that are independent of each other;

[0089] The top electromagnetic shielding layer covers the inner wall of the top groove and is electrically connected to the top wiring layer 21, and the bottom electromagnetic shielding layer covers the inner wall of the bottom groove and is electrically connected to the bottom wiring layer 22.

[0090] For example, the top wiring layer 21 has a top grounding line, and the bottom wiring layer 22 has a bottom grounding line. The top electromagnetic shielding layer is electrically connected to the top grounding line, meaning the top electromagnetic shielding layer is grounded through the top wiring layer 21. The bottom electromagnetic shielding layer is electrically connected to the bottom grounding line, meaning the bottom electromagnetic shielding layer is grounded through the bottom wiring layer 22. By providing a top grounding line in the top wiring layer 21 and a bottom grounding line in the bottom wiring layer 22, the grounding flexibility of the electromagnetic shielding layer 15 is improved.

[0091] In other embodiments, the electromagnetic shielding layer 15 includes a top electromagnetic shielding layer and a bottom electromagnetic shielding layer electrically connected to the top electromagnetic shielding layer;

[0092] The top electromagnetic shielding layer covers the inner wall of the top groove, and the bottom electromagnetic shielding layer covers the inner wall of the bottom groove and is electrically connected to the bottom wiring layer.

[0093] For example, the bottom wiring layer 22 has a bottom grounding line, and the top electromagnetic shielding layer is electrically connected to the top wiring layer 21. That is, the top electromagnetic shielding layer is electrically connected to the bottom grounding line in the bottom wiring layer 22 through the top wiring layer 21 and the first conductive connecting post 20. The bottom electromagnetic shielding layer is grounded through the bottom wiring layer 22. By providing the bottom grounding line only in the bottom wiring layer 22, so that both the top and bottom electromagnetic shielding layers are grounded through the bottom grounding line, the circuit structure of the top wiring layer 21 is simplified, and the design flexibility of the top wiring layer 21 is improved.

[0094] Figure 9 This is another cross-sectional schematic diagram of the electromagnetic shielding packaging structure in a specific embodiment of this utility model. Figure 10 This is a schematic diagram illustrating another relative positional relationship between the adapter board and the first chip in a specific embodiment of this utility model. In other embodiments, the electromagnetic shielding packaging structure further includes:

[0095] The second conductive connection post 70 is located within the substrate 10. One end of the second conductive connection post 70 is electrically connected to the top electromagnetic shielding layer, and the other end is electrically connected to the bottom electromagnetic shielding layer.

[0096] In some embodiments, the bottom electromagnetic shielding layer continuously covers the inner walls of the plurality of bottom grooves and the surface of the bottom wiring layer 22 between adjacent bottom grooves;

[0097] The second conductive connection post 70 extends between adjacent bottom grooves and is electrically connected to the bottom electromagnetic shielding layer located between adjacent bottom grooves.

[0098] Specifically, by providing the second conductive connection post 70 in the substrate 10, the top electromagnetic shielding layer and the bottom electromagnetic shielding layer are electrically connected through the second conductive connection post 70, thereby enabling the top electromagnetic shielding layer and the bottom electromagnetic shielding layer to be grounded together through the bottom grounding line in the bottom wiring layer 22, thus simplifying the grounding operation of the electromagnetic shielding layer 15.

[0099] In some embodiments, the electromagnetic shielding packaging structure further includes:

[0100] A first molding layer 16 is filled in the plurality of grooves 30, and the first molding layer 16 covers the surface of the electromagnetic shielding layer 15 and molds the plurality of the first chips 11.

[0101] The second molding layer 17 is located above the adapter board, and the second molding layer 17 molds the second chip 12.

[0102] For example, such as Figure 1As shown, the first molding compound 16 fills the entire groove 30 and molds the first chip 11 within the groove 30. The second molding compound 17 is located above the adapter plate and molds the second chip 12. By setting the first molding compound 16 and the second molding compound 17, not only can the first chip 11 and the second chip 12 be protected, but the strength of the adapter plate can also be enhanced, and the stress on opposite sides of the top wiring layer 21 can be balanced, reducing or even avoiding large-scale deformation of the top wiring layer 21. In one example, the material of the first molding compound 16 and the material of the second molding compound 17 are the same, for example, both the material of the first molding compound 16 and the material of the second molding compound 17 are epoxy resin molding compound.

[0103] The electromagnetic shielding packaging structure provided by this utility model forms multiple independent grooves within an adapter board, and mounts multiple first chips into these grooves. An electromagnetic shielding layer is formed within each groove, at least covering the inner wall of the groove. A wiring layer is formed on the adapter board, and a second chip is mounted onto the wiring layer. Both the first and second chips are electrically connected to the wiring layer. The electromagnetic shielding layer provides electromagnetic shielding to the grooves, enabling the integration of various types of chips, such as radio frequency chips, within the grooves. This expands the functionality and application areas of the packaging structure. The multiple discrete grooves isolate the first chips within different grooves, preventing mutual interference between first chips integrated within the adapter board. The wiring layer enables electrical connections between the second chip and the adapter board, as well as between the second chip and the first chip, eliminating the need for chip-to-chip bonding. This simplifies the manufacturing process, significantly reduces manufacturing costs, and helps reduce the overall thickness of the packaging structure, promoting miniaturization. By providing multiple independent grooves within the adapter board, and using these grooves to accommodate the first chip, combined with the wiring layer, a large number of I / O interface interconnects can be provided, making it suitable for fabricating package structures requiring a high number of I / O interfaces. This invention eliminates the need for processes such as TMV, thereby further reducing manufacturing costs and complexity.

[0104] It should be noted that the terms "comprising" and "having," and their variations, used in this utility model document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this utility model can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this utility model. In the various embodiments described above, each embodiment focuses on the differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.

[0105] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.

Claims

1. An electromagnetic shielding encapsulation structure, characterized in that, include: An adapter plate includes a substrate and a plurality of grooves located within the substrate, wherein the plurality of grooves are independent of each other; The wiring layer is located on the adapter board; Multiple first chips are respectively located in multiple grooves, and all multiple first chips are electrically connected to the wiring layer; An electromagnetic shielding layer covers the inner wall of the groove; The second chip is located above the adapter board and is electrically connected to the wiring layer.

2. The electromagnetic shielding encapsulation structure according to claim 1, characterized in that, The electromagnetic shielding layer covers the entire inner wall of the groove; or, The electromagnetic shielding layer covers the inner wall of a portion of the grooves.

3. The electromagnetic shielding encapsulation structure according to claim 1, characterized in that, Each of the first chips includes a functional surface and a back surface that are relatively distributed; The functional surface of the first chip faces the wiring layer, and the back surface of the first chip is bonded to the surface of the electromagnetic shielding layer by an adhesive layer.

4. The electromagnetic shielding encapsulation structure according to claim 1, characterized in that, The adapter board includes an upper surface and a lower surface that are oppositely distributed, and the second chip is located above the upper surface of the adapter board; The plurality of grooves are arranged at intervals along a direction parallel to the upper surface of the adapter plate.

5. The electromagnetic shielding encapsulation structure according to claim 1, characterized in that, The adapter board includes an upper surface and a lower surface that are oppositely distributed, and the second chip is located above the upper surface of the adapter board; The plurality of grooves are arranged at intervals along a direction perpendicular to the upper surface of the adapter plate.

6. The electromagnetic shielding encapsulation structure according to claim 1, characterized in that, The adapter board includes an upper surface and a lower surface that are oppositely distributed, and the second chip is located above the upper surface of the adapter board; A portion of the grooves are spaced apart along a direction parallel to the upper surface of the adapter plate, and at least two of the grooves are spaced apart along a direction perpendicular to the upper surface of the adapter plate.

7. The electromagnetic shielding encapsulation structure according to claim 6, characterized in that, A portion of the grooves are bottom grooves, and another portion of the grooves are top grooves. The bottom grooves extend from the lower surface of the adapter plate toward the interior of the adapter plate, and a plurality of the bottom grooves are spaced apart along a direction parallel to the upper surface of the adapter plate. The top grooves extend from the upper surface of the adapter plate toward the interior of the adapter plate.

8. The electromagnetic shielding encapsulation structure according to claim 7, characterized in that, The projection of the top groove on the upper surface of the adapter plate is greater than the projection of the bottom groove on the upper surface of the adapter plate.

9. The electromagnetic shielding encapsulation structure according to claim 7, characterized in that, The multiple top grooves are distributed one-to-one above the multiple bottom grooves, and the width of each top groove is the same as the width of its corresponding bottom groove.

10. The electromagnetic shielding packaging structure according to claim 7, characterized in that, The wiring layer includes: a top wiring layer located on the upper surface of the adapter board, wherein the second chip and the first chip located in the top groove are both electrically connected to the top wiring layer; A bottom wiring layer is located on the lower surface of the adapter board. The first chip located in the bottom groove is electrically connected to the bottom wiring layer, and the top wiring layer is electrically connected to the bottom wiring layer.

11. The electromagnetic shielding encapsulation structure according to claim 10, characterized in that, The adapter plate also includes: A first conductive connection post penetrates the substrate, with one end of the first conductive connection post electrically connected to the top wiring layer and the other end electrically connected to the bottom wiring layer.

12. The electromagnetic shielding encapsulation structure according to claim 10, characterized in that, The electromagnetic shielding layer includes a top electromagnetic shielding layer and a bottom electromagnetic shielding layer that are independent of each other; The top electromagnetic shielding layer covers the inner wall of the top groove and is electrically connected to the top wiring layer, and the bottom electromagnetic shielding layer covers the inner wall of the bottom groove and is electrically connected to the bottom wiring layer.

13. The electromagnetic shielding encapsulation structure according to claim 10, characterized in that, The electromagnetic shielding layer includes a top electromagnetic shielding layer and a bottom electromagnetic shielding layer electrically connected to the top electromagnetic shielding layer. The top electromagnetic shielding layer covers the inner wall of the top groove, and the bottom electromagnetic shielding layer covers the inner wall of the bottom groove and is electrically connected to the bottom wiring layer.

14. The electromagnetic shielding encapsulation structure according to claim 13, characterized in that, Also includes: A second conductive connection post is located within the substrate, with one end of the second conductive connection post electrically connected to the top electromagnetic shielding layer and the other end electrically connected to the bottom electromagnetic shielding layer.

15. The electromagnetic shielding encapsulation structure according to claim 14, characterized in that, The bottom electromagnetic shielding layer continuously covers the inner walls of the multiple bottom grooves and the surface of the bottom wiring layer between adjacent bottom grooves; The second conductive connection post extends between adjacent bottom grooves and is electrically connected to the bottom electromagnetic shielding layer located between adjacent bottom grooves.

16. The electromagnetic shielding encapsulation structure according to claim 1, characterized in that, Also includes: A first molding layer is filled in the plurality of said grooves, and the first molding layer covers the surface of the electromagnetic shielding layer and molds the plurality of the first chips; A second molding layer is located above the adapter board, and the second molding layer encapsulates the second chip.

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