Encapsulation carrier structure

Abstract

The utility model provides a kind of encapsulation carrier structure including glass substrate, at least one through substrate via and interconnection structure.Glass substrate has first surface and second surface relative to first surface.At least one through substrate via is through glass substrate.Interconnection structure is set on the first surface of glass substrate.Interconnection structure includes first dielectric layer, multiple conductive layers and multiple vias.Multiple conductive layers are set in first dielectric layer.Multiple vias are set in first dielectric layer and are connected between adjacent multiple conductive layers.The encapsulation carrier structure provided by the utility model has improved reliability and reduces cost.

Description

Technical Field

[0001] This utility model relates to a structure, and more particularly to a packaging carrier structure. Background Technology

[0002] 3D packaging technology utilizes silicon interposers to connect chips and components vertically, increasing packaging density and improving overall performance. As industry demands for high-performance computing increase, package sizes are gradually increasing to accommodate more electronic components for efficient operation. However, this increase in package size makes the interposer prone to warping, leading to decreased reliability and consequently impacting performance. Therefore, optimizing the packaging structure for high-performance computing while maintaining good reliability is a current priority. Utility Model Content

[0003] This invention provides a packaging carrier structure that improves reliability and reduces cost.

[0004] This invention provides a packaging carrier structure comprising a glass substrate, at least one through-substrate via, and an interconnect structure. The glass substrate has a first surface and a second surface opposite to the first surface. At least one through-substrate via penetrates the glass substrate. The interconnect structure is disposed on the first surface of the glass substrate. The interconnect structure includes a first dielectric layer, multiple conductive layers, and multiple vias. The multiple conductive layers are disposed in the first dielectric layer. The multiple vias are disposed in the first dielectric layer and connect adjacent conductive layers.

[0005] In one embodiment of the present invention, the layer closest to the glass substrate among the plurality of conductive layers includes at least one pad portion, and the at least one pad portion corresponds to and is in direct contact with at least one through-substrate via.

[0006] In one embodiment of the present invention, the width of at least one pad portion is less than the width of at least one through-substrate via.

[0007] In one embodiment of the present invention, the width of the plurality of vias on the side closer to the glass substrate is greater than the width of the plurality of vias on the side farther from the glass substrate.

[0008] In one embodiment of the present invention, the above-mentioned packaging carrier structure further includes a second dielectric layer disposed between the glass substrate and the interconnect structure, wherein at least one through-substrate via also penetrates the second dielectric layer.

[0009] In one embodiment of the present invention, the second dielectric layer is in direct contact with and bonded to the first dielectric layer.

[0010] In one embodiment of the present invention, the first dielectric layer is in direct contact with and bonded to the first surface of the glass substrate.

[0011] In one embodiment of the present invention, the above-mentioned packaging carrier structure further includes a chip disposed on the interconnect structure and electrically connected to the interconnect structure.

[0012] In one embodiment of this utility model, the contacts of the chip are in direct contact with and engaged with the corresponding vias in the interconnect structure.

[0013] In one embodiment of the present invention, the above-mentioned packaging carrier structure further includes a circuit board disposed on the second surface of the glass substrate and electrically connected to at least one through-substrate via.

[0014] Based on the above, the packaging carrier structure of this utility model uses a glass substrate as an interlayer, and attaches the interconnect structure to the glass substrate through hybrid bonding, so that one side of the glass substrate can be bonded to a chip with fine circuitry, and the other side is connected to a circuit board. In this way, the possibility of warpage in the packaging carrier structure can be reduced, production costs can be reduced, and reliability can be improved. It is also suitable for large-size packaging and can be applied to high-performance computing.

[0015] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a cross-sectional schematic diagram of a packaging carrier structure according to an embodiment of the present utility model;

[0017] Figure 2 This is a cross-sectional schematic diagram of a packaging carrier structure according to another embodiment of the present utility model;

[0018] Figures 3A to 3G This is a cross-sectional schematic diagram showing the manufacturing process of a packaging carrier structure according to an embodiment of the present invention. Detailed Implementation

[0019] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Throughout the specification, the same reference numerals denote the same components. It should be understood that when a component such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another component, it may be directly on or connected to the other component, or an intermediate component may also be present. Conversely, when a component is referred to as being "directly on" or "directly connected" to another component, no intermediate component is present. As used herein, "connection" can refer to a physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may refer to the presence of other components between the two components.

[0020] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, and / or portions should not be limited by these terms. These terms are used only to distinguish one component, part, region, layer, or portion from another. Therefore, “first component,” “part,” “region,” “layer,” or “portion” discussed below may be referred to as a second component, part, region, layer, or portion without departing from the teachings of this document.

[0021] Figure 1 This is a cross-sectional schematic diagram of a packaging carrier structure according to an embodiment of the present utility model.

[0022] Please refer to Figure 1 The encapsulation carrier structure 10 includes a glass substrate 100, a through-substrate via 102, and an interconnect structure 110. The glass substrate 100 has a first surface 100a and a second surface 100b opposite to the first surface 100a. The through-substrate via 102 penetrates the glass substrate 100. The interconnect structure 110 is disposed on the first surface 100a of the glass substrate 100. The interconnect structure 110 includes a first dielectric layer 112 and a plurality of conductive layers 114 and a plurality of vias 116 disposed in the first dielectric layer 112. The vias 116 can connect adjacent conductive layers 114.

[0023] In some embodiments, the glass substrate 100 may include a quartz glass substrate, a phosphosilicate glass substrate, a borosilicate glass substrate, a fluorosilicate glass substrate, or other suitable glass substrates, and the present invention is not limited thereto.

[0024] In some embodiments, the first dielectric layer 112 is in direct contact with and bonded to the glass substrate 100. In some embodiments, covalent bonds are formed at the interface between the first dielectric layer 112 and the glass substrate 100. In some embodiments, the material of the first dielectric layer 112 includes silicon oxide or other suitable dielectric materials, and the present invention is not limited thereto.

[0025] In some embodiments, the layer closest to the glass substrate 100 among the plurality of conductive layers 114 may include at least one pad portion 114p. The pad portion 114p is in direct contact with and engaged with the corresponding through-substrate via 102.

[0026] In some embodiments, the width W2 of the pad portion 114p may be smaller than the width W1 of the through-substrate via 102.

[0027] In some embodiments, the via 116 is tapered. In some embodiments, the width W3 of the via 116 on the side closer to the glass substrate 100 is greater than the width W4 of the via 116 on the side farther from the glass substrate 100.

[0028] In some embodiments, the width W2 of the pad portion 114p is greater than the width W3 of the via 116 on the side closest to the glass substrate 100.

[0029] In some embodiments, conductive pads 104 may be provided on the second surface 100b of the glass substrate 100. The conductive pads 104 are provided corresponding to and covering the through-substrate vias 102 to facilitate external connections of the through-substrate vias 102. In some embodiments, additional dielectric layers, conductive layers, and conductive vias (not shown) may also be formed on the second surface 100b of the glass substrate 100 to form additional interconnect structures on the second surface 100b of the glass substrate 100, similar to the aforementioned interconnect structure 110.

[0030] In some embodiments, the materials of the through-substrate via 102, conductive layer 114 and via 116 may include copper, titanium, tungsten, aluminum, tantalum, gold, silver or combinations thereof or other suitable conductive materials, and this invention is not limited thereto.

[0031] In some embodiments, the packaging carrier structure 10 further includes a chip 120 and a circuit board 130. The chip 120 is disposed on and electrically connected to the interconnect structure 110. The circuit board 130 is disposed on the second surface 100b of the glass substrate 100 and electrically connected to the through-substrate via 102.

[0032] In some embodiments, the contacts 129 of the chip 120 are in direct contact with and engaged with the corresponding vias 116 in the interconnect structure 110. The chip 120 can be electrically connected to the through-substrate vias 102 through the interconnect structure 110.

[0033] In some embodiments, the bottom surface of the chip 120 may be in direct contact with the top surface of the interconnect structure 110.

[0034] In some embodiments, chip 120 may include a logic chip, a memory chip, a system chip, or other suitable chips, and the present invention is not limited thereto. In some embodiments, chip 120 may be a three-dimensional chip composed of multiple stacked dies.

[0035] In some embodiments, the circuit board 130 includes a core layer 131, add-on structures 133 and 133', and protective layers 135 and 135'. Add-on structures 133 and 133' are respectively disposed on opposite sides of the core layer 131, and protective layers 135 and 135' are respectively disposed on the add-on structures 133 and 133'. In some embodiments, the circuit board 130 further includes a conductive via T penetrating the core layer 131 to electrically connect the add-on structures 133 and 133' located on both sides of the core layer 131. In some embodiments, each add-on structure 133 and 133' includes an interleaved stacked circuit layer 132 and a dielectric layer 134.

[0036] In some embodiments, the materials of the core layer 131 and the dielectric layer 134 may each include epoxy resin impregnated glass fiber cloth, Ajinomoto build-up film material, bismaleimide triazine resin (BT) resin or other suitable materials, and the present invention is not limited thereto.

[0037] In some embodiments, the materials of the circuit layer 132 and the conductive via T may include copper, titanium, tungsten, aluminum, tantalum, gold, silver, or combinations thereof, or other suitable conductive materials, and this invention is not limited thereto. In some embodiments, the protective layers 135 and 135' may be, for example, solder resist layers, and this invention is not limited thereto.

[0038] In some embodiments, the glass substrate 100 can be bonded to the circuit board 130 via a conductive connector 109. The conductive connector 109 can be connected between the conductive pad 104 and the topmost circuit layer 132 of the layer build-up structure 133, so that the chip 120 can be electrically connected to the circuit board 130 through the interconnect structure 110, the through-substrate via 102, and the conductive connector 109. In some embodiments, the material of the conductive connector 109 may include solder balls, metal bumps, conductive adhesive, or other suitable materials, and the present invention is not limited thereto.

[0039] In some embodiments, the circuit board 130 further includes conductive terminals 139 disposed on the side of the circuit board 130 away from the glass substrate 100 and electrically connected to the line layer 132 of the layered structure 133' to provide external connectivity of the packaging carrier structure 10. In some embodiments, the material of the conductive terminals 139 may include solder balls, metal bumps, conductive adhesive, or other suitable materials, and the present invention is not limited thereto.

[0040] In some embodiments, the circuit board 130 may be an integrated circuit board, a printed circuit board or other suitable circuit board, and the present invention is not limited thereto.

[0041] In this embodiment, the packaging carrier structure 10 uses a glass substrate 100 as an intermediary layer. The first surface 100a of the glass substrate 100 is bonded to the first dielectric layer 112 of the interconnect structure 110, and the through-substrate via 102 is bonded to the pad portion 114p of the interconnect structure 110. Therefore, through the interconnect structure 110 disposed on the glass substrate 100 and the through-substrate via 102 in the glass substrate 100, the chip 120 can be connected to the circuit board 130, thereby reducing the possibility of warpage, reducing production costs, improving reliability, and being suitable for large-size packaging and application in high-performance computing.

[0042] Figure 2 This is a cross-sectional schematic diagram of a packaging carrier structure according to another embodiment of the present invention. It must be noted here that... Figure 2 The embodiments follow Figure 1 The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0043] Please refer to Figure 2 , Figure 2 The encapsulation carrier structure 20 and Figure 1 The main difference between the encapsulation carrier structure 10 and the encapsulation carrier structure 20 is that the encapsulation carrier structure 20 also includes a second dielectric layer 106. The second dielectric layer 106 is disposed on the first surface 100a of the glass substrate 100 and located between the glass substrate 100 and the interconnect structure 110 to facilitate the bonding between the glass substrate 100 and the interconnect structure 110.

[0044] In some embodiments, the through-substrate via 102 also penetrates the second dielectric layer 106. That is, the top surface of the through-substrate via 102 may be higher than the first surface 100a of the glass substrate 100. In some embodiments, the top surface of the through-substrate via 102 may be substantially coplanar with the top surface of the second dielectric layer 106.

[0045] In some embodiments, the second dielectric layer 106 is in direct contact with and bonded to the first dielectric layer 112. In some embodiments, covalent bonds are formed at the interface between the second dielectric layer 106 and the first dielectric layer 112. In some embodiments, the material of the second dielectric layer 106 is the same as the material of the first dielectric layer 112. The material of the second dielectric layer 106 may include silicon oxide or other suitable dielectric materials, and the present invention is not limited thereto.

[0046] In this embodiment, the packaging carrier structure 20 uses a glass substrate 100 as an intermediary layer. The first surface 100a of the glass substrate 100 is bonded to the first dielectric layer 112 of the interconnect structure 110 through the second dielectric layer 106, and the through-substrate via 102 is bonded to the pad portion 114p of the interconnect structure 110. Therefore, through the interconnect structure 110 disposed on the glass substrate 100 and the through-substrate via 102 in the glass substrate 100, the chip 120 can be connected to the circuit board 130, thereby reducing the possibility of warpage, reducing production costs, improving reliability, and being suitable for large-size packaging and application in high-performance computing.

[0047] Figures 3A to 3G This is a cross-sectional schematic diagram illustrating the manufacturing process of a packaging carrier structure according to an embodiment of the present invention. It must be noted that... Figures 3A to 3G The embodiments follow Figure 1 The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0048] Please refer to Figure 3A A temporary carrier board 101 is provided, and an interconnect structure 110 is formed on the temporary carrier board 101. The conductive layer 114 and via 116 in the interconnect structure 110 can be formed by a dual damascene process, but this invention is not limited thereto. For example, a dielectric material layer (not shown) can be formed on the temporary carrier board 101 first, and then the dielectric material layer can be patterned by photolithography and etching processes to form openings corresponding to the patterns of the vias and openings corresponding to the patterns of the conductive layers (not shown). A conductive material layer (not shown) is formed in the openings and a planarization process (e.g., chemical mechanical polishing, mechanical polishing, or the like) is performed to form a first conductive layer 114 and via 116 in the openings, and the top surface of the conductive layer 114 is coplanar with the dielectric material layer. The above steps are repeated until a predetermined number of conductive layers are formed, thereby completing the fabrication of the interconnect structure 110. It can be seen that the dielectric layer 112 is formed by stacking multiple dielectric material layers.

[0049] Please refer to Figure 3B A glass substrate 100 is provided, and a through-substrate via 102 is formed in the glass substrate 100. For example, a through-hole passing through a first surface 100a and a second surface 100b of the glass substrate 100 can be formed in the glass substrate 100 by a drilling process, and then a conductive material is filled into the through-hole to form the through-substrate via 102.

[0050] In some embodiments, before forming the through-hole through the glass substrate 100, a second dielectric layer (not shown, but referenced) may be formed on the first surface 100a of the glass substrate 100. Figure 2 Then, a drilling process is performed to make the through hole penetrate the glass substrate 100 and the second dielectric layer.

[0051] In some embodiments, after the conductive material is formed, a planarization process (e.g., chemical mechanical polishing, mechanical polishing, or the like) may be performed to remove excess conductive material on the first surface 100a and the second surface 100b of the glass substrate 100, and to make one end of the through-substrate via 102 coplanar with the first surface 100a (or the top surface of the second dielectric layer, if any) of the glass substrate 100, and the other end of the through-substrate via 102 coplanar with the second surface 100b of the glass substrate 100.

[0052] Please refer to Figure 3C Interconnect structure 110 is bonded to glass substrate 100 via hybrid bonding. For example, interconnect structure 110 can face the first surface 100a of glass substrate 100, and the pad portion 114p of interconnect structure 110 can be correspondingly disposed with a through-substrate via 102 in glass substrate 100, such that the pad portion 114p and the through-substrate via 102 are metal-to-metal (e.g., copper-to-copper) bonded. The dielectric layer 112 of interconnect structure 110 can be dielectric-to-dielectric bonded with the first surface 100a (or the top surface of the second dielectric layer, if any) of glass substrate 100 to form covalent bonds at the interface between dielectric layer 112 and glass substrate 100 (or the second dielectric layer, if any). In this way, glass substrate 100 and interconnect structure 110 can be well bonded, allowing fine circuitry to be formed on glass substrate 100 for subsequent connection to a chip. Furthermore, since the interconnect structure 110 is formed independently and then attached to the glass substrate 100 after formation, the possibility of damage or breakage of the glass substrate 100 during the process can be reduced.

[0053] Please refer to Figure 3D A conductive pad 104 is formed on the second surface 100b of the glass substrate 100, and the conductive pad 104 covers one end of the through-hole 102 in the substrate.

[0054] Please refer to Figure 3E The temporary carrier plate 101 is then peeled off.

[0055] Please refer to Figure 3F The chip 120 is mounted on the interconnect structure 110. For example, the contact 129 of the chip 120 can be engaged with the corresponding via 116 in the interconnect structure 110 via metal-to-metal (e.g., copper-to-copper) bonding.

[0056] Then, please refer to Figure 1 The glass substrate 100 is mounted on the circuit board 130. For example, the glass substrate 100 can be bonded to the corresponding line layer 132 in the circuit board 130 via a conductive connector 109.

[0057] In some embodiments, conductive terminals 139 may be formed on the side of the circuit board 130 away from the glass substrate 100.

[0058] The embodiment described above involves first mounting the chip 120 on the glass substrate 100, and then bonding the glass substrate 100 carrying the chip 120 to the circuit board 130. However, this invention does not limit the mounting order of the chip 120 and the circuit board 130. In other embodiments, such as Figure 3G and Figure 1 As shown, the glass substrate 100 can be first mounted on the circuit board 130, and then the chip 120 can be mounted on the glass substrate 100.

[0059] Based on the above, the manufacturing of the encapsulation carrier structure 10 can be roughly completed.

[0060] In summary, the packaging carrier structure of this invention uses a glass substrate as an interlayer and attaches the interconnect structure to the glass substrate through hybrid bonding. This allows one side of the glass substrate to be bonded to a chip with fine circuitry, while the other side is connected to a circuit board. This reduces the possibility of warpage in the packaging carrier structure, lowers production costs, and improves reliability. Furthermore, it is suitable for large-size packaging and can be applied to high-performance computing.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A packaging carrier structure, characterized in that, include: A glass substrate having a first surface and a second surface relative to the first surface; At least one through-substrate via penetrating the glass substrate; as well as An interconnect structure is disposed on the first surface of the glass substrate, wherein the interconnect structure includes: First dielectric layer; Multiple conductive layers are disposed in the first dielectric layer; and Multiple vias are disposed in the first dielectric layer and connected between adjacent conductive layers.

2. The encapsulation carrier structure according to claim 1, characterized in that, The layer closest to the glass substrate among the plurality of conductive layers includes at least one pad portion, which corresponds to and is in direct contact with the at least one through-substrate via.

3. The encapsulation carrier structure according to claim 2, characterized in that, The width of the at least one pad portion is less than the width of the at least one through-substrate via.

4. The encapsulation carrier structure according to claim 1, characterized in that, The width of the plurality of vias on the side closer to the glass substrate is greater than the width of the plurality of vias on the side farther from the glass substrate.

5. The encapsulation carrier structure according to claim 1, characterized in that, Also includes: A second dielectric layer is disposed between the glass substrate and the interconnect structure, wherein at least one through-substrate via also penetrates the second dielectric layer.

6. The encapsulation carrier structure according to claim 5, characterized in that, The second dielectric layer is in direct contact with and bonded to the first dielectric layer.

7. The encapsulation carrier structure according to claim 1, characterized in that, The first dielectric layer is in direct contact with and bonded to the first surface of the glass substrate.

8. The encapsulation carrier structure according to claim 1, characterized in that, Also includes: The chip is disposed on the interconnect structure and electrically connected to the interconnect structure.

9. The encapsulation carrier structure according to claim 8, characterized in that, The chip's contacts are in direct contact with and engaged with the corresponding vias in the interconnect structure.

10. The encapsulation carrier structure according to claim 1, characterized in that, Also includes: A circuit board is disposed on the second surface of the glass substrate and electrically connected to the at least one through-substrate via.

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