A reset circuit

Abstract

The utility model discloses a reset circuit, including reset management chip, power monitoring module and RC reset module, reset management chip is supplied by power voltage, power monitoring module provides input voltage for reset management chip, triggers power failure signal when input voltage is lower than the working voltage of reset management chip, and supplies power for the external circuit and DSP connected with RC reset module, RC reset module includes manual reset unit, and manual reset unit at least includes switch button S1 and diode group, the first end of switch button S1, the positive pole of diode group and the third pin GND of reset management chip are all grounded, and the second end of switch button S1 is connected with the negative pole of diode group in reset management chip. Through reset management chip real -time monitoring the state of input voltage, and triggers power failure signal in time when power supply is abnormal, carries out automatic and / or manual reset processing procedure, effectively avoids the influence circuit normal power supply because of power failure, enhances the anti -interference performance of circuit.

Description

Technical Field

[0001] This utility model belongs to the field of circuit design technology, and in particular relates to a reset circuit. Background Technology

[0002] In embedded control systems and microprocessor applications, the power-on reset (POR) circuit is a crucial module for ensuring reliable startup and stable operation of the microcontroller. Its core function is to generate a valid reset signal during system power-on, initializing the microcontroller's internal registers, state machine, and peripheral modules to a defined state, thereby preventing program crashes or logic errors caused by unstable power supply voltage. Furthermore, during operation, if the power supply voltage drops due to abnormal interference or sudden load changes (such as voltage spikes or brief power outages), the reset circuit must promptly detect and trigger a reset operation to prevent the system from entering unpredictable states.

[0003] However, traditional power-on reset circuits only include an automatic reset circuit. If the automatic reset circuit malfunctions or malfunctions, the reset operation cannot be performed. In this case, it is impossible to determine whether the fault is caused by the automatic reset circuit, an abnormal power supply voltage, or a hardware failure. Troubleshooting is difficult and time-consuming. Therefore, designing a reset circuit is an important technical problem that those skilled in the art need to solve. Utility Model Content

[0004] The purpose of this invention is to solve the aforementioned problems in the prior art and to provide a reset circuit.

[0005] The objective of this utility model is achieved through the following technical solution:

[0006] A reset circuit includes a reset management chip, a power monitoring module, and an RC reset module. The reset management chip is powered by a power supply voltage. The power monitoring module provides an input voltage to the reset management chip. When the input voltage is lower than the operating voltage of the reset management chip, a power fault signal is triggered. The power supply voltage drives the RC reset module to operate, entering a reset program to power external circuits and a DSP connected to the RC reset module. The RC reset module includes an automatic reset unit and a manual reset unit. The input voltage, after being processed by the reset management chip, is output from the automatic reset unit to power external circuits and the DSP. The manual reset unit includes at least a switch button S1 and a diode group. The first terminal of the switch button S1, the positive terminal of the diode group, and the third pin GND of the reset management chip are all grounded. The second terminal of the switch button S1 and the negative terminal of the diode group are connected to the first pin (non-MR) and the fifth pin (non-PFO) of the reset management chip.

[0007] Preferably, the power supply voltage is 5V, and a resistor R1 is provided at the output terminal of the power supply voltage. A capacitor C1 and the second pin VCC of the reset management chip are connected in parallel at the output terminal of the resistor R1; the other end of the capacitor C1 is grounded.

[0008] Preferably, the output terminal of the power supply voltage is further provided with a resistor R4, which is connected in parallel with the resistor R1; the output terminal of the resistor R4 is connected in parallel with the eighth pin RESET of the reset management chip and is electrically connected to the RESET_HIGH terminal.

[0009] Preferably, the power monitoring module includes a power supply voltage VDD, a resistor R2 connected to the output terminal of the power supply voltage VDD, a resistor R3, a capacitor C2, and the fourth pin PFI of the reset management chip connected in parallel at the output terminal of the resistor R2; the input voltage is the voltage on the fourth pin PFI; and the output terminals of the resistor R3 and the capacitor C2 are grounded.

[0010] Preferably, the automatic reset unit includes the RESET_HIGH terminal and the non-RESET_LOW terminal; the output terminal of the non-RESET terminal of the seventh pin of the reset management chip is connected to a resistor R5, and the output terminal of the resistor R5 is connected in parallel with the non-RESET_LOW terminal, the resistor R6, and the capacitor C3; the output terminals of the resistor R6 and the capacitor C3 are grounded.

[0011] Preferably, the manual reset unit further includes a capacitor C4 and a resistor R7; the first ends of the capacitor C4 and the resistor R7 are connected to the second end of the switch button S1, and the first ends of the capacitor C4 and the resistor R7 are connected to the negative terminal of the diode group.

[0012] Preferably, the diode group includes diode one, diode two, and diode DTVS1; the positive terminals of diode one and diode DTVS1 are connected in parallel to the positive terminal of the switch button S1, the negative terminal of diode one is connected to a wire and the positive terminal of diode two, and the negative terminals of diode DTVS1 and diode two are both connected to the second terminals of capacitor C4 and resistor R7; the other end of the wire is connected to the second terminal of the switch button S1.

[0013] The advantages of this utility model's technical solution are mainly reflected in:

[0014] The reset management chip monitors the input voltage status in real time and triggers a power fault signal when the input voltage is lower than the operating voltage, performing automatic and / or manual reset procedures. This effectively prevents power failures from affecting the normal power supply of the circuit, provides time for maintenance, and enhances the circuit's anti-interference performance.

[0015] By sequentially activating the automatic reset procedure and the manual reset procedure, the cause of circuit faults can be identified, thereby improving work effectiveness and efficiency.

[0016] The reset circuit disclosed in this utility model can still provide normal power to the reset management chip when the voltage is abnormal or the power supply is unstable due to environmental or external interference, such as temperature, EMI interference, or abnormal load, during normal operation, thereby reducing the adverse effects on the circuit or the reset management chip.

[0017] The diode array suppresses transient voltages and prevents reverse current flow, ensuring unidirectional signal output. Meanwhile, resistor R7 and capacitor C4 extend the reset time, suppressing noise interference at the reset signal edge and improving the circuit's anti-interference performance. Attached Figure Description

[0018] Figure 1 Circuit diagram of a preferred embodiment of this utility model;

[0019] Figure 2 : Internal structure diagram of the reset management chip in a preferred embodiment of this utility model. Detailed Implementation

[0020] The purpose, advantages, and features of this utility model will be illustrated and explained through the following non-limiting description of preferred embodiments. These embodiments are merely typical examples of applying the technical solutions of this utility model, and all technical solutions formed by equivalent substitutions or equivalent transformations fall within the scope of protection claimed by this utility model.

[0021] In the description of the solution, it should be noted that the terms "center," "upper," "lower," "left," "right," "front," "rear," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience and simplification of description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Also, in the description of the solution, with the operator as a reference, the direction closer to the operator is the proximal end, and the direction farther from the operator is the distal end.

[0022] like Figure 1As shown, this utility model discloses a reset circuit, including a reset management chip 1, a power monitoring module 2, and an RC reset module 3. The reset management chip 1 is powered by a power supply voltage. Preferably, the power supply voltage is designed to be 5V, but in other embodiments, the power supply voltage can be adjusted as needed, and is not limited here. Specifically, a resistor R1 is provided at the output terminal of the power supply voltage, and a capacitor C1 and the second pin VCC of the reset management chip 1 are connected in parallel at the output terminal of the resistor R1; that is, the power supply voltage is divided to power the reset management chip 1. Furthermore, the other end of the capacitor C1 is grounded, and the capacitor C1 begins to charge after the power supply voltage is supplied. If the power supply voltage cannot be supplied due to power failure or circuit damage, it can be supplied through the capacitor C1 to ensure that the circuit can be used normally for a period of time.

[0023] Furthermore, a resistor R4 is provided at the output terminal of the power supply voltage, that is, resistor R4 is connected in parallel with resistor R1. The output terminal of resistor R4 is connected in parallel with the eighth pin RESET of the reset management chip 1, and is electrically connected to the RESET_HIGH terminal. The power supply voltage supplies power to the RESET_HIGH and RESET_LOW terminals, ensuring that the external circuits and DSP connected to them work normally.

[0024] Furthermore, the power monitoring module 2 includes a supply voltage VDD, a resistor R2 connected to the output terminal of the supply voltage VDD, and a resistor R3, a capacitor C2, and the fourth pin PFI of the reset management chip 1 connected in parallel at the output terminal of the resistor R2. The input voltage is the voltage on the fourth pin PFI. That is, the power monitoring module 2 provides an input voltage to the fourth pin PFI of the reset management chip 1, and after the input voltage enters the reset management chip 1, its built-in comparator compares the input voltage with the operating voltage of the reset management chip 1. The operating voltage in this invention is preferably 1.3V, but the value of this operating voltage can also be other values ​​in other embodiments, which are adjusted according to application requirements and will not be elaborated here. The output terminals of the resistor R3 and the capacitor C2 are grounded.

[0025] Furthermore, when the input voltage, i.e., the voltage on the fourth pin PFI, is higher than the operating voltage, the RC reset module 3 is not triggered; that is, the RC reset module 3 is not enabled at this time, and the circuit is powered according to the normal procedure. When the input voltage is lower than the operating voltage of the reset management chip 1, a power fault signal is triggered, and the RC reset module 3 is driven by the power supply voltage to enter the reset procedure. At this time, the power supply voltage supplies power to the external circuit and DSP connected to the RC reset module 3. Therefore, the reset circuit disclosed in this utility model can still provide normal power to the reset management chip when the voltage is abnormal or the power supply is unstable due to environmental or external interference, such as temperature effects, EMI interference, abnormal load, etc., during normal operation, reducing the adverse effects on the circuit or the reset management chip.

[0026] like Figure 1 As shown, the RC reset module 3 includes an automatic reset unit 31 and a manual reset unit 32. Specifically, the input voltage, after being processed by the reset management chip 1, is output from the eighth pin (RESET) and the seventh pin (Non-RESET), and supplies power to the external circuitry and DSP on the automatic reset unit 31. The external circuitry is connected to the RESET_HIGH terminal, and the DSP is connected to the Non-RESET_LOW terminal.

[0027] Specifically, the automatic reset unit 31 includes the RESET_HIGH terminal and non-RESET_LOW terminals. The input terminal of the RESET_HIGH terminal is connected in parallel with the eighth pin RESET of the reset management chip 1 and the power supply voltage. When the input voltage, i.e., the voltage on the fourth pin PFI, is higher than the operating voltage, the power supply voltage powers the external circuit and DSP, and the RC reset module is not activated at this time. When the input voltage, i.e., the voltage on the fourth pin PFI, is lower than the operating voltage, the power supply voltage powers the external circuit and DSP, and a circuit fault signal is triggered. That is, the fifth pin (non-PFO) of the reset management chip 1 sends a power fault signal to the first pin (non-MR), thereby activating the RC reset module and entering the reset processing procedure.

[0028] The output terminal of the seventh pin of the reset management chip 1 (non-RESET) is connected to a resistor R5. The output terminal of the resistor R5 is connected in parallel with the non-RESET_LOW, resistor R6, and capacitor C3. The output terminals of resistor R6 and capacitor C3 are grounded.

[0029] like Figure 1 and Figure 2As shown, after entering the reset process, the automatic reset process is activated first. At this time, the seventh pin (non-RESET) and the eighth pin (RESET) of the reset management chip 1 output to the DSP and the external circuit respectively. The power supply voltage supplies power to the RESET_HIGH terminal via resistor R4, and to resistors R5, R6, capacitor C3, and the non-RESET_LOW terminal respectively. During the power supply to the non-RESET_LOW terminal, capacitor C3 is gradually charged, and the DSP input terminal is pulled low. At this time, the low level is active, and the system remains in the reset state until capacitor C3 is fully charged. After the voltage at the DSP input terminal gradually rises to the operating voltage of the reset chip 1, the system exits the reset state. The reset pulse width is determined by capacitor C3, which prolongs the reset time and effectively avoids reset caused by instantaneous voltage or external interference, improving the circuit's anti-interference performance and operational stability.

[0030] When the automatic reset process fails to reset the circuit, a manual reset process can be activated; that is, a manual reset unit. Specifically, the manual reset unit 32 includes at least a switch button S1 and a diode group. The first terminal of the switch button S1, the positive terminal of the diode group, and the third pin GND of the reset management chip 1 are all grounded; the second terminal of the switch button S1 and the negative terminal of the diode group are connected to the first pin (non-MR) and the fifth pin (non-PFO) of the reset management chip 1. Further, the manual reset unit also includes a capacitor C4 and a resistor R7; the first terminals of the capacitor C4 and the resistor R7 are connected to the second terminal of the switch button S1, and the first terminals of the capacitor C4 and the resistor R7 are connected to the negative terminal of the diode group.

[0031] Since a negative voltage may be generated momentarily when the switch button S1 is manually pressed and released, this invention includes a diode group in the manual reset unit. The diode group clamps the voltage of the first pin (non-MR) and the fifth pin (non-PFO) of the reset management chip 1 within a safe voltage range, effectively preventing the reset management chip 1 from burning out and improving circuit safety and lifespan. The diode group also ensures consistent transient voltage, preventing reverse current flow and guaranteeing unidirectional signal output. Simultaneously, resistor R7 and capacitor C4 extend the reset time, suppressing noise interference at the reset signal edge and improving the circuit's anti-interference performance.

[0032] Furthermore, the diode group includes diode 321, diode 322, and diode DTVS1. The anodes of diodes 321 and DTVS1 are connected in parallel to the anode of the switch button S1. The cathode of diode 321 is connected to a wire and the anode of diode 322. The cathodes of both diodes DTVS1 and 322 are connected to the second terminals of capacitor C4 and resistor R7. The other end of the wire is connected to the second terminal of the switch button S1. When a negative voltage is generated, diode 322 short-circuits, simultaneously charging capacitor C4. After power-off, diode 322 rapidly discharges capacitor C4 for the next use of the circuit.

[0033] The working process of this utility model is briefly described below:

[0034] S1, the 5V power supply provides power to the reset management chip 1.

[0035] S2, power monitoring module 2 is activated. The supply voltage VDD in power monitoring module 2 provides the input voltage to the fourth pin PFI of the reset management chip 1. Specifically, the supply voltage VDD is the output current and voltage of resistor R2. Only the current and voltage of resistor R2 are divided by resistor R3, capacitor C2, and the fourth pin PFI. The current and voltage passing through resistor R3 and capacitor C2 flow to the ground pin and supply power to capacitor C2. The fourth pin PFI receives the divided input voltage.

[0036] S3, the comparator built into the reset management chip 1 tests whether the input voltage is lower than the operating voltage of the reset management chip 1; if so, proceed to step S4, otherwise the RC reset module 3 is not enabled.

[0037] S4, the automatic reset process is initiated. The fifth pin (non-PFO) of the reset management chip 1 sends a power fault signal to the first pin (non-MR). Simultaneously, the RC reset module 3 is activated, entering the reset procedure. At this time, the power supply voltage continues to power the reset management chip 1. After processing by the reset management chip 1, its seventh pin (non-RESET) and eighth pin (RESET) output voltage to the automatic reset unit 31 in the RC reset module 3. This voltage is used for resetting external circuits and the DSP connected to the RC reset module 3.

[0038] S4.1, the voltage output from the non-RESET pin is divided by resistor R5 and fed into resistor R6, capacitor C3, and the non-RESET_LOW terminal, supplying power to the DSP connected to the non-RESET_LOW terminal. During this process, capacitor C3 charges, pulling down the voltage at the output of resistor R5, keeping the system in a reset state until capacitor C3 is fully charged, at which point the voltage at the output of resistor R5 rises to the operating voltage, and the system exits the reset state.

[0039] S4.2 The voltage output via the eighth pin RESET is combined with the power supply voltage and output to the RESET_HIGH terminal, without powering any external circuit connected to the RESET_HIGH terminal.

[0040] S5, activate the manual reset unit 32 in the RC reset module 3, press the switch button S1 to keep the pin voltage on the first pin (non-MR) of the reset management chip 1 connected to the manual reset unit 32 within the safe voltage range, and at the same time enable the automatic reset unit 31.

[0041] Steps S4 and S5 can be performed simultaneously. If the circuit still fails to restore power after step S5 is initiated, it indicates a hardware fault in the circuit. In this case, maintenance personnel should be notified to perform emergency circuit repairs. This invention features a simple overall circuit structure. The use of capacitors and resistors to construct a delay structure enhances the reliability and anti-interference capability of the circuit. Furthermore, capacitors C2, C3, and C4 serve as multi-stage decoupling capacitors, extending the reset time, suppressing noise at the reset signal edge, and filtering to prevent interference, thus ensuring a clean reset signal.

[0042] This utility model has many other embodiments. All technical solutions formed by equivalent transformation or equivalent transformation fall within the protection scope of this utility model.

Claims

1. A reset circuit, characterized in that: The system includes a reset management chip (1), a power monitoring module (2), and an RC reset module (3). The reset management chip (1) is powered by a power supply voltage. The power monitoring module (2) provides an input voltage to the reset management chip (1). When the input voltage is lower than the operating voltage of the reset management chip (1), a power fault signal is triggered. The RC reset module (3) is driven by the power supply voltage to enter the reset program and provide power to the external circuits and DSP connected to the RC reset module (3). The RC reset module (3) includes an automatic reset unit (31) and a manual reset unit (32). The input voltage is processed by the reset management chip (1) and output from the automatic reset unit (31) to provide power to the external circuits and DSP. The manual reset unit (32) includes at least a switch button S1 and a diode group. The first end of the switch button S1, the positive terminal of the diode group, and the third pin GND of the reset management chip (1) are all grounded. The second end of the switch button S1 and the negative terminal of the diode group are connected to the first pin (non-MR) and the fifth pin (non-PFO) of the reset management chip (1).

2. The reset circuit according to claim 1, characterized in that: The power supply voltage is 5V. A resistor R1 is provided at the output terminal of the power supply voltage. A capacitor C1 and the second pin VCC of the reset management chip (1) are connected in parallel at the output terminal of the resistor R1. The other end of the capacitor C1 is grounded.

3. A reset circuit according to claim 2, characterized in that: The output terminal of the power supply voltage is also connected to a resistor R4, which is set in parallel with the resistor R1; the output terminal of the resistor R4 is connected in parallel with the eighth pin RESET of the reset management chip (1) and is electrically connected to the RESET_HIGH terminal.

4. A reset circuit according to claim 1, characterized in that: The power monitoring module (2) includes a power supply voltage VDD, a resistor R2 connected to the output terminal of the power supply voltage VDD, a resistor R3, a capacitor C2 and the fourth pin PFI of the reset management chip (1) connected in parallel at the output terminal of the resistor R2; the input voltage is the voltage on the fourth pin PFI; the output terminals of the resistor R3 and the capacitor C2 are grounded.

5. A reset circuit according to claim 3, characterized in that: The automatic reset unit (31) includes the RESET_HIGH terminal and the non-RESET_LOW terminal; the output terminal of the seventh pin of the reset management chip (1) is connected to a resistor R5, and the output terminal of the resistor R5 is connected in parallel with the non-RESET_LOW terminal, the resistor R6 and the capacitor C3; the output terminals of the resistor R6 and the capacitor C3 are grounded.

6. A reset circuit according to claim 1, characterized in that: The manual reset unit (32) further includes a capacitor C4 and a resistor R7; the first end of the capacitor C4 and the resistor R7 is connected to the second end of the switch button S1, and the first end of the capacitor C4 and the resistor R7 is connected to the negative terminal of the diode group.

7. A reset circuit according to claim 6, characterized in that: The diode group includes diode one (321), diode two (322) and diode DTVS1; the positive terminals of diode one (321) and diode DTVS1 are connected in parallel to the positive terminal of the switch button S1, the negative terminal of diode one (321) is connected to a wire and the positive terminal of diode two (322), and the negative terminals of diode DTVS1 and diode two (322) are both connected to the second terminals of capacitor C4 and resistor R7; the other end of the wire is connected to the second terminal of the switch button S1.

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