TOSA and ROSA multiplexing power-on test device

Abstract

The utility model relates to the field of optical communication especially, and it is a kind of TOSA and ROSA multiplexing power-on testing device, for connecting the interface circuit of ROSA under test and main control circuit connection, main control circuit is connected with the interface circuit for connecting TOSA under test, main control circuit is connected with host computer through USB interface, power supply circuit is connected with main control circuit, for connecting the interface circuit for connecting TOSA under test, for connecting the interface circuit for connecting ROSA under test, USB interface respectively.The utility model has the advantages that: power-on test board has for connecting the interface circuit for connecting ROSA under test and for connecting the interface circuit for connecting TOSA under test, realize the original in each independent test station under test optical transmitting component TOSA and under test optical receiving component ROSA are connected with power-on test board, so that test equipment and instrument resources can realize sharing, reduce floor area, realize resource efficient integration and utilization, avoid the problem of resource waste caused by independent test station.

Description

Technical Field

[0001] This utility model relates to the field of optical communication, and in particular to a TOSA and ROSA multiplexing power-on test device. Background Technology

[0002] In the production and testing phase of high-speed lasers, the testing of TOSA (Optical Transmitter Component) and ROSA (Optical Receiving Component) is crucial. Currently, the following issues urgently need to be addressed in the testing process:

[0003] 1. Independent testing stations lead to resource waste.

[0004] In the high-speed laser production process, TOSA and ROSA conduct tests at their respective independent testing stations. This independent testing layout prevents the sharing of various testing equipment, instruments, and other resources. Not only is the cost of setting up the testing environment high, but the large area required also puts pressure on the planning of the production site. At the same time, due to the independent nature of each station, the utilization efficiency of instrument resources is low, which drags down production efficiency and makes it difficult to meet the demand for efficient testing in large-scale production.

[0005] 2. The messy external signal cables have many drawbacks.

[0006] During the testing of the TOSA (Optical Transmitter Component) and ROSA (Optical Receiving Component), the power board is used to drive the internal laser. During the testing process, the connection between the product components and the instrument involves multiple sets of messy external interconnection signal lines. The messy cables increase the complexity of the test personnel's operation and increase the manpower and cost of daily maintenance. On the other hand, wiring sequence problems can easily cause false triggers, which may damage the components, disrupt the stability of the test station, and lead to frequent abnormal situations in the production testing process, disrupting the overall delivery rhythm and delaying the product delivery time.

[0007] 3. Limited MCU performance increases maintenance difficulty.

[0008] In TOSA and ROSA testing, the MCU plays a dual role in interacting with the host computer and driving the internal laser. However, due to the limitations of the MCU's driving capabilities, the MCU often responds slowly, which directly leads to delays in the testing process and reduces production efficiency. Moreover, when faced with a large amount of data processing, the MCU cannot respond in time, which can easily result in untimely test results.

[0009] 4. Existing testing systems have obvious limitations.

[0010] Currently, in TOSA and ROSA testing, only TOSA testing or only RSOA testing can be performed in the same time domain and spatial domain, and TOSA and ROSA cannot be tested simultaneously in the same spatial domain.

[0011] In summary, there is an urgent need to develop a new type of high-speed laser testing device that can overcome the above-mentioned defects, so as to improve testing efficiency, reduce costs, enhance stability, and meet the urgent needs of large-scale production of high-speed lasers. Utility Model Content

[0012] The purpose of this invention is to provide a TOSA and ROSA multiplexed power-on test device that integrates test stations, enabling simultaneous testing of TOSA and ROSA in the same spatial domain, optimizing signal connection methods, simplifying operation procedures, improving test efficiency, and ensuring smooth test processes.

[0013] To achieve the above objectives, this utility model employs the following technical solution:

[0014] A TOSA and ROSA multiplexed power-on test device includes a power-on test board. The power-on test board includes a main control circuit, a power supply circuit, an interface circuit for connecting the TOSA under test, and an interface circuit for connecting the ROSA under test. The interface circuit for connecting the ROSA under test is connected to the main control circuit. The main control circuit is connected to the interface circuit for connecting the TOSA under test. The main control circuit is connected to a host computer via a USB interface. The power supply circuit is connected to the main control circuit, the interface circuit for connecting the TOSA under test, the interface circuit for connecting the ROSA under test, and the USB interface.

[0015] The main control circuit includes an OPT_MCU circuit and a COM_MCU circuit. The OPT_MCU circuit and the COM_MCU circuit are connected. The interface circuit for connecting the ROSA under test is connected to the OPT_MCU circuit and the COM_MCU circuit through ports, respectively. The interface circuit for connecting the TOSA under test is connected to the OPT_MCU circuit and the COM_MCU circuit through ports, respectively.

[0016] The OPT_MCU circuit includes the OPT_MCU chip, which uses the DS4834.

[0017] The COM_MCU circuit includes a COM_MCU chip, which is a C8051F320.

[0018] Pins 13 and 14 of the OPT_MCU chip are connected to pins 13 and 14 of the COM_MCU chip, respectively; pin 8 of the OPT_MCU chip is connected to pin 23 of the COM_MCU chip; pin 18 of the OPT_MCU chip is connected to pin 15 of the COM_MCU chip; pin 19 of the OPT_MCU chip is connected to pin 20 of the COM_MCU chip; pin 9 of the OPT_MCU chip is connected to pin 22 of the COM_MCU chip; and pin 10 of the OPT_MCU chip is connected to pin 31 of the COM_MCU chip.

[0019] The USB interface is a TYPE-B USB interface, and pins 2 and 3 of the USB interface are connected to pins 5 and 4 of the COM_MCU chip, respectively.

[0020] The interface circuit used to connect to the TOSA under test includes a TEC control circuit, an E modulation circuit, a BIAS-TEE circuit, and an AMP circuit. The input terminal of the TEC control circuit is connected to the output terminal 1 of the OPT_MCU circuit via a port. The output terminal of the TEC control circuit is connected to the input terminal 1 of the COM_MCU circuit via a port. The input terminal 1 of the E modulation circuit is connected to the output terminal 2 of the OPT_MCU circuit via a port. The output terminal of the E modulation circuit is connected to the input terminal 2 of the COM_MCU circuit via a port. The input terminal 2 of the E modulation circuit is connected to the output terminal of the BIAS-TEE circuit via a port. The input terminal of the BIAS-TEE circuit is connected to the output terminal of the AMP circuit via a port. The input terminal of the AMP circuit is connected to the output terminal 3 of the OPT_MCU circuit via a port.

[0021] The TEC control circuit includes a TEC control chip for connecting to the laser's emitting component TOSA. Pin D4 of the TEC control chip is connected to pin 7 of the OPT_MCU chip, pin C3 of the TEC control chip is connected to pin 19 of the OPT_MCU chip, pin C4 of the TEC control chip is connected to pin 5 of the OPT_MCU chip, and pin C3 of the TEC control chip is connected to pin 20 of the COM_MCU chip. The TEC control chip uses an ADN8833.

[0022] The E modulation circuit includes an E modulation chip for connecting the optical transmitter component under test (TOSA) and the bit error rate meter (BIT_ERRORRATE_TESTER); the BIAS-TEE circuit includes BIAS-TEE circuit one and BIAS-TEE circuit two. One end of BIAS-TEE circuit two is connected to the TXSDOP pin of the E modulation chip. One end of BIAS-TEE circuit one is connected in series with a capacitor C34 and a resistor R18. The other end of the resistor R18 is connected to one end of BIAS-TEE circuit two.

[0023] Pins 26 and 25 of the E modulation chip are connected to pins 3 and 32 of the OPT_MCU chip, respectively. Pin 16 of the E modulation chip is connected to pin 12 of the OPT_MCU chip. Pin 27 of the OPT_MCU chip is connected to pin 31 of the E modulation chip through a BIAS-TEE circuit. Pin 8 of the E modulation chip is connected to pin 9 of the OPT_MCU chip. Pin 8 of the E modulation chip is connected to pin 22 of the COM_MCU chip.

[0024] The other end of BIAS-TEE circuit one is connected to one end of resistor R22 in AMP circuit, and the other end of BIAS-TEE circuit two is connected to power supply circuit.

[0025] The AMP circuit includes an AMP chip. Pin IN- of the AMP chip is connected to the other end of resistor R22. Pin 3 of the AMP chip is connected to pin 27 of the OPT_MCU chip through resistors R22 and R1.

[0026] The AMP chip uses the MAX4335, and the E-modulation chip uses the GN2044.

[0027] The BIAS-TEE circuit one and BIAS-TEE circuit two have the same structure, both including an inductor L, a ferrite bead FB1, and a ferrite bead FB2 connected in series, and a resistor R connected in parallel with the inductor L.

[0028] The interface circuit for connecting the ROSA under test includes a TIA transimpedance amplifier circuit. The input of the TIA transimpedance amplifier circuit is used to connect to the ROSA under test, and the output of the TIA transimpedance amplifier circuit is connected to the input of the OPT_MCU circuit through a port.

[0029] The TIA transimpedance amplifier circuit includes a TIA amplifier circuit and a DA conversion circuit. The TIA amplifier circuit includes a TIA amplifier chip, and the DA conversion circuit includes a DA conversion chip. Pin 12 of the TIA amplifier chip is connected to pin 8 of the ROSA optical receiver component under test through resistor R39. Pin 35 of the TIA amplifier chip is connected to pin 9 of the DA conversion chip through resistor R35. Pins 5 and 6 of the DA conversion chip are connected to pins 32 and 3 of the OPT_MCU chip, respectively.

[0030] The TIA amplifier chip uses MAX15059, and the DA converter chip uses MAX15059.

[0031] Compared with the prior art, the beneficial effects of this utility model are:

[0032] 1. The OPT_MCU chip and COM_MCU chip work together in a division of labor. The OPT_MCU chip is responsible for driving the laser, while the COM_MCU chip is responsible for data interaction with the host computer. This significantly improves the working efficiency of the power-on test board and avoids the problems of slow response speed and test process delay caused by a single chip handling too many tasks.

[0033] 2. The interface circuit used to connect the ROSA under test is connected to the ROSA under test optical receiver via a flexible band, and the interface circuit used to connect the TOSA under test is also connected to the TOSA under test optical transmitter via a flexible band. The flexible band connection simplifies the operation process, solves many drawbacks caused by messy external signal lines, reduces operational complexity, reduces maintenance manpower costs, and avoids abnormal situations such as false triggering and device damage caused by wiring sequence problems, thereby improving the stability of the test station and helping to ensure the normal progress of production testing and the overall delivery schedule.

[0034] 3. The power-on test board has interface circuits for connecting the ROSA under test and the TOSA under test, which enables the TOSA and ROSA under test, which were originally located at their own independent test stations, to be connected to the power-on test board. This allows for the sharing of test equipment and instrument resources, which not only reduces the floor space occupied, but also effectively improves test efficiency and saves costs. It achieves efficient integration and utilization of resources and avoids the problem of resource waste caused by independent test stations.

[0035] 4. The USB interface is used to connect to the host computer, which allows testers to view test data information at any time via the host computer. Attached Figure Description

[0036] Figure 1 This is the schematic diagram of the TOSA and ROSA combined power-on test device. Figure 1 .

[0037] Figure 2 This is the schematic diagram of the TOSA and ROSA combined power-on test device. Figure 2 .

[0038] Figure 3 It is the principle of power supply circuit. Figure 1 ;

[0039] Figure 4 It is the principle of power supply circuit. Figure 2 ;

[0040] Figure 5 It is the principle of power supply circuit. Figure 3 ;

[0041] Figure 6 This is a schematic diagram of a USB interface;

[0042] Figure 7 This is the schematic diagram of the interface circuit used to connect to the TOSA under test;

[0043] Figure 8 Main control circuit principle Figure 1 ;

[0044] Figure 9Main control circuit principle Figure 2 ;

[0045] Figure 10 This is the schematic diagram of an E-modulation circuit;

[0046] Figure 11 This is the schematic diagram of the TEC control circuit;

[0047] Figure 12 This is the schematic diagram of the interface circuit used to connect to the ROSA under test;

[0048] Figure 13 This is the schematic diagram of a TIA amplifier circuit;

[0049] Figure 14 This is the schematic diagram of a DA conversion circuit;

[0050] Figure 15 This is the schematic diagram of an AMP circuit;

[0051] Figure 16 This is a schematic diagram of the device pinout for the TOSA softband.

[0052] Figure 17 This is a schematic diagram of the device pinout for the ROSA softband. Detailed Implementation

[0053] The present invention will now be described in detail with reference to the accompanying drawings. However, it should be noted that the implementation of the present invention is not limited to the following embodiments.

[0054] The following embodiments are implemented based on the technical solution of this utility model, providing detailed implementation methods and specific operation processes. However, the protection scope of this utility model is not limited to the following embodiments. Unless otherwise specified, the methods used in the following embodiments are conventional methods.

[0055] Example 1

[0056] A TOSA and ROSA multiplexed power-on testing device includes a power-on test board. The power-on test board includes a main control circuit, a power supply circuit, an interface circuit for connecting the TOSA under test, an interface circuit for connecting the ROSA under test, and a USB interface. The main control circuit is connected to a host computer via the USB interface. Figure 1 , Figure 6 The power supply circuit provides operating power for the main control circuit, the interface circuit for connecting the TOSA under test, the interface circuit for connecting the ROSA under test, and the USB interface. (See...) Figures 3-5The main control circuit includes an OPT_MCU circuit and a COM_MCU circuit. The OPT_MCU circuit includes an OPT_MCU chip, which is a DS4834. The COM_MCU circuit includes a COM_MCU chip, which is a C8051F320. Pins 13 and 14 of the OPT_MCU chip are connected to pins 13 and 14 of the COM_MCU chip, respectively, for internal IIC communication. Pin 8 of the OPT_MCU chip is connected to pin 23 of the COM_MCU chip for synchronously acquiring the temperature reported by the thermistor inside the TOSA device. Pin 18 of the OPT_MCU chip is connected to the CO... Pin 15 of the M_MCU chip is connected to indicate the current TOSA transmit status; pin 19 of the OPT_MCU chip is connected to pin 20 of the COM_MCU chip for synchronously acquiring the load temperature feedback from the TEC; pin 9 of the OPT_MCU chip is connected to pin 22 of the COM_MCU chip to indicate the current TOSA operating status; pin 10 of the OPT_MCU chip is connected to pin 31 of the COM_MCU chip to indicate the OPT_MCU soft-start operating status; the USB interface is a TYPE-B USB interface, and pins 2 and 3 of the USB interface are connected to pins 5 and 4 of the COM_MCU chip, respectively, see... Figure 6 , Figure 8 , Figure 9 .

[0057] The main control circuit is connected to the interface circuit used to connect the TOSA under test, see [link / details]. Figure 7 The interface circuit for connecting the TOSA under test includes a TEC control circuit, an E-modulation circuit, a BIAS-TEE circuit, and an AMP circuit. The TEC control circuit includes a TEC control chip. Pin D4 of the TEC control chip is connected to pin 7 of the OPT_MCU chip for chip select. Pin C3 of the TEC control chip is connected to pin 19 of the OPT_MCU chip for reporting the output current of the TEC chip. Pin C4 of the TEC control chip is connected to pin 5 of the OPT_MCU chip for sending control signals to the TEC chip. Pin C3 of the TEC control chip is connected to pin 20 of the COM_MCU chip for reporting the output current of the TEC chip to the host computer. The TEC control chip uses an ADN8833. Pins E3, B1, and B2 of the TEC control chip are connected to pins 1 and 2 of the TOSA under test via a flexible strip. Pins B1 and B2 of the TEC control chip are shorted. See [link to documentation]. Figure 1 ,See Figure 11 .

[0058] The E-modulation circuit includes an E-modulation chip, which is a GN2044. Pins 19 and 20 of the E-modulation chip are connected via softband to the bit error rate tester (BIT_ERROR RATE_TESTER). Pin 31 of the E-modulation chip is connected via a BIAS-TEE circuit to pin 4 of the optical transmitter under test (TOSA) via softband. Pin 3 of the E-modulation chip is connected via ferrite beads fb22 and fb21 to pin 7 of the TOSA. (See...) Figure 1 ,See Figure 10 The top side of the power-on test board has a surface interface for connecting the flexible band. Pins 26 and 25 of the E-modulation chip are connected to pins 3 and 32 of the OPT_MCU chip, respectively, for communication between the E-modulation chip and the OPT_MCU. Pin 16 of the E-modulation chip is connected to pin 12 of the OPT_MCU chip for the OPT_MCU to control the reset of the E-modulation chip. Pin 27 of the OPT_MCU chip is connected to pin 31 of the E-modulation chip via a BIAS-TEE circuit for the OPT_MCU to monitor the operating status of the E-modulation chip. Pin 8 of the E-modulation chip is connected to pin 9 of the OPT_MCU chip for the OPT_MCU to monitor the operating status of the E-modulation chip. Pin 8 of the E-modulation chip is connected to pin 22 of the COM_MCU chip to report the current operating status of the E-modulation chip. See [link to relevant documentation]. Figure 10 The BIAS-TEE circuit includes BIAS-TEE circuit one and BIAS-TEE circuit two. One end of BIAS-TEE circuit two is connected to the TXSDOP pin of the E modulation chip. One end of BIAS-TEE circuit one has a capacitor C34 and a resistor R18 connected in series. The other end of resistor R18 is connected to one end of BIAS-TEE circuit two. The other end of BIAS-TEE circuit one is connected to one end of resistor R22 in the AMP circuit. See [link to BIAS-TEE circuit]. Figure 15 The other end of the BIAS-TEE circuit, TOSAVCC, is connected to the power supply circuit's VCCIN port, see... Figure 4The first BIAS-TEE circuit includes an inductor L1, ferrite beads FB12 and FB15 connected in series, with resistor R14 connected in parallel with inductor L1. The second BIAS-TEE circuit includes an inductor L4, ferrite beads FB13 and FB16 connected in series, with resistor R15 connected in parallel with inductor L4. Using the BIAS-TEE circuit enables interference-free coupling between the DC bias signal and the modulation signal, optimizes the insertion loss and matching characteristics of the modulation signal, and reduces the transmission attenuation of the modulation signal. The AMP circuit includes an AMP chip, with pin IN- of the AMP chip connected to the other end of resistor R22. Pin 3 of the AMP chip is connected to pin 27 of the OPT_MCU chip via resistors R22 and R1. The AMP chip used is a MAX4335.

[0059] The interface circuit for connecting the ROSA under test includes a TIA transimpedance amplifier circuit. The input of the TIA transimpedance amplifier circuit is connected to the ROSA under test, and the output of the TIA transimpedance amplifier circuit is connected to the input of the OPT_MCU circuit via a port. (See...) Figures 12-14 The TIA transimpedance amplifier circuit includes a TIA amplifier circuit and a DA conversion circuit. The TIA amplifier circuit includes a TIA amplifier chip, and the DA conversion circuit includes a DA conversion chip. Pin 12 of the TIA amplifier chip is connected to pin 8 of the ROSA optical receiver component under test via resistor R39. Pin 35 of the TIA amplifier chip is connected to pin 9 of the DA conversion chip via resistor R35. Pins 5 and 6 of the DA conversion chip are connected to pins 32 and 3 of the OPT_MCU chip, respectively, for IIC communication between the chips. The TIA amplifier chip and the DA conversion chip are both MAX15059.

[0060] Testing process:

[0061] The principle behind this test board's TOSA testing is explained below. Figure 2 The testing system is based on a power-on test board and includes an optical splitter, optical power meter, spectrum analyzer, host computer, eye diagram analyzer, adjustable optical attenuator, and bit error rate analyzer. During TOSA testing, the optical transmitter under test (TOSA) is placed on the power-on test board and connected to the optical splitter via optical fiber. After splitting, the data is connected to the optical power meter, spectrum analyzer, and eye diagram analyzer via optical fiber. Test data is transmitted from the bit error rate analyzer to the power-on test board. By adjusting the modulation voltage EA and drive current of the laser inside the TOSA via the host computer, the optical power read from the power meter can be obtained. A set of eye diagrams is obtained from the eye diagram analyzer. By comparing the optical power, eye diagram jitter, and extinction ratio of the test sample, the pass / fail status of the TOSA can be determined.

[0062] Based on the same testing system, when testing the ROSA (Optical Signal Absorber) of the optical receiver under test, the standard light source output optical signal is analyzed by a bit error rate analyzer and then connected to the ROSA via an adjustable optical attenuator. After decoding, the test board transmits the signal to the host computer. The test board then transmits the optical signal received by the ROSA back to the bit error rate analyzer. The change in bit error rate is observed, and the result is compared with the standard value of the sample test to determine whether the sensitivity of the ROSA is qualified.

[0063] Example 2

[0064] In this embodiment, a TOSA and ROSA multiplexed power-on test device is the same as in Embodiment 1, but with the addition of a flexible band connection for the TOSA (Optical Transmitter Component) or ROSA (Optical Receiver Component) under test. The top surface of the power-on test board has a surface interface for connecting the flexible band. See [link to documentation]. Figures 16 to 17 .

[0065] When any TOSA or ROSA soft tape is connected to the first interface (the first interface, which is the connection test interface reserved for TOSA soft tape on the board) or the second interface (the second interface, which is the connection test interface reserved for ROSA soft tape on the board) of the power-on test board, one end of the TOSA or ROSA soft tape is connected to the pin of the first interface or the second interface (the pin refers to the solder pad interface reserved on the physical test board), and the other end of the TOSA or ROSA soft tape is used to connect to the optical emitting component TOSA or the optical receiving component ROSA under test.

[0066] This invention employs a collaborative approach using an OPT_MCU chip and a COM_MCU chip. The OPT_MCU chip drives the laser, while the COM_MCU chip handles data interaction with the host computer. This significantly improves the efficiency of the power-on test board, avoiding the slow response and test process delays caused by a single chip handling too many tasks. The interface circuit connecting the ROSA under test to the ROSA under test is connected via a flexible band, as is the interface circuit connecting the TOSA under test to the TOSA under test. This flexible band connection simplifies the operation process, resolving many drawbacks caused by messy external signal lines, reducing operational complexity, minimizing maintenance costs, and preventing false triggering and device damage due to wiring sequence issues. This improves the stability of the test station, ensuring the smooth progress of production testing and the overall delivery schedule. The power-on test board has interface circuits for connecting the ROSA under test and the TOSA under test, enabling both the TOSA and ROSA, which were originally located at their own independent test stations, to be connected to the power-on test board. This allows for the sharing of test equipment and instrument resources, reducing floor space, improving testing efficiency, and saving costs. It achieves efficient integration and utilization of resources, avoiding resource waste caused by independent test stations. The USB interface connects to the host computer, allowing testers to view test data at any time.

Claims

1. A TOSA and ROSA multiplexed power-on testing device, characterized in that, The system includes a power-on test board, which comprises a main control circuit, a power supply circuit, an interface circuit for connecting the TOSA under test, and an interface circuit for connecting the ROSA under test. The interface circuit for connecting the ROSA under test is connected to the main control circuit, and the main control circuit is connected to the interface circuit for connecting the TOSA under test. The main control circuit is connected to a host computer via a USB interface. The power supply circuit is connected to the main control circuit, the interface circuit for connecting the TOSA under test, the interface circuit for connecting the ROSA under test, and the USB interface. The main control circuit includes an OPT_MCU circuit and a COM_MCU circuit. The OPT_MCU circuit and the COM_MCU circuit are connected. The interface circuit for connecting the ROSA under test is connected to the OPT_MCU circuit and the COM_MCU circuit through ports, respectively. The interface circuit for connecting the TOSA under test is connected to the OPT_MCU circuit and the COM_MCU circuit through ports, respectively.

2. The TOSA and ROSA multiplexed power-on testing device according to claim 1, characterized in that, The OPT_MCU circuit includes an OPT_MCU chip, which is a DS4834. The COM_MCU circuit includes a COM_MCU chip, which is a C8051F320. Pins 13 and 14 of the OPT_MCU chip are connected to pins 13 and 14 of the COM_MCU chip, respectively; pin 8 of the OPT_MCU chip is connected to pin 23 of the COM_MCU chip; pin 18 of the OPT_MCU chip is connected to pin 15 of the COM_MCU chip; pin 19 of the OPT_MCU chip is connected to pin 20 of the COM_MCU chip; pin 9 of the OPT_MCU chip is connected to pin 22 of the COM_MCU chip; and pin 10 of the OPT_MCU chip is connected to pin 31 of the COM_MCU chip. The USB interface is a TYPE-B USB interface, and pins 2 and 3 of the USB interface are connected to pins 5 and 4 of the COM_MCU chip, respectively.

3. The TOSA and ROSA multiplexed power-on testing device according to claim 1, characterized in that, The interface circuit for connecting the TOSA under test includes a TEC control circuit, an E modulation circuit, a BIAS-TEE circuit, and an AMP circuit. The input terminal of the TEC control circuit is connected to the output terminal 1 of the OPT_MCU circuit via a port. The output terminal of the TEC control circuit is connected to the input terminal 1 of the COM_MCU circuit via a port. The input terminal 1 of the E modulation circuit is connected to the output terminal 2 of the OPT_MCU circuit via a port. The output terminal of the E modulation circuit is connected to the input terminal 2 of the COM_MCU circuit via a port. The input terminal 2 of the E modulation circuit is connected to the output terminal of the BIAS-TEE circuit via a port. The input terminal of the BIAS-TEE circuit is connected to the output terminal of the AMP circuit via a port. The input terminal of the AMP circuit is connected to the output terminal 3 of the OPT_MCU circuit via a port.

4. The TOSA and ROSA multiplexing power-on testing device according to claim 3, characterized in that, The TEC control circuit includes a TEC control chip for connecting to the laser's emission component TOSA. Pin D4 of the TEC control chip is connected to pin 7 of the OPT_MCU chip, pin C3 of the TEC control chip is connected to pin 19 of the OPT_MCU chip, pin C4 of the TEC control chip is connected to pin 5 of the OPT_MCU chip, and pin C3 of the TEC control chip is connected to pin 20 of the COM_MCU chip. The TEC control chip is an ADN8833.

5. The TOSA and ROSA multiplexing power-on testing device according to claim 3, characterized in that, The E modulation circuit includes an E modulation chip for connecting the optical emission component under test (TOSA) and the bit error rate meter (BIT_ERROR RATE_TESTER); the BIAS-TEE circuit includes BIAS-TEE circuit one and BIAS-TEE circuit two. One end of BIAS-TEE circuit two is connected to the TXSDOP pin of the E modulation chip. One end of BIAS-TEE circuit one is connected in series with a capacitor C34 and a resistor R18. The other end of the resistor R18 is connected to one end of BIAS-TEE circuit two. Pins 26 and 25 of the E modulation chip are connected to pins 3 and 32 of the OPT_MCU chip, respectively. Pin 16 of the E modulation chip is connected to pin 12 of the OPT_MCU chip. Pin 27 of the OPT_MCU chip is connected to pin 31 of the E modulation chip through a BIAS-TEE circuit. Pin 8 of the E modulation chip is connected to pin 9 of the OPT_MCU chip. Pin 8 of the E modulation chip is connected to pin 22 of the COM_MCU chip. The other end of BIAS-TEE circuit one is connected to one end of resistor R22 in AMP circuit, and the other end of BIAS-TEE circuit two is connected to power supply circuit. The AMP circuit includes an AMP chip, with pin IN- of the AMP chip connected to the other end of resistor R22; pin 3 of the AMP chip is connected to pin 27 of the OPT_MCU chip through resistors R22 and R1. The AMP chip uses the MAX4335, and the E-modulation chip uses the GN2044.

6. The TOSA and ROSA multiplexed power-on testing device according to claim 5, characterized in that, The BIAS-TEE circuit one and BIAS-TEE circuit two have the same structure, both including an inductor L, a ferrite bead FB1, and a ferrite bead FB2 connected in series, and a resistor R connected in parallel with the inductor L.

7. The TOSA and ROSA multiplexed power-on testing device according to claim 1, characterized in that, The interface circuit for connecting the ROSA under test includes a TIA transimpedance amplifier circuit. The input terminal of the TIA transimpedance amplifier circuit is used to connect to the ROSA under test, and the output terminal of the TIA transimpedance amplifier circuit is connected to the input terminal of the OPT_MCU circuit through a port.

8. The TOSA and ROSA multiplexed power-on testing device according to claim 7, characterized in that, The TIA transimpedance amplifier circuit includes a TIA amplifier circuit and a DA conversion circuit. The TIA amplifier circuit includes a TIA amplifier chip, and the DA conversion circuit includes a DA conversion chip. Pin 12 of the TIA amplifier chip is connected to pin 8 of the ROSA optical receiver component under test via resistor R39. Pin 35 of the TIA amplifier chip is connected to pin 9 of the DA conversion chip via resistor R35. Pins 5 and 6 of the DA conversion chip are connected to pins 32 and 3 of the OPT_MCU chip, respectively.

9. A TOSA and ROSA multiplexed power-on testing device according to claim 8, characterized in that, The TIA amplifier chip and the DA converter chip are both MAX15059.

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