Semiconductor device

Abstract

A semiconductor device includes a substrate, a shallow trench isolation region above the substrate, a fin or sheet stack above the substrate, a gate structure disposed above the substrate and the shallow trench isolation region, a source / drain structure, and an opening containing a dielectric structure that extends into the substrate to a depth below the shallow trench isolation region and the source / drain structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices with high aspect ratio cut-fill structures. Background Technology

[0002] The semiconductor device manufacturing industry has experienced exponential growth. Over time, technological advancements in materials, design, and manufacturing have led to semiconductor devices with increasingly smaller and more complex circuits. During the development of semiconductor devices, the number of interconnects per wafer area has generally increased, while the size of circuit components has generally decreased. This shrinking of semiconductor device architecture typically increases the complexity of handling and manufacturing semiconductor devices. Utility Model Content

[0003] Some embodiments of this disclosure provide a semiconductor device including a substrate and a plurality of shallow trench isolation regions disposed on the substrate. The device also includes a plurality of fins spaced apart on the substrate and projecting from the plurality of shallow trench isolation regions. The plurality of fins extend in a first direction and include channel regions and a plurality of recesses disposed on opposite sides of the channel regions. The device also includes a plurality of metal gates disposed above the substrate and the shallow trench isolation regions. The plurality of metal gates extend in a second direction and contact the channel regions of the plurality of fins. The device also includes source / drain structures disposed in the recesses. The device includes an opening filled with a dielectric structure. The opening extends into the substrate to a depth below the shallow trench isolation regions and the source / drain structures. The opening divides one of the plurality of fins between a pair of source / drain structures in the plurality of source / drain structures along the first direction, and divides one of the plurality of metal gates along the second direction. When viewed in a cross-section taken along the second direction, the width of the opening decreases from a level at the top of the plurality of fins to a level at the bottom of the plurality of shallow trench isolation regions.

[0004] Other embodiments of this disclosure provide a semiconductor device including a substrate and a field-effect transistor (FET) device disposed on the substrate. The FET device includes fins disposed across the substrate in a first direction. The fins include channel regions. The FET device also includes shallow trench isolation regions disposed around the fins, with the fins protruding from the shallow trench isolation regions. The FET device further includes a gate structure extending along a second direction intersecting the first direction. The gate structure covers the channel regions. The FET device also includes a plurality of source / drain structures formed on opposite sides of the gate structure in the channel regions. The FET device further includes an opening filled with a dielectric structure, and this opening extends into the substrate to a depth below the source / drain structures and below the shallow trench isolation regions. The opening divides the fins along the first direction and the gate structure along the second direction. When viewed in a cross-section taken along the second direction, the width of the opening decreases from a level at the top of the fins to a level at the bottom of the shallow trench isolation regions.

[0005] Further embodiments of this disclosure provide a semiconductor device including a substrate and a plurality of adjacent field-effect transistor (FET) devices on the substrate. Each of the adjacent FET devices includes a stack comprising multiple layers of semiconductor material, such that the stack extends along a first direction and includes a channel region. Each of the adjacent FET devices also includes a metal gate extending along a second direction intersecting the first direction, such that the metal gate covers the channel region. Each of the adjacent FET devices also includes a plurality of source / drain epitaxial structures formed on opposite sides of the gate in the channel region. Each of the adjacent FET devices also includes a plurality of shallow trench isolation regions disposed around the stack. The semiconductor device also includes an opening filled with a dielectric structure. The opening is formed between the adjacent FET devices. The opening extends into the substrate to a depth below the source / drain epitaxial structures and the shallow trench isolation regions. When viewed from a cross-section taken along the second direction, the width of the opening decreases from a level at the top of the plurality of stacks of adjacent FET devices to a level at the bottom of the shallow trench isolation regions. Attached Figure Description

[0006] This disclosure is best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of discussion.

[0007] Figure 1A and Figure 1B Cross-sections of openings formed during manufacturing of semiconductor devices according to various embodiments of this disclosure are shown;

[0008] Figure 2 Different openings formed in a substrate of a semiconductor device according to various embodiments of this disclosure are shown;

[0009] Figure 3A A plan view of an opening formed in the structure of a semiconductor device according to various embodiments of the present disclosure is shown;

[0010] Figure 3B Cross-sections of openings formed in the structure of a semiconductor device according to various embodiments of the present disclosure are shown;

[0011] Figure 3C A plan view of an opening formed in the structure of a semiconductor device according to various embodiments of the present disclosure is shown;

[0012] Figure 3D Cross-sections of openings formed in the structure of a semiconductor device according to various embodiments of the present disclosure are shown;

[0013] Figure 4A , Figure 4B , Figure 4C and Figure 4D A cross-section of the structure of a semiconductor device according to several embodiments of the present disclosure is shown;

[0014] Figure 5A , Figure 5B , Figure 5C and Figure 5D A cross-section of the structure of a semiconductor device according to several embodiments of the present disclosure is shown;

[0015] Figure 6A and Figure 6B A cross-section of the structure of a semiconductor device according to an embodiment of this disclosure is shown;

[0016] Figure 7A and Figure 7B A cross-section of the structure of a semiconductor device according to an embodiment of this disclosure is shown;

[0017] Figure 8 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0018] Figure 9 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0019] Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B Multiple cross-sectional views of a series of process stages of a method for manufacturing a semiconductor device according to multiple embodiments of the present disclosure are shown.

[0020] Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A ,and Figure 25B Multiple cross-sectional views of a series of process stages of a method for manufacturing a semiconductor device according to multiple embodiments of the present disclosure are shown.

[0021] Figure 26A , Figure 26B , Figure 26C , Figure 27A , Figure 27B , Figure 27C , Figure 28A , Figure 28B , Figure 28C , Figure 29A , Figure 29B , Figure 29C , Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 32A ,and Figure 32B Multiple cross-sectional views of a series of process stages of a method for manufacturing a semiconductor device according to multiple embodiments of the present disclosure are shown.

[0022] Figure 33A , Figure 33B , Figure 34A , Figure 34B , Figure 35A , Figure 35B , Figure 36A , Figure 36B , Figure 37A , Figure 37B , Figure 38A , Figure 38B , Figure 39A ,and Figure 39B Multiple cross-sectional views of a series of process stages of a method for manufacturing a semiconductor device according to multiple embodiments of the present disclosure are shown.

[0023] Figure 40A , Figure 40B , Figure 41A , Figure 41B , Figure 42A , Figure 42B , Figure 43A , Figure 43B , Figure 44A , Figure 44B , Figure 45A ,and Figure 45B Multiple cross-sectional views of a series of process stages of a method for manufacturing a semiconductor device according to multiple embodiments of the present disclosure are shown.

[0024] Figure 46A , Figure 46B , Figure 47A , Figure 47B , Figure 48A , Figure 48B , Figure 49A , Figure 49B , Figure 50A , Figure 50B , Figure 51A , Figure 51B , Figure 52A ,and Figure 52B Multiple cross-sectional views of a series of process stages of a method for manufacturing a semiconductor device according to various embodiments of the present disclosure are shown.

[0025] [Symbol Explanation]

[0026] 2: Opening

[0027] 3: Opening

[0028] 4: Depth

[0029] 5: Depth

[0030] 6: Area

[0031] 7: Area

[0032] 8: Etched opening (opening)

[0033] 10:Substrate

[0034] 12: Etched opening (opening)

[0035] 14:Substrate

[0036] 16: Opening

[0037] 18: Opening

[0038] 20: Opening

[0039] 22: Self-aligned contact layer

[0040] 24: Gate layer

[0041] 26: Masking layer

[0042] 28: Fins

[0043] 30: Interlayer dielectric layer

[0044] 31: Contact Etching Stop Layer

[0045] 32: Source / Drain Structure

[0046] 33: Hard mask layer

[0047] 34: Opening

[0048] 36: Location

[0049] 38: Thin sheet stacking

[0050] 40: Interlayer dielectric layer

[0051] 41: Contact Etching Stop Layer

[0052] 42: Source / Drain Structure

[0053] 44: Opening

[0054] 46: Metal gate layer (metal gate)

[0055] 48: Masking layer

[0056] 50: Opening

[0057] 52: Location

[0058] 54: Bottleneck

[0059] 56: Opening

[0060] 58: Fins

[0061] 60: Shallow trench isolation area

[0062] 62: Opening

[0063] 64:Substrate

[0064] 66: Thin sheet stacking (stacked)

[0065] 68: Metal gate

[0066] 70: Base

[0067] 72: Thin slice

[0068] 74: Shallow trench isolation area

[0069] 76: Gate Dielectric

[0070] 78: Passage Area

[0071] 80: Source / Drain Structure

[0072] 82: concave part

[0073] 84: Internal spacers

[0074] 86: Interlayer dielectric layer

[0075] 88: Contact Etching Stop Layer

[0076] 90: Gate sidewall spacer (sidewall spacer)

[0077] 92: Hard mask layer (hard mask)

[0078] 94: Gate isolation notch

[0079] 96: Three-layer masking (three-layer masking)

[0080] 98: Bottom

[0081] 100: Intermediate Layer

[0082] 102: Upper Level

[0083] 104: Opening

[0084] 106: Opening

[0085] 110: Padding

[0086] 112: Dielectric filler

[0087] 114:Substrate

[0088] 116: Fins

[0089] 118: Shallow trench isolation area

[0090] 120: Sacrificial Gate

[0091] 122: Passage Area

[0092] 124: Gate dielectric film (gate dielectric layer)

[0093] 126: Gate spacer

[0094] 128: concave part

[0095] 130: Source / Drain Structure

[0096] 132: Interlayer dielectric layer

[0097] 134: Contact Etching Stop Layer

[0098] 136: Interlayer

[0099] 138: Gate cutting opening

[0100] 140: Sacrificial Fin

[0101] 142: Cutting polycrystalline silicon to fill dielectric

[0102] 144: Compression layer (layer)

[0103] 146: Three-layer masking (three-layer mask)

[0104] 148: Bottom Layer

[0105] 150: Intermediate Layer

[0106] 152: Upper Level

[0107] 154: Opening

[0108] 156: Opening

[0109] 158: Trench

[0110] 160: Padding

[0111] 162: Dielectric filler

[0112] 164:Substrate

[0113] 166: Fins

[0114] 168: Shallow trench isolation area

[0115] 170: Passage Area

[0116] 172: concave part

[0117] 174: Source / Drain Structure

[0118] 176: Contact Etching Stop Layer

[0119] 178: Interface Dielectric

[0120] 180: Gate dielectric layer

[0121] 182: Metal gate

[0122] 184: Dielectric Characteristics

[0123] 186: Part 2

[0124] 188: Upper Part

[0125] 190: Hard mask (hard mask layer)

[0126] 192: Interlayer dielectric layer

[0127] 194: Semiconductor layer (layer)

[0128] 196: Gate cut-fill structure

[0129] 198: Hard Mask

[0130] 200: Conductive layer

[0131] 202: Masking Structure

[0132] 204: Bottom Layer

[0133] 206: Intermediate Layer

[0134] 208: Photoresist layer

[0135] 210: Opening

[0136] 212: Trench

[0137] 214: Padding

[0138] 216: Filler material

[0139] 218: Sacrificial Gate

[0140] 220: Shallow trench isolation area

[0141] 222:Substrate

[0142] 224: Thin sheet stacking

[0143] 226: Dielectric layer

[0144] 228: Covering layer

[0145] 230: High dielectric constant dielectric region

[0146] 232: Dielectric layer

[0147] 234: First semiconductor layer

[0148] 235: concave part

[0149] 236: Second semiconductor layer

[0150] 237: Source / Drain Structure

[0151] 238: Internal spacers

[0152] 240: Interlayer dielectric layer

[0153] 242: Contact Etching Stop Layer

[0154] 244: Low dielectric constant dielectric spacer (low dielectric constant dielectric layer)

[0155] 246: Hard Mask

[0156] 248: Three-layer masking layer

[0157] 250: Bottom layer

[0158] 252: Intermediate Layer

[0159] 254: Upper Level

[0160] 256: Opening

[0161] 258: Opening

[0162] 260: Dielectric pad (dielectric pad layer)

[0163] 262: Dielectric layer

[0164] 264: Sacrificial Gate

[0165] 266: Shallow trench isolation area

[0166] 268:Substrate

[0167] 270: Thin sheet stacking

[0168] 272: First semiconductor layer (first layer)

[0169] 274: Second Layer

[0170] 276: Oxide layer

[0171] 278: concave part

[0172] 280: Source / Drain Structure (Source / Drain Region)

[0173] 282: Internal spacers

[0174] 284: Interlayer dielectric layer

[0175] 286: Contact Etching Stop Layer

[0176] 288: Sidewall spacers

[0177] 290: Hard Mask

[0178] 292: Three-layer masking layer (mask layer)

[0179] 294: Bottom Layer

[0180] 296: Intermediate Layer

[0181] 298: Upper Level

[0182] 300: Opening

[0183] 302: Opening

[0184] 304:Substrate

[0185] 306: Thin sheet stacking (stacked)

[0186] 308: Base

[0187] 310: Thin sheet

[0188] 312: Shallow trench isolation area

[0189] 314: First dielectric layer (first layer)

[0190] 316: Second dielectric layer

[0191] 318: Conformal semiconductor layer (conformal layer)

[0192] 320: Dielectric layer

[0193] 322: High dielectric constant dielectric layer

[0194] 324: Gate dielectric layer

[0195] 326: Metal gate

[0196] 328: Source / Drain Structure

[0197] 330: Internal spacers

[0198] 332: Interlayer dielectric layer

[0199] 334: Contact Etching Stop Layer

[0200] 336: Gate sidewall spacer

[0201] 338: Gate isolation notch

[0202] 340: Hard mask layer (hard mask)

[0203] 342: Three-layer masking layer

[0204] 344: Bottom layer

[0205] 346: Intermediate Layer

[0206] 348: Upper Level

[0207] 350: Opening

[0208] 352: Opening

[0209] 354: Pad

[0210] 805: Steps

[0211] 810: Steps

[0212] 820: Steps

[0213] 830: Steps

[0214] 840: Steps

[0215] 910: Steps

[0216] 920: Steps

[0217] 930: Steps

[0218] 940: Steps

[0219] a: width

[0220] a1: width

[0221] A: Cross-sectional area

[0222] A1: Cross-sectional area (area)

[0223] A2: Cross-sectional area (area)

[0224] b: width

[0225] b1: Width

[0226] BB: Section

[0227] c: Depth

[0228] c1: Depth

[0229] CC: Section

[0230] d: size

[0231] d1: Dimensions

[0232] e: Size

[0233] E1: Etched outline

[0234] E2: Etched outline

[0235] J1: Level

[0236] J2: Level

[0237] X: Position

[0238] Z1: Size

[0239] Z2: Size

[0240] α1: Cross-sectional area (area)

[0241] α2: Cross-sectional area (area)

[0242] θ1: Angle

[0243] θ2: Angle

[0244] θ3: Angle

[0245] θ4: Angle Detailed Implementation

[0246] It is understood that the following disclosure provides many different implementations or embodiments to implement the various features of this disclosure. Specific implementations or embodiments of components and arrangements are described below to simplify this disclosure. Of course, these are merely implementations and not limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the apparatus. Furthermore, in the following description, forming a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed and inserted between the first and second features, such that the first and second features may not be in direct contact. For simplicity and clarity, the various features may be drawn at any scale.

[0247] Furthermore, to facilitate the description of the relationship between one element or feature and another as illustrated in the accompanying drawings, spatially relative terms such as “below,” “lower,” “lower,” “above,” “upper,” “top,” “bottom,” “middle,” and similar terms may be used herein, and these terms do not preclude the existence of other structures above, below, or between said features. In addition to the directions depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Furthermore, the phrase “made of” may mean “comprising” or “consisting of.”

[0248] Additionally, in the following manufacturing processes, one or more additional operations may exist between the described multiple operations, and the order of the multiple operations may be changed. In this disclosure, the term "one of A, B, and C" means "A, B, and / or C" (A; B; C; A and B; A and C; B and C; or A, B, and C), and unless otherwise described, does not mean an element from A, an element from B, and an element from C. Throughout the disclosure, source and drain are used interchangeably, and source / drain refers to one or both of the source and drain. In the following various embodiments, the materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment (e.g., one or more figures) may be applied in other various embodiments, and their detailed description may be omitted. A source / drain configuration may refer to a source or a drain, individually or collectively depending on the context.

[0249] This disclosure generally relates to semiconductor devices including one or more field-effect transistors (FETs) and methods of manufacturing such devices. Various embodiments of the FETs included in this disclosure include planar FETs, fin FETs, wafer FETs (e.g., nanosheet FETs), horizontal gate all-around (HGAA) FETs, vertical gate all-around (VGAA) FETs, or other FET devices. The active regions of a semiconductor device can generally be considered as the regions where one or more transistors are formed. In some cases, spacers or isolation elements are provided between multiple active regions of the semiconductor device. Openings in the semiconductor device can be provided between adjacent active regions. Conversely, multiple active regions of the semiconductor device can be provided between multiple openings. In some forms, forming one or more openings can be achieved by etching through a region of the semiconductor device and filling the openings with one or more dielectric materials (i.e., dielectric structures).

[0250] In some methods of manufacturing semiconductor devices (including fin field-effect transistors or wafer field-effect transistors), openings can be formed by performing fin dicing or wafer dicing processes and filling the fin dicing or wafer dicing regions with one or more dielectric materials. In some embodiments, the fin dicing or wafer dicing etching process that cuts a sacrificial gate material, such as polysilicon, is called a Cut Poly on Diffusion Edge (CPODE) etching process. In some embodiments, the fin dicing or wafer dicing etching process that cuts through a metal gate is called a Cut Metal on Diffusion Edge (CMODE) etching process. A diffusion edge can be called an active edge, that is, an edge adjacent to an adjacent active region. Furthermore, the process of cutting through a metal gate can be called a Cut Metal Gate (CMG) process.

[0251] CPODE or CMODE etching processes can be used to reduce gate pitch, thereby increasing the density of multi-gate devices and consequently improving device performance required for large-scale circuits and devices. CPODE or CMODE etching processes can be used to pattern transistors to avoid leakage current in the source / drain structures or regions formed epitaxially, the transistors, and the silicon substrate. CPODE or CMODE etching processes can form openings with deep etch profiles and high aspect ratios (e.g., triangular or narrow funnel-shaped profiles) to isolate current leakage from the source to the drain across the silicon substrate. Openings with high aspect ratios can be formed by carefully controlling and minimizing minor head loss of the etchant during the CPODE or CMODE etching process. Figure 1A An embodiment of an opening 2 formed via a CPODE or CMODE process in a fin field-effect transistor device is shown. The opening 2 extends to a depth 4 below the shallow trench isolation (STI) region 6. Figure 1B An embodiment of an opening 3 formed in a wafer field-effect transistor device via a CPODE or CMODE process is shown. The opening 3 extends to a depth 5 below the (STI) region 7.

[0252] CPODE or CMODE etching processes can form openings with high aspect ratios by minimizing at least minor head loss of the fluid or plasma etchant during the etching process. Typically, minimizing minor head loss can minimize abrupt changes in the shape of the opening (e.g., trench) or etch profile in the substrate when viewed in cross-section along an etch direction that passes through the etched area.

[0253] In some forms, the relationship between the major head loss and the minor head loss can be represented by the following equations and variables.

[0254] Modified Bernoulli Equation (ignoring the energy losses of the fluid, both major and minor):

[0255]

[0256] Where P is absolute pressure, ρ is fluid density, v is fluid velocity, h is the height above the reference point, g is gravitational acceleration, q is charge density, and E is electric field.

[0257] Modified Darcy–Weisbach equations (considering the energy of the fluid, both primary and secondary losses):

[0258]

[0259] Where h f It is the final height, h i It is the initial height, P f It is the final pressure, P i It is the initial pressure, v f It is the final velocity, v i ρ is the initial velocity, g is the fluid density, q is the gravitational acceleration, E is the electric field, and A is the cross-sectional area.

[0260] Main losses:

[0261]

[0262] Where f is the Darcy-Wiesbach friction coefficient, v is the velocity, g is the gravitational acceleration, Q is the charge carried by the etchant, E is the electric field, and m is the mass.

[0263] Although the term "tunnel" is used in the above equation, this formula can be applied to any etched structure, such as a tunnel, opening, hole, cavity, or trench. Without intending to be bound by any particular theory, the main loss is considered to be caused by friction between the etchant and the surface of the etched structure (e.g., tunnel, opening, hole, cavity, or trench).

[0264] Secondary losses:

[0265]

[0266] Where K is the minor loss coefficient, v is the velocity, g is the gravitational acceleration, Q is the charge carried by the etchant, E is the electric field, and m is the mass.

[0267] Without intending to be bound by any particular theory, the following is a description of secondary losses. Secondary losses are considered to result from shape changes (e.g., changes in cross-sectional shape) of the structure as it is etched along the etching direction, and from the turbulence in the etchant or other materials caused by these shape changes. Shape changes may include joints, contractions, connections, or bottlenecks within the etched structure. It is believed that shape changes cause secondary losses through turbulence induced by the impact of the etchant on regions with shape changes. When considering energy losses as h… minor loss It is generally believed that a relatively large change in the cross-sectional area of ​​the etched structure along the etching direction will lead to a relatively high h. minor loss The relatively small change in cross-sectional area of ​​the etched structure along the etching direction results in a relatively small h. minor loss It is generally believed that a relatively abrupt change in the cross-sectional area of ​​the etched structure along the etching direction leads to a relatively high h. minor loss The relatively gradual change in the cross-sectional area of ​​the etched structure along the etching direction results in a relatively small h. minor loss .

[0268] Figure 2Multiple cross-sections taken along the etching direction via embodiments of a first etch profile (E1) and a second etch profile (E2) are shown. The first etch profile (E1) includes an etch opening 8 in the substrate 10, and the second etch profile (E2) includes an etch opening 12 in the substrate 14. Both the first and second etch profiles terminate at position X in the etch openings 8 and 12. Downward arrows within the etch profiles (E1) and (E2) schematically indicate the approximate direction of at least some etchant during the etching process. When compared to the opening 12 of the second etch profile (E2) having a cross-sectional area A2 at level J1, the opening 8 of the first etch profile (E1) has a relatively small cross-sectional area A1 at level J1. Similarly, when compared to the cross-sectional area α2 of the opening 12 of the second etch profile (E2) at level J2, the opening 8 of the etch profile (E1) has a relatively small cross-sectional area α1 at level J2.

[0269] In situations where there is no intention to be bound by any particular theory, Figure 2 The following differences also exist between the etched profiles (E1) and (E2) shown. When energy loss is considered as h... minor loss When compared with the etch profile (E2) at level J1, the etch profile (E1) is considered to have a higher h during the etching period at level J1. minor loss This is because the cross-sectional area A1 of the opening 8 in the etch profile (E1) is smaller than the cross-sectional area A2 of the opening 12 in the etch profile (E2). Relatively speaking, when compared to the more abrupt change in the shape of the opening 12 along the etch direction from level J1 to level J2 in the etch profile (E2), the etch profile (E1) is considered to have a lower h during the etching period at level J2 compared to the etch profile (E2) due to the more gradual change in the shape of the opening 8 along the etch direction from level J1 to level J2. minor loss The change in the shape of the etched structure (E1) can be viewed as the change in the cross-sectional area of ​​the etched opening 8 from area A1 at level J1 to area α at level J2. 1 The ratio. When compared with the rate of change of the etched structure (E1), the etched structure (E2) has a faster shape change in the etching direction from level J1 with area A2 to level J2 with area α2.

[0270] In situations where no particular theory is applied, the following points should be noted. It is generally believed that in etching processes using high-density plasma at low pressures (e.g., 0.1 mT–100 mT), secondary head losses (h) are... minor lossThis can be significant. As the size of the device and the etch profile shrinks, etch profiles with relatively small critical dimensions are considered to produce relatively high secondary head losses compared to etch profiles with relatively large critical dimensions (CD). For example, in Figure 2 The smaller opening area A1 at level J1 of the etched profile (E1) is considered to have a relatively higher secondary head loss compared to the opening area A2 of the etched profile (E2).

[0271] Figure 3A and Figure 3C An embodiment of the pattern with openings 16 and 18 is shown in a plan view. Figure 3A This shows a relatively high pattern density (high aperture ratio) of the openings, while Figure 3C This shows a relatively low pattern density (low aperture ratio) for a single opening in the same area. Figure 3B and Figure 3D Embodiments of openings 16 and 18 formed using one or more etching processes as described herein (e.g., CPODE or CMODE etching processes) are shown respectively. Figure 3B and Figure 3D The cross-section is taken along the etching direction of openings 16 and 18. Figure 3B The dimension Z1 shown ranges from 160 nm to 200 nm from the level at the top of the fin. Figure 3D The dimension Z2 of the level at the top of the fin shown can range from 170 nm to 210 nm.

[0272] Without being bound by any particular theory, the following points should be noted. It is believed that when the etched profile has a gradually changing shape, for example in… Figure 3B and Figure 3D The funnel-shaped etched profile shown reduces secondary head loss. Along the... Figure 3B and Figure 3D The multiple cross-sections cut along the etching direction of the etch profile shown gradually change in shape from level J1 (with cross-sectional areas A1 and A2, respectively) to level J2 (with cross-sectional areas α1 and α2, respectively). It is believed that the funnel-shaped etch profile significantly reduces secondary head loss at level J2. It is also believed that... Figure 3B The secondary head loss of the etched profile shown is greater at level J1 than at [other locations]. Figure 3D The secondary head loss at level J1 in the etched profile shown is due to the area A1 being smaller than the area A2. However, it is believed that this loss occurs when compared with... Figure 3D Compared to the etched outline in the middle, in Figure 3BIn the etched profile shown, the shape of the etched profile changes gradually from level J1 to level J2, so in Figure 3D The secondary head loss of the etched profile shown is greater at level J2 than at [other locations]. Figure 3B The minor head loss at level J1 is shown in the etched profile.

[0273] In some forms, when considering Figure 3A When using the high-density pattern (high aperture ratio) shown in the figure, the desired minimum is achieved in Figure 3B The secondary head loss at level J2 shown is minimized by a gradual change in cross-sectional area from A1 to a1. In some forms, when considering... Figure 3C When the low-density pattern (low aperture ratio) is shown, it is desirable to provide in Figure 3D The relatively large cross-sectional area A2 is used to minimize the secondary head loss at level J1.

[0274] Figure 4A and Figure 4B Different etch profiles are shown, according to some embodiments, of cross-sections taken along the gate structure of a fin field-effect transistor device having a self-aligned contact (SAC) structure (formed from amorphous silicon). Figure 4A The cross-section shown forms part of the device, which has multiple openings with a high-density pattern (high aperture ratio). Figure 4B The cross-section shown forms part of the device, which has multiple openings with a low-density pattern (low aperture ratio).

[0275] exist Figure 4A The opening 20 in the structure is formed by an etching process, such as CPODE or CMODE, to provide a gradual change in shape by etching the profile along the etching direction of the opening to minimize minor head loss at level J2, thereby allowing high-density placement of multiple openings in the device without etching structures such as self-aligned contact layers 22 and gate layers 24, which are separated from the openings by a mask layer 26.

[0276] Formed in Figure 4B The opening 34 in the structure is etched using an etching process, such as CPODE or CMODE, to minimize secondary head loss at level J1 without exposing structures such as the self-aligned contact layer 22 or gate layer 24, which are separated from the opening 34 by a mask layer 26. The opening 34 is etched without exposing the self-aligned contact layer at location 36.

[0277] In some implementations, control is in Figure 4A and Figure 4BThe cross-sectional area (A) at the top of the opening shown can be adjusted by modifying the pattern size in extreme ultraviolet (EUV) lithography or hard mask opening etching processes.

[0278] Figure 4C and Figure 4D They were displayed in Figure 4A and Figure 4B The structure shown is a cross-section taken along fin 28. An interlayer dielectric (ILD) layer 30 is provided above the epitaxially formed source / drain structure 32. Contact etch stop layers (CESL) 31 are provided in the region between the top of the source / drain structure 32 and the interlayer dielectric layer 30, and on the sidewalls of the interlayer dielectric layer. In some forms, the contact etch stop layers may be formed of silicon nitride. A hard mask layer 33 is formed above the top of the interlayer dielectric layer 30.

[0279] Figure 4C This illustrates that the etching process does not damage the interlayer dielectric layer 30 on either side of the opening 20. In some embodiments, a portion of the contact etch stop layer 31 (e.g., with a thickness between 0 and 3 nanometers) remains on the sidewall of the interlayer dielectric layer 30 facing the opening 20. In some embodiments, a portion of the self-aligned contact layer 22 (e.g., with a thickness ranging from 0 to 3 nanometers) remains on the surface of the contact etch stop layer 31 facing the opening 20, in a region below the level of the hard mask layer 33. Figure 4D In this process, the etching process that forms the opening 34 will not damage the interlayer dielectric layer 30 or the epitaxially formed source / drain structure 32 on either side of the opening 34.

[0280] Figure 5A and Figure 5B Different etch profiles are shown, according to some embodiments, of cross-sections taken along the metal gate structure of a thin-film field-effect transistor device. Figure 5A The cross-section shown forms part of the device, which has multiple openings with a high-density pattern (high aperture ratio). Figure 5B The cross-section shown forms part of the device, which has multiple openings with a low-density pattern (low aperture ratio). In some embodiments, control is achieved within... Figure 5A and Figure 5B The cross-sectional area (A) at the top of the opening shown can be adjusted by adjusting the pattern size in an extreme ultraviolet lithography process or a hard mask opening etching process.

[0281] Figure 5C and Figure 5D They were displayed in Figure 5A and Figure 5BThe structure shown is a cross-section taken along the stack of thin sheets 38. Formed in Figure 5A The opening 44 in the structure shown is provided with a gradual change in shape via an etching process, such as via a CPODE or CMODE process, through an etching direction along the etch profile of the opening to minimize minor head loss at level J2, thereby allowing for high-density placement of multiple openings in the device without exposing the structure of the metal gate layer 46 separated from the opening by the mask layer 48.

[0282] Formed in Figure 5B The opening 50 in the structure shown is etched using an etching process, such as a CPODE or CMODE process, to minimize secondary head loss at level J1 without exposing the metal gate 46 separated from the opening 50 by the mask layer 48. The opening 50 is etched so as not to expose the metal gate 46 at location 52.

[0283] Figure 5C and Figure 5D They were displayed in Figure 5A and Figure 5B The structure shown is a cross-section taken along the stack of thin sheets 38. Figure 5C and Figure 5D This shows the interlayer dielectric layer 40 provided above the epitaxially formed source / drain structure 42. Figure 5C and Figure 5D It is also shown that a contact etch stop layer 41 is provided in the region between the top of the source / drain structure 42 and the interlayer dielectric layer 40, and on the sidewalls of the interlayer dielectric layer. In some forms, the contact etch stop layer may be formed of silicon nitride. Figure 5C This demonstrates that the etching process does not damage the interlayer dielectric layer 40, the contact etch stop layer 41, or the epitaxially formed source / drain structure 42 on either side of the opening 44. Figure 5D The etching process is shown to have not damaged the interlayer dielectric layer 40 or the epitaxially formed source / drain structure 42 on either side of the opening 50, and at least a plurality of portions of the contact etch stop layer 41 remain on the sidewall of the interlayer dielectric layer 40 and face the opening 50.

[0284] Figure 6A This shows a cross-section of an embodiment of a fin field-effect transistor device taken along the metal gate after performing a CMODE etching process. Figure 6B A magnified view of the bottleneck 54 of opening 56 is shown, where the dimension "b" is... Figure 6AThe measurements are as follows: Reference numeral (a) corresponds to the width of the opening 56 at the top of the fin 58. Reference numeral (b) corresponds to the width of the opening at the bottleneck 54. In some forms, the ratio of width (a) to width (b) is in the range of about 2.8 to about 3.8, or from about 2.7 to about 3.4. Reference numeral (c) corresponds to a depth of this opening, measured from a level at the top of the fin 58 to the bottom of the opening. Reference numeral (d) corresponds to a dimension of this opening, measured from a level at the top of the fin 58 to a level at the bottom of the shallow trench isolation region 60. In some forms, the ratio of depth (c) to depth (d) is in the range of about 1.7 to about 2, or from about 1.8 to about 1.9. Reference numeral (e) corresponds to a dimension between the base of the bottleneck within the opening and the level at the bottom of the shallow trench isolation region. In some forms, the ratio of width (b) to dimension (e) ranges from about 2.3 to about 5.8, or from about 2.4 to about 5.7. Angles (θ1 and θ2) correspond to multiple slopes on opposite sides of this opening, from the layer at the top of the fin to the layer at the bottom of the shallow trench isolation region. Angles (θ3 and θ4) correspond to multiple slopes on opposite sides of this opening, from the layer at the bottom of the shallow trench isolation region to the bottom of the opening. In some forms, the ratio of one of angles θ1 and θ2 to one of angles θ3 and θ4 ranges from about 0.85 to about 0.95, or from about 0.87 to about 0.93.

[0285] Figure 7A This shows a cross-section of an embodiment of a fin field-effect transistor device taken along the fins after performing a CMODE etching process. Figure 7B It shows in Figure 7AThe diagram shows an enlarged view of the opening 62 in a region near the top of the fin and the gate structure. Reference numeral (a1) corresponds to the width of the opening 62 at the top of the gate. Reference numeral (b1) corresponds to the width of the opening 62 at the top of the fin. In some forms, the ratio of width (a1) to width (b1) ranges from about 1.04 to about 1.18, or from 1.07 to about 1.16. Reference numeral (c1) corresponds to the depth of the contraction of the funnel-shaped feature of the opening, measured from a level at the top of the gate to a level at the top of the fin. Reference numeral (d1) corresponds to a dimension of this opening from the top level of the fin to the bottom of the opening. In some forms, the ratio of depth (c1) to dimension (d1) ranges from about 0.02 to about 0.06, or from about 0.03 to about 0.05. Angles (θ1 and θ2) correspond to multiple slopes on opposite sides of this opening from the level at the top of the gate to the level at the top of the fin. Angles (θ3 and θ4) correspond to multiple slopes on opposite sides of this opening from the level at the top of the fin to the bottom of the opening. In some forms, the ratio of one of angles θ1 and θ2 to one of angles θ3 and θ4 is in the range of about 0.9 to about 1, or in the range of about 0.92 to about 0.99.

[0286] In some embodiments, when viewed from a cross-section taken along the direction of the gate structure, the width of the opening decreases from a level at the top of the plurality of fins of the fin field-effect transistor device to a level at the bottom of the plurality of shallow trench isolation regions. In some embodiments, the width of the opening gradually and continuously decreases from a level at the top of the plurality of fins to a level at the bottom of the plurality of shallow trench isolation regions. In some embodiments, when viewed from a cross-section taken along the direction of the gate structure, the width of the opening decreases from a level at the top of the stack of fin stacks to a level at the bottom of the shallow trench isolation regions. In some embodiments, the width of the opening gradually and continuously decreases from a level at the top of the fin stack to a level at the bottom of the shallow trench isolation regions.

[0287] According to various embodiments of this disclosure, any suitable etching conditions and etching apparatus can be used to perform the etching process, such as the CPODE etching process or the CMODE etching process. In some embodiments, the etching process is performed via a high-density plasma generated within an etching apparatus (e.g., an etching chamber), which includes an inductively coupled plasma (ICP) coil, a dipole antenna coil, or an electron cyclotron resonance (ECR) magnetron. In various embodiments, the useful operating frequency range for the bias power of the ICP and dipole antenna etching apparatus is from 1 MHz to 35 MHz, 1 MHz to 27 MHz, or 2 MHz to 13.6 MHz. In some embodiments, the suitable operating frequency range for the bias power of the ECR etching apparatus is from 200 kHz to 700 kHz, 350 kHz to 500 kHz, and in other embodiments from 250 kHz to 700 kHz.

[0288] In some forms, etching processes, such as CPODE or CMODE etching, can be performed in a plasma etching apparatus (including an ECR magnetron) at low pressure to achieve highly directional and anisotropic etching. In some embodiments, plasma etching is performed in a processing chamber at pressures from about 0.1 mTorr to about 150 mTorr; in some embodiments, at pressures from about 0.2 mTorr to about 100 mTorr; and in other embodiments, at pressures from about 0.3 mTorr to about 80 mTorr, or less than about 50 mTorr. In some embodiments, plasma etching is performed in a processing chamber at temperatures ranging from about 10 degrees Celsius to about 130 degrees Celsius; in some embodiments, from about 20 degrees Celsius to about 120 degrees Celsius; or in other embodiments, from about 30 degrees Celsius to about 100 degrees Celsius. Plasma etching is performed simultaneously with the application of power from an RF power generator, in some embodiments ranging from about 75 W to about 2600 W, in some embodiments from about 0 W to about 2500 W, or in other embodiments from about 200 W to about 1100 W. In some embodiments, pulsed plasma etching is performed with a duty cycle ranging from about 2% to about 98%, in some embodiments from about 5% to about 95%, or in other embodiments from about 10% to about 90%. In some embodiments, plasma etching is performed while an RF bias power ranging from about 0 W to about 2500 W, from about 100 W to about 2000 W, or from about 1500 W to about 1500 W is applied to the substrate. Insufficient etching or damage to the semiconductor device components may occur at pressures, temperatures, and power levels outside the disclosed ranges.

[0289] In embodiments disclosed herein, the etching process, such as the CPODE etching process or the CMODE etching process, uses any suitable etchant species or combination thereof. In some forms, CMODE or CPODE etching for etching silicon can use HBr or Cl2, optionally with the addition of O2 or CO2. In some aspects, achieving control over one or more critical dimensions can be achieved by forming a SiO(Br) passivation layer through the addition of SiCl4, HBr, and O2 during etching. Following the deposition of the passivation layer, a highly directional breakthrough step using etchants with low selectivity (e.g., CF4, C4F6, CH3F, CH2F2, and CHF3) can be used to remove the passivation layer at the etch front and facilitate further etching of silicon. The etching process, which involves passivation layer formation, breakthrough, and passivation layer removal, can be performed in multiple loop steps, for example, repeating the passivation layer formation and breakthrough passivation layer process in multiple loops.

[0290] During the etching process, various etching conditions, such as CMODE or CPODE etching processes, can be used to achieve low energy loss, such as low minor head loss, and to produce openings with low-energy-loss etch profiles exhibiting a gradual change in cross-sectional area, such as a funnel shape or a triangular profile according to embodiments of this disclosure. In some forms, the etching process can produce openings with low-energy-loss etch profiles by performing a series of multiple etching steps with gradually increasing pressure or gradually decreasing temperature. In some aspects, the pressure can be increased while performing the etching steps. In some forms, the pressure can be kept constant during the first etching step and increased during subsequent etching steps. In some aspects, the temperature can be decreased while performing the etching steps. In some forms, the temperature can be kept constant during the first etching step and decreased during subsequent etching steps.

[0291] In some aspects, etching processes can produce openings with low energy loss etch profiles via steps that increase etch selectivity, such as a series of multiple etching steps performed using an etchant formulation that has progressively increasing silicon etch selectivity relative to one or more silicon oxides and silicon nitrides. In some embodiments, the etching process produces increased etch selectivity via a series of multiple etch steps, by etching with an etchant comprising Cl2 or BCl3 during an initial etch step, followed by the use of an etchant comprising HBr in subsequent etch steps.

[0292] The etching operation according to various embodiments of this disclosure creates an opening with a relatively large cross-sectional area at the top of the opening, via an etching step performed at low pressure and high temperature or using an etchant with low etch selectivity for a particular material (e.g., silicon). The etching operation further creates an opening with a relatively small cross-sectional area at a distance from the top of the opening, via etching at high pressure and low temperature or via a highly selective etching step. In some embodiments, very low pressure (e.g., below about 50 mTorr) is used in the main etching step on silicon, achieving a low energy loss profile, such as a funnel shape or a triangular profile. Such low pressure can be achieved by using modern tools capable of generating high-density plasma at low pressure, such as electron cyclotron resonance (ECR) tools and other tools.

[0293] Figure 8 A flowchart illustrating an embodiment of the etching process according to this disclosure is shown. The etching process may include CPODE or CMODE etching processes. During the fabrication of a fin field-effect transistor semiconductor device, an etching process can be performed on any structure. Figure 8 The etching process shown includes extending an opening through the gate structure by removing a segment of the gate structure extending in a second direction (step 810). The gate structure may include a metal gate or a sacrificial gate. When etching a sacrificial gate, the etching process may include a CPODE process, or when etching a metal gate, it may include a CMODE process. Figure 8 The etching process shown also includes extending an opening through the fin by removing a segment of the fin extending in a first direction, where the first direction intersects with a second direction (step 820). Furthermore, by removing a segment of the fin, extending the opening through the fin can be performed without exposing multiple source / drain structures on opposite sides of the opening along the first direction. Figure 8 The etching process shown also includes extending the opening through the shallow trench isolation region by removing a portion of the shallow trench isolation region (step 830), and extending the opening into the substrate by removing a portion of the substrate (step 840). Used in Figure 8 The etching process shown creates openings that extend through the gate structure, fins, and shallow trench isolation region, and to a depth in the substrate below the shallow trench isolation region. The etching process can also extend the openings below the source / drain structure of the fin field-effect transistor device. Figure 8 The etching process can optionally extend the opening through the semiconductor material formed above the gate structure by removing a segment of the semiconductor material (step 805).

[0294] Figure 9A flowchart of an etching process according to an embodiment of this disclosure is shown. Typically, the etching process may include a CPODE or CMODE etching process. During the fabrication of a wafer field-effect transistor semiconductor device (e.g., a nanosheet field-effect transistor semiconductor device), the etching process can be performed on any structure. Figure 9 The etching process shown includes extending an opening through the gate structure by removing a segment of the gate structure extending in a second direction (step 910). The gate structure may include a metal gate or a sacrificial gate. The etching process may include a CPODE process when etching a sacrificial gate, or a CMODE process when etching a metal gate. Figure 9 The etching process shown also includes extending the opening by removing a segment of a stack (comprising multiple layers of semiconductor material) extending along a first direction, where the first direction intersects with a second direction (step 920). Furthermore, the removal of a segment of the stack can be performed without exposing multiple source / drain structures along the first direction on opposite sides of the opening. Figure 9 The etching process shown also includes extending the opening through the shallow trench isolation region by removing a portion of the shallow trench isolation region (step 930), and extending the opening into the substrate by removing a portion of the substrate (step 940). Used in Figure 9 The etching process shown creates openings that extend through the gate structure, stack, and shallow trench isolation region, and to a depth in the substrate below the shallow trench isolation region. The etching process can also extend openings below the source / drain structure of the wafer field-effect transistor device.

[0295] In some aspects, the etching process includes reducing the etching temperature during etching. In some embodiments, the etching process includes continuously reducing the etching temperature throughout one or more consecutive stages of the etching process. In some embodiments, the etching process includes maintaining a constant etching temperature during each respective stage of two or more consecutive stages, while performing the subsequent stage of two or more consecutive stages at an etching temperature lower than the etching temperature during the preceding stage of the two or more consecutive stages. In some forms, the sequential multiple stages correspond to the removal of different components of the structure of the semiconductor device during the etching process. In some embodiments, the etching temperature when the extension opening passes through the semiconductor material formed over the gate structure is higher than the etching temperature when the extension opening passes through the gate structure. In some embodiments, the etching temperature when the extension opening passes through the gate structure is higher than the etching temperature when the extension opening passes through a fin or wafer stack. In some embodiments, the etching temperature when the extension opening passes through a fin or wafer stack is higher than the etching temperature when the extension opening passes through a shallow trench isolation region. In some embodiments, the etching temperature when the extension opening passes through a shallow trench isolation region is higher than the etching temperature when the extension opening extends into the substrate.

[0296] In some aspects, the etching process includes increasing the etching pressure during the etching process. In some embodiments, the etching process includes continuously increasing the etching pressure during one or more consecutive stages of performing the etching process. In some embodiments, the etching process includes maintaining a constant etching pressure during each respective stage of two or more consecutive stages, while performing a subsequent stage of two or more consecutive stages at an etching pressure higher than the etching pressure during the preceding stage of the two or more consecutive stages. In some forms, the consecutive multiple stages of the etching process coincide with the removal of different components of the structure of the semiconductor device during the etching process. In some embodiments, the etching pressure when the extension opening passes through the semiconductor material formed over the gate structure is lower than the etching pressure when the extension opening passes through the gate structure. In some embodiments, the etching pressure when the extension opening passes through the gate structure is lower than the etching pressure when the extension opening passes through a fin or wafer stack. In some embodiments, the etching pressure when the extension opening passes through a fin or wafer stack is lower than the etching pressure when the extension opening passes through a shallow trench isolation region. In some embodiments, the etching pressure when the extension opening passes through a shallow trench isolation region is lower than the etching pressure when the extension opening extends into the substrate.

[0297] In some aspects, the etching process includes increasing pressure and decreasing temperature during the etching process, consistent with any combination of the various embodiments of increasing pressure and decreasing temperature during the etching process described in this disclosure. In some implementations, one or more of the following conditions are met during the etching process: the etching temperature when the extension opening passes through the semiconductor material formed over the gate structure is higher than the etching temperature when the extension opening passes through the gate structure; the etching temperature when the extension opening passes through the gate structure is higher than the etching temperature when the extension opening passes through the fin or wafer stack; the etching temperature when the extension opening passes through the fin or wafer stack is higher than the etching temperature when the extension opening passes through the shallow trench isolation region; the etching temperature when the extension opening passes through the shallow trench isolation region is higher than the etching temperature when the extension opening extends into the substrate; the etching pressure when the extension opening passes through the semiconductor material formed over the gate structure is lower than the etching pressure when the extension opening passes through the gate structure; the etching pressure when the extension opening passes through the gate structure is lower than the etching pressure when the extension opening passes through the fin or wafer stack; the etching pressure when the extension opening passes through the fin or wafer stack is lower than the etching pressure when the extension opening passes through the shallow trench isolation region; and the etching pressure when the extension opening passes through the shallow trench isolation region is lower than the etching pressure when the extension opening extends into the substrate.

[0298] In some aspects, the etching process includes increasing the etch selectivity of silicon relative to silicon oxide or silicon nitride throughout the etching process. In some embodiments, this is achieved by using an initial etchant formulation comprising a high concentration of Cl2 or BCl3 in early etching stages and an etchant formulation with a high concentration of HBr in later etching stages. In some forms, each stage of the etching process includes a different etchant formulation, wherein an etchant formulation with a high proportion of Cl2 is used in the initial stage, and the etchant formulation in each subsequent etching stage has a lower proportion of Cl2. In some aspects, the etchant formulation in the initial stage of the etching process comprises a low proportion of HBr, and the etchant formulation in each subsequent etching stage has a higher proportion of HBr.

[0299] The descriptions of process stages in this document, such as the first, second, or third stage of a process, such as CPODE or CMODE etching processes, do not preclude the performance of intermediate processing on the structure between sequentially numbered stages. Furthermore, the description of the first stage of a process (e.g., a CPODE or CMODE process) does not preclude the performance of earlier processing on the structure prior to the first stage. Moreover, the apparent inclusion of the last stage in the described sequence of processing stages does not preclude subsequent processing of the structure resulting from multiple processing stages in this sequence. Furthermore, any intermediate, earlier, or subsequent processing may include any one or more processes used to produce the structure, including any one or more additional CPODE or CMODE processes. Additionally, processing stages may be reordered, or one or more processing stages may be omitted as needed.

[0300] Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A ,and Figure 17A Multiple cross-sections of multiple structures are shown during several successive stages of a method for manufacturing a semiconductor device (including multiple thin-film field-effect transistor devices) according to some embodiments. Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A ,and Figure 17A The multiple cross sections shown are cut along a stack of thin-film field-effect transistor devices, wherein the stack of thin-film devices extends in a first direction. Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B ,and Figure 17B Showing respectively in Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A ,and Figure 17A The diagram shows multiple cross-sectional views of the various structures along a metal gate structure, wherein the metal gate structure extends in a second direction intersecting the first direction.

[0301] Figure 10A and Figure 10BA cross-section of a structure including substrate 64 is shown. Substrate 64 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., having p-type or n-type dopants) or undoped. The substrate may be a wafer, such as a silicon wafer. Typically, an SOI substrate may include a layer of semiconductor material formed on an insulating layer (not shown). The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer may be provided on a substrate, such as a silicon or glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the substrate includes a semiconductor material. In some forms, the semiconductor material of the substrate may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The substrate may also include structurally additional features or components not shown in the accompanying drawings.

[0302] exist Figure 10A and Figure 10B The embodiment shown includes a sheet stack 66 formed over a substrate 64. Figure 10A The cross-section of the stack 66 extending in the first direction is shown. Figure 10B A plurality of stacks 66 are shown in a cross-section taken along a metal gate 68 extending in a second direction. The stacks 66 include a substrate 70 and a plurality of sheets 72 above the substrate. In some forms, the sheets have the same composition as the substrate and the base plate. Figure 10BA shallow trench isolation region 74 formed around a substrate 70 of a stack 66 is shown. In some embodiments, the shallow trench isolation region includes shallow trench isolation recesses filled with one or more insulating materials. The shallow trench isolation recesses can be formed via an etching process. In some embodiments, the shallow trench isolation recesses are formed using a dry etching process using etchant gases such as HF and NH3. Plasma may be generated during the etching process. Argon gas may also be included during the etching process. In some embodiments, the shallow trench isolation recesses are formed using a wet etching process using HF. The shallow trench isolation region may include a pad oxide (not shown), which may be a thermal oxide formed via thermal oxidation of a surface layer of the substrate. The pad oxide may also be a deposited silicon oxide layer, formed using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), flowable chemical vapor deposition (FCVD), or the like. Shallow trench isolation regions may also include a dielectric material above the pad oxide, wherein the dielectric material can be formed using flowable chemical vapor deposition, spin coating, or the like. In some forms, dielectric materials such as SiOx, SiN, SiCN, SiOCN, and SiGeOx can be used to fill the shallow trench isolation regions. Pads can be formed in the shallow trench isolation regions, and the dielectric materials formed above the pads can each be independently any type of insulating material, including various oxides such as silicon oxides, nitrides, or other insulators, or combinations thereof. Other dielectric materials and other formation processes can be used.

[0303] exist Figure 10A and Figure 10B The embodiment shown includes a gate dielectric 76 formed over shallow trench isolation regions and multiple portions of the substrate 70 of the stack 66. The gate dielectric covers and surrounds multiple sheets 72 within the channel regions 78 of the stack 66. The gate dielectric may comprise silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric comprises a high-k dielectric material. In some forms, the gate dielectric has a dielectric constant (k value) greater than about 7.0 and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. The gate dielectric can be formed via any suitable process, such as molecular beam deposition (MBD), atomic layer deposition, and the like. In some forms, the thickness of the gate dielectric ranges from about 8 angstroms. (Approximately 20 angstroms)

[0304] Figure 10A and Figure 10BA metal gate 68 formed above a stack 66 is shown, covering and surrounding a plurality of sheets 72 in a channel region 78, with a gate dielectric 76 disposed between the metal gate 68 and the sheets 72. In some forms, the metal gate is referred to as a work function layer and can be a P-type work function layer, an N-type work function layer, multiple layers thereof, or a combination thereof. Examples of P-type work function metals that may be included in the metal gate for a P-type device include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Examples of N-type work function metals that may be included in the metal gate for an N-type device include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof.

[0305] Figure 10A An epitaxial source / drain structure 80 is shown formed on opposite sides of a plurality of thin sheets 72 at a metal gate 68 and a channel region 78. The source / drain structure may refer to a source or a drain, individually or collectively, depending on the context. The illustrated epitaxial source / drain structure 80 is formed within a recess 82 extending into a substrate 64. The epitaxial source / drain structure may also extend relatively above the stack. The epitaxial source / drain structure can be formed in the recess by growing strained material in the recess via an epitaxial (epi) process. The lattice constant of the strained material may differ from the lattice constant of the substrate (on which the epitaxial source / drain structure is formed). Accordingly, the epitaxial source / drain structure can be used as a stress source to improve carrier mobility. According to some embodiments, the source / drain structure includes silicon-germanium, carbon-doped silicon, or silicon.

[0306] Depending on whether the field-effect transistor (FET) is a p-type or n-type FET, p-type or n-type impurities can be doped in situ during the epitaxial process to form the source / drain structure. For example, when the resulting FET is a p-type FET, silicon germanium boron (SiGeB) can be grown. Conversely, when the resulting FET is an n-type fin FET, silicon phosphide (SiP) or silicon carbide phosphide (SiCP) can be grown. In some embodiments, the source / drain structure can be planted with p-type or n-type impurities as needed. When the source / drain structure is in situ doped with p-type or n-type impurities during epitaxial formation, the planting can be skipped. In some forms, the source / drain structure includes a lower portion formed in the shallow trench isolation region and an upper portion formed above the top surface of the shallow trench isolation region.

[0307] Figure 10AMultiple internal spacers 84 are also shown disposed between multiple regions of a metal gate between the epitaxial source / drain structure 80 and multiple sheets 72. The internal spacers may be formed of SiOCN, SiON, SiOC, SiCN, or the like. An interlayer dielectric layer 86 is formed over the epitaxial source / drain structure 80, and a contact etch stop layer 88 is provided in the region between the top of the source / drain structure 80 and the interlayer dielectric layer 86, and on the sidewalls of the interlayer dielectric layer. In some forms, the contact etch stop layer is formed of silicon oxide, silicon nitride, silicon carbon nitride, or the like, or combinations thereof, and may be formed using chemical vapor deposition, atomic layer deposition, or the like. In some forms, the interlayer dielectric layer comprises a dielectric material formed using, for example, flowable chemical vapor deposition, spin coating, chemical vapor deposition, or any other suitable deposition method. In some forms, the interlayer dielectric layer is formed of an oxygen-containing dielectric material, which may include silicon oxide, phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or similar materials. The formation of the contact etch stop layer and the interlayer dielectric layer may include depositing a conformal contact etch stop layer, depositing the interlayer dielectric layer, and performing a planarization process. Figure 10A Gate sidewall spacers 90 formed on opposite sides of the metal gate 68 are also shown. In some forms, the gate sidewall spacers comprise a low-k dielectric material, such as silicon nitride, silicon carbon nitride, or the like, and may have a single-layer structure or a multilayer structure comprising multiple dielectric layers. The illustrated gate sidewall spacers 90 are disposed between a contact etch stop layer 88 and the metal gate 68, and the contact etch stop layer 88 is disposed between the gate sidewall spacers 90 and the interlayer dielectric layer 86.

[0308] Figure 10A The hard mask layer 92 formed over the metal gate 68, the contact etch stop layer 88, and the sidewall spacers 90 is illustrated. Figure 10B The diagram shows the structure in the configuration after performing a metal gate dicing process. The metal gate dicing process forms a gate isolation notch 94 that extends through the metal gate 68 and into the shallow trench isolation region 74. The metal gate dicing process is used to form multiple isolated transistors. Figure 10BA hard mask 92 is shown formed over a metal gate 68 and fills the gate isolation notch 94. In some forms, the hard mask is formed of silicon nitride, silicon, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof, or multiples thereof. In some forms, the hard mask is formed via any suitable process, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD). After the hard mask is formed, the structure can be cleaned using a wet cleaning process comprising a cleaning agent, such as dilute hydrofluoric acid or an aqueous solution comprising ammonium hydroxide and hydrogen peroxide.

[0309] Figure 11A and Figure 11BA three-layer mask layer 96 formed over a hard mask 92 is shown. The three-layer mask layer 96 includes a bottom layer 98, an intermediate layer 100 above the bottom layer, and a top layer 102 above the intermediate layer. In some forms, the top layer is formed of a photoresist comprising an organic material (e.g., a photosensitive material), and can be a positive or negative photosensitive material. In some forms, the photoresist layer comprises a polymer, such as phenolic resin, poly(norbornene)-maleic anhydride copolymer (COMA), poly(4-hydroxystyrene) (PHS), phenolic resin (bakelite), polyethylene (PE), polypropylene (PP), polycarbonate, polyester, or acrylate-based polymers, such as polymethyl methacrylate (PMMA) or polymethyl methacrylate (PMAA). In some forms, the top layer comprising the photoresist can be formed by spin coating. In some forms, the photoresist layer can be patterned to form an opening therein. In some forms, the intermediate layer has high etch selectivity relative to the top and bottom layers. In some forms, the intermediate layer comprises an inorganic material, which may be a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), an oxide (e.g., silicon oxide), or the like. In some forms, the underlayer is formed using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or another suitable deposition technique. The underlayer may comprise a carbon-based polymer material formed via spin coating. In some forms, the underlayer is a bottom anti-reflective coating (BARC) or an ashing removal dielectric (ARD) layer (e.g., amorphous carbon). Different materials may be used such that the optical and / or etch properties of the underlayer and intermediate layers differ from each other. In some forms, the underlayer is a carbon layer, and the intermediate layer is a silicon-rich layer designed to provide etch selectivity between the intermediate and underlayer layers. The individual layers of a three-layer mask layer may be sequentially carpet-deposited using, for example, a spin coating process. Other processes and materials may be used. Although a three-layer mask layer has been discussed herein, any suitable mask layer may be used. In some implementations, a single-layer or double-layer masking layer may be used (e.g., consisting only of a bottom and top layer without an intermediate layer). The type of masking layer used (e.g., a single-layer, double-layer, or triple-layer masking layer) may depend on the photolithography process used, such as extreme ultraviolet photolithography.

[0310] Figure 11A and Figure 11BThe image shows an upper layer 102 comprising photoresist after patterning to form opening 104. The upper layer can be patterned using any suitable photolithography process to form one or more openings therein. For example, a photomask (not shown) can be placed above the upper layer, which can then be exposed to radiation, such as ultraviolet (UV) beams or radiation in the form of excimer lasers, radiation from extreme ultraviolet systems, or electron beams (e-beams). One or more exposure steps can be performed, and baking or curing operations can be performed to harden the upper layer. Depending on whether a positive or negative photoresist is used, a developer can be used to remove the exposed or unexposed portions of the upper layer. One or more openings can be formed within the structure of a semiconductor device. Figure 11A and Figure 11B Multiple openings are arranged at multiple locations where a portion of the metal gate 68 will be cut using the CMODE process.

[0311] Figure 12A and Figure 12B This illustrates an embodiment of the semiconductor device structure after a section of hard mask 92 has been removed via the first stage of a CMODE etching process. Figure 12A and Figure 12B In both cases, an opening 106 has been formed in the hard mask 92, and the upper layer 102 of the three-layer mask 96 is used as the etching mask. The first stage of the CMODE etching process can be a dry etching process perpendicular to the metal gate 68, with the metal gate used as an etch stop layer. After the first stage of the CMODE process, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0312] Figure 13A and Figure 13B Several embodiments of this disclosure are shown for extending the opening 106 and removing multiple portions of the metal gate 68 and gate dielectric 76 after the second stage of the CMODE etching process. The metal gate 68 is removed from the stack of sheets 72 in the opening 105. Figure 14A and Figure 14B An alternative implementation is shown, following the second stage of the CMODE etching process, to extend the opening 106 and partially remove the metal gate 68 while using a hard mask 92 as an etching mask. Figure 13A , Figure 13B , Figure 14A ,and Figure 14B The second stage of the CMODE process shown can include dry etching. Alternatively, a wet etching process can be used to achieve the desired result. Figure 13A , Figure 13B , Figure 14A ,and Figure 14B The structure within. Etching to obtain in Figure 13A , Figure 13B , Figure 14A ,and Figure 14B After the structure is completed, it can be cleaned using a wet cleaning process, such as the wet cleaning process described in this article.

[0313] Figure 15A and Figure 15B The respective displays show the values ​​in Figure 13A and Figure 13B The structure shown follows the third stage of the CMODE process to extend the opening 106 into the substrate 64. The third stage of the CMODE process removes the portion located within the substrate 64. Figure 13A and Figure 13B Multiple portions of the substrate 64 are shown below the opening 106 defined by the hard mask 92. The opening 106 extends into the substrate to a depth below the shallow trench isolation region 74 and the source / drain structure 80. Figure 15A As shown, in the third stage of the CMODE process, at least a plurality of portions of the internal spacers 84 and a plurality of portions of the sheet 72 therebetween are retained at the level of the source / drain structure 80, and the opening 106 does not expose the source / drain structure 80. Furthermore, the opening 106 does not expose the interlayer dielectric layer 86 along the first direction. In some forms, the opening does not expose the contact etch stop layer and retains at least a portion of the gate sidewall spacers lining the walls of the opening. Figure 15B The opening 106 along the second direction does not expose multiple metal gates 68 of two adjacent field-effect transistor devices. A hard mask 92 is positioned along the second direction between the opening 106 and the metal gates 68 of the two adjacent field-effect transistor devices. The third stage of the CMODE process may include an oriented anisotropic dry etching process. After the third stage of the CMODE etching process, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0314] Figure 16A and Figure 16B The formation of a conformal dielectric liner 110 in an opening and the deposition of a dielectric filler 112 over the liner 110 are shown. The conformal dielectric liner can be any suitable dielectric material, including silicon oxide, silicon oxynitride, or the like, and can be formed using techniques such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like. The dielectric filler can be formed from silicon nitride, silicon oxynitride, silicon carbon nitride, or the like. The dielectric filler can be formed using suitable material deposition techniques such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, flowable chemical vapor deposition, or the like. After the liner and dielectric filler are formed, the structure can be cleaned by using any of the wet cleaning processes described herein. Figure 17A andFigure 17B The diagrams show planarization processes, such as chemical mechanical polishing (CMP), used to planarize surfaces in... Figure 16A and Figure 16B The structure shown.

[0315] Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A Multiple cross-sections of several successive stages of a method for manufacturing a semiconductor device (including multiple fin field-effect transistor devices) according to some embodiments are shown. Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A The multiple cross sections shown are cut along the fins of multiple fin field-effect transistor devices, wherein the fins extend in a first direction. Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B ,and Figure 25B Showing along respectively in Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A ,and Figure 25A The structure shown depicts multiple cross-sections of the sacrificial gate, wherein the sacrificial gate extends in a second direction intersecting the first direction.

[0316] Figure 18A and Figure 18B A structure including a substrate 114 is shown, the substrate 114 including a plurality of fins 116 extending above the substrate. The substrate and fins can comprise or be formed of any material or combination of materials, and can be formed via any process or combination of processes for forming the substrate or fins, such as any material, process, or combination thereof described herein in conjunction with the substrate or fins. Figure 18A and Figure 18BThe fins 116 are formed via a patterned substrate 114, and the material of the fins is the same as that of the substrate. However, the dopant concentration in the fins 116 may differ from the dopant concentration in the substrate 114. In some forms, the dopant is a P-type or N-type dopant. In some forms, the fins include a dopant with the opposite polarity to the dopant in the substrate. In some forms, only one fin or substrate is doped. The dopant concentration in the fins may be higher than that in the substrate, or the dopant concentration in the substrate may be higher than that in the fins. In some forms, the substrate and fins comprise or are formed of group IV semiconductors, such as silicon, germanium, or combinations thereof.

[0317] Figure 18B A shallow trench isolation region 118 is shown disposed above a substrate and around fins, with fins protruding from the shallow trench isolation region. The shallow trench isolation region can comprise or be formed of any material or combination of materials, and can be formed via any process or combination of processes for forming the shallow trench isolation region, such as any material, process, or combination thereof described herein in connection with the shallow trench isolation region. The shallow trench isolation region 118 is recessed, and the top portion of the fin 116 protrudes above the top surface of the shallow trench isolation region. In other embodiments, the top surface of the fin and the top surface of the shallow trench isolation region are substantially flush with each other. In other embodiments, the fin is a replacement fin, formed by etching multiple portions of the substrate between multiple shallow trench isolation regions to form multiple recesses and epitaxially growing another semiconductor material to form the fin in these recesses. Accordingly, the grown fin can be formed of a semiconductor material different from that of the substrate.

[0318] Figure 18A and Figure 18B A sacrificial gate 120 is shown formed across and covering the channel region 122 of fin 116. The sacrificial gate 120 also extends across the shallow trench isolation region 118. In some forms, the sacrificial gate extends in a direction perpendicular to the fin extension direction. Figure 18A and Figure 18B The sacrificial gate shown includes a gate dielectric film 124 formed over the surface and sidewalls of the shallow trench isolation region 118 and the protruding fin 116. The gate dielectric film 124 is formed in the bottom of the recessed region that fills the sacrificial gate 120. In some embodiments, the gate dielectric film is formed of or includes silicon oxide. In some forms, the sacrificial gate is formed using, for example, polycrystalline silicon or amorphous silicon, and other materials may also be used.

[0319] refer to Figure 18AA gate spacer 126 is formed on the sidewall of the sacrificial gate 120. The gate spacer may be formed of a low dielectric constant dielectric material, such as silicon nitride, silicon carbon nitride, or the like, and may have a single-layer structure or a multilayer structure including multiple dielectric layers. Figure 18A A plurality of recesses 128 are shown formed in the portion of fin 116 not covered by sacrificial gate 120 and gate spacer 126. The recesses are filled with source / drain structures 130. Source / drain structures 130 are formed on multiple opposing sides of sacrificial gate 120 in the channel region.

[0320] Figure 18A An interlayer dielectric layer 132 formed over the source / drain structure 130 is shown. A contact etch stop layer 134 is provided in the region between the top of the source / drain structure 130 and the interlayer dielectric layer 132, and on the sidewalls of the interlayer dielectric layer. The interlayer dielectric layer and the contact etch stop layer may comprise or be formed of any material or combination of materials, and may be formed via any process or combination of processes for forming the interlayer dielectric layer or the contact etch stop layer, such as any material, process, or combination thereof described herein in connection with the interlayer dielectric layer or the contact etch stop layer. An interlayer layer 136 separates the contact etch stop layer 134 from the gate spacer 126. The interlayer layer may comprise an insulator such as silicon nitride. A planarization process, such as a chemical mechanical polishing process or a mechanical polishing process, may be performed to planarize the multiple top surfaces of the interlayer dielectric, the sacrificial gate, the gate spacer, the interlayer layer, and the contact etch stop layer.

[0321] refer to Figure 18B The polysilicon dicing process forms gate dicing openings 138 between a plurality of fins 116 and into a shallow trench isolation region 118. The openings are filled with sacrificial fins 140 protruding from the shallow trench isolation region 118. In some forms, the sacrificial fins may comprise insulators such as silicon oxide or silicon nitride. A diced polysilicon-filling dielectric 142 is formed over the sacrificial fins. In some forms, the sacrificial fins and the diced polysilicon dielectric comprise insulators such as silicon nitride, silicon oxide, or a high dielectric constant dielectric material. Figure 18A and Figure 18B Layer 144 is shown above the sacrificial gate 120, the fill dielectric 142, and the interlayer dielectric layer 132. Layer 144 can be used as a hard mask and is formed of or includes one or more materials, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, the like, or combinations thereof. In some forms, this layer is formed of SiN with a thickness ranging from [insert thickness here]. to After the SiN layer is formed, the structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0322] Figure 19A and Figure 19B A three-layer mask 146 formed above a compression layer 144 is shown. The three-layer mask layer 146 includes a bottom layer 148, an intermediate layer 150 above the bottom layer, and an upper layer 152 including a photoresist disposed above the intermediate layer. In some forms, the thickness of the upper layer ranges from... to The thickness range of the intermediate layer is from to The thickness range of the bottom layer is from to Figure 19A Page 19B shows an upper layer 152 including an opening 154, the opening 154 being formed via photolithography, such as extreme ultraviolet lithography. Figure 19A and Figure 19B Multiple openings are arranged at locations where a portion of the sacrificial gate will be cut using the CPODE process.

[0323] Figure 20A and Figure 20B This illustrates an embodiment of the structure when an opening 156 is formed in a section of the compression layer 144 during the first stage of the CPODE etching process. Figure 21A and Figure 21B An embodiment of the structure is shown when a portion of the sacrificial gate 120 below the opening 156 in the compression layer is removed in the second stage of the CPODE etching process. Figure 21A The second stage of the CPODE etching process is shown, exposing the gate dielectric 124 at the bottom of the opening and the gate spacer 126 on the sidewall of the opening. Figure 21B The opening 156 exposes the gate dielectric layer 124 formed above the fins 116 and the shallow trench isolation region 118 at the bottom of the opening. Figure 22A and Figure 22B An embodiment of the structure is shown when the gate dielectric layer 124 is removed from the opening during the third stage of the CPODE etching process.

[0324] Figure 23A and Figure 23B Showing Figure 22A and Figure 22B The structure is implemented in a way that further etches to extend the opening 156 via the fourth stage of the CPODE etching process. Figure 23A It shows that an opening 156 is formed through a portion of the fin 116 and into the substrate 114. Figure 23BThe diagram shows an opening 156 extending through multiple portions of the shallow trench isolation region 118 and into the substrate 114. The opening 156 extends into the substrate 114 to a depth below the source / drain structure 130 and below the shallow trench isolation region 118. Figure 23A The opening 156 is shown dividing the fins along the first direction, and the source / drain structure 130 or the interlayer dielectric layer 132 along the first direction is not exposed. Figure 23B The opening 156 is shown dividing the sacrificial gate 120 along the second direction. Figure 23B The bottom of the opening is also shown, which includes a plurality of trenches 158 separated in a second direction. After any one or more of the first, second, third and fourth stages of the CPODE etching process, the resulting structure can be cleaned before further processing, and this cleaning can be performed using a wet cleaning process as described herein.

[0325] Figure 24A and Figure 24B Showing Figure 23A and Figure 23B The structure is formed after depositing a conformal dielectric liner 160 in the opening and depositing a dielectric filler 162 over the liner 160. The conformal dielectric liner and dielectric filler may include or be formed of any material or combination of materials, and may be formed via any process or combination of processes for forming the conformal dielectric liner or dielectric filler respectively, such as any material, process, or combination thereof described herein in connection with the conformal dielectric liner or dielectric filler. Figure 25A and Figure 25B The structure of the dielectric filler material after planarization using a process such as chemical mechanical polishing is shown.

[0326] Figure 26A , Figure 27A , Figure 28A , Figure 29A ,and Figure 30A Multiple perspective views of multiple structures at various stages of a method for manufacturing a semiconductor device including multiple fin field-effect transistors according to some embodiments are shown. Figure 26B , Figure 27B , Figure 28B , Figure 29B ,and Figure 30B Showing respectively in Figure 26A , Figure 27A , Figure 28A , Figure 29A ,and Figure 30A The cross-sectional view of the structure shown is illustrated. Similarly, Figure 26C , Figure 27C , Figure 28C , Figure 29C ,and Figure 30CThey are respectively in Figure 26A , Figure 27A , Figure 28A , Figure 29A ,and Figure 30A The cross-sectional view of the structure shown. Figure 26A The positions of sections BB and CC along the first and second directions are shown, respectively. Figure 26B , Figure 27B , Figure 28B , Figure 29B ,and Figure 30B The diagrams ending with "B" show the corresponding figures in Figure 26A The diagram shows multiple cross-sectional views of section BB at various process stages. Figure 26C , Figure 27C , Figure 28C , Figure 29C ,and Figure 30C The diagrams ending with "C" show the corresponding figures in Figure 26A The cross-sectional views shown are multiple cross-sectional views of the various processes of the cross-section CC. Figure 31A and Figure 32A It shows that according to some implementation methods Figure 30B Additional processing of the structure shown. Figure 31B and Figure 32B It shows that according to some implementation methods Figure 30C Additional treatment of the structures shown. In some figures, for ease of illustration, some reference numerals for components or features shown may be omitted to avoid obscuring other components or features. Figure 26A , Figure 26B , Figure 26C , Figure 27A , Figure 27B , Figure 27C , Figure 28A , Figure 28B , Figure 28C , Figure 29A , Figure 29B , Figure 29C , Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 32A and Figure 32B Some structural features of the shown implementation have been omitted to simplify illustration and understanding.

[0327] As in Figures 26A to 26CAs shown, this structure includes a substrate 164 and a plurality of fins 166 spaced apart on the substrate and extending in a first direction. A plurality of shallow trench isolation regions 168 are disposed on the substrate, from which the fins 166 extend. Each fin 166 includes a channel region 170 and a plurality of recesses 172 formed on opposite sides of the channel region. A source / drain structure 174 is disposed in the recesses 172. A contact etch stop layer 176 is formed over the source / drain structure 174, and an interlayer dielectric layer 192 is formed on the contact etch stop layer 176. The contact etch stop layer 176 is provided in the region between the top of the source / drain structure 174 and the interlayer dielectric layer 192, and on portions of the sidewalls of the interlayer dielectric layer. This structure also includes an interface dielectric 178 formed on the fin 166, a gate dielectric layer 180 formed on the interface dielectric 178, and a plurality of metal gates 182 extending in a second direction and formed on the gate dielectric layer 180 for use as gate electrodes. The metal gates 182 are disposed above the substrate 164 and the shallow trench isolation region 168. In some embodiments, the metal gates 182 are work function metals. The metal gates 182 contact the channel region 170 of the fin 166. In some embodiments, dielectric features 184 are formed between the plurality of source / drain structures 174 and extend into the channel region, such as in... Figure 26A and Figure 26C As shown in the diagram. In some embodiments, each dielectric feature 184 includes a lower portion 186 and an upper portion 188. In some embodiments, the lower portion 186 and the upper portion 188 include different dielectric materials. For example, the lower portion 186 may include silicon nitride, and the upper portion 188 may include a high dielectric constant dielectric material. The dielectric feature 184 may include different materials or combinations of different materials and may have any suitable shape. The dielectric feature 184 may be formed after the insulating material is formed but before the insulating material is recessed to form the shallow trench isolation region 168. For example, an opening is formed in the insulating material, and the dielectric feature 184 is formed in the opening. The material of the dielectric feature 184 may be different from that of the shallow trench isolation region 168.

[0328] Figure 26A and Figure 26B A hard mask 190 formed on an interlayer dielectric layer 192 is shown. The hard mask 190 may include a dielectric material that has a different etch selectivity than the interlayer dielectric layer 192. In some embodiments, the hard mask 190 includes silicon nitride. Forming the hard mask 190 may be achieved by recessing the interlayer dielectric layer 192, forming the hard mask 190 in the recess, and performing a planarization process to expose the sacrificial gate stack prior to a gate replacement process. Figures 26A to 26CA semiconductor layer 194 is shown, formed over a plurality of metal gates 182 and around the interlayer dielectric layer 192 and the hard mask layer 190. In some forms, the semiconductor layer is a self-aligned contact layer and may be formed of a semiconductor material such as amorphous silicon or a semiconductor material comprising amorphous silicon. In some embodiments, a conductive layer 200 is formed on the metal gates, and a layer comprising a semiconductor material is formed on this conductive layer. The conductive layer may be a metal, such as tungsten, such as fluorine-free tungsten.

[0329] Figure 26A and Figure 26C The diagram illustrates a metal gate dicing process to form a gate dicing structure filled with a gate dicing fill structure 196. The metal gate dicing process extends the gate dicing structure through a semiconductor layer 194, a metal gate 182, a gate dielectric layer 180, and an interface dielectric 178. The gate dicing fill structure 196 contacts a corresponding dielectric feature 184, as shown in... Figure 26A and Figure 26C As shown in the image. Figures 26A to 26C The structure after depositing a hard mask 198 on layer 194 and gate diced fill structure 196 is shown. In some forms, the hard mask 198 comprises silicon nitride. In some embodiments, the hard mask 198 and the gate diced fill structure 196 are monolithic. In other words, the hard mask 198 and the gate diced fill structure 196 are formed simultaneously via the same process and comprise the same material. In some embodiments, the hard mask 198 is a separate layer formed on layer 194 and the gate diced fill structure 196. The hard mask 198 may comprise a material different from that of the gate diced fill structure 196. The hard mask 198 may have a thickness ranging from about 60 nm to about 80 nm. After the hard mask is formed, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0330] As in Figures 27A to 27C As shown, a mask structure 202 is formed on a hard mask 198. In some embodiments, the mask structure 202 is a three-layer photoresist. For example, the mask structure 202 may include a base layer 204, an intermediate layer 206 disposed on the base layer, and a photoresist layer 208 disposed on the intermediate layer. In some forms, the photoresist layer has a range from to The thickness of the intermediate layer ranges from to The thickness, and the bottom layer has a range from to The thickness of the bottom layer 204 and the intermediate layer 206 is such that the optical and / or etch properties of the bottom and intermediate layers differ from each other. In some embodiments, the bottom layer is a carbon-based layer, and the intermediate layer is a silicon-rich layer designed to provide etch selectivity between the intermediate and bottom layers. The photoresist layer 208 can be patterned using photolithography processes, such as extreme ultraviolet lithography, to form the opening 210. Figures 27A to 27C The opening 210 is located at a position where a portion of the metal gate 182 and layer 194 will be removed using the CMODE process.

[0331] Figures 28A to 28C It shows the use in Figures 27A to 27C The first stage of the CMODE etching process for the mask structure 202 shown is used to extend the opening 210. The first stage of the CMODE etching process can be a dry etching process. After extending the opening 210 to remove a section of layer 194, the mask structure can be removed, thereby exposing the metal gate 182 in the opening 210. In some embodiments, conductive layers and other gate cut-fill structures as described above are also removed. After the first stage of the CMODE etching process, the resulting structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0332] Figures 29A to 29C An embodiment of the structure is shown when the opening 210 is extended in the second stage of the CMODE etching process to remove a segment of the metal gate 182. In some forms, the second stage of the CMODE etching process can be a dry etching process. In other forms, a wet etching process can be used to produce the desired effect. Figures 29A to 29C The structure is as follows. In some embodiments, during the second stage of the CMODE etching process, multiple portions of the gate dielectric layer 180 and the interface dielectric 178 are also removed, and one or more fins 166 are exposed in the opening 210. After the second stage of the CMODE etching process, the resulting structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0333] Figures 30A to 30C It is shown in opening 210 (as in Figure 29C The embodiment shown in the diagram has multiple portions of the exposed fins removed and the third stage of the CMODE etching process is used to extend the opening 210 through and below the shallow trench isolation region 168 and into the substrate 164. Figure 30B and Figure 30C The third stage of the CMODE etching process is shown, in which multiple trenches 212 are formed at the bottom of the opening 210 and extend through the shallow trench isolation region 168 into the substrate 164. The multiple trenches 212 are spaced apart along the second direction. Figure 30BAn opening 210 is shown, which divides one of a plurality of fins between a pair of source / drain structures 174 along a first direction into one fin 166. Figure 31A The opening 210 is also shown to have a funnel profile, wherein the width of the funnel profile outside the substrate is greater than the width of the funnel profile inside the substrate. In some embodiments, a portion of the contact etch stop layer 176 (e.g., with a thickness between 0 and 3 nm) is retained on the sidewall of the interlayer dielectric layer 192 facing the opening 210. In some embodiments, a portion of the semiconductor layer 194 (e.g., with a thickness ranging from 0 to 3 nm) is retained on the surface of the contact etch stop layer 176 facing the opening 210, located in a region below the level of the hard mask layer 190. Figure 30C The opening 210 is shown dividing the metal gate 182 along the second direction. (As shown in...) Figure 30B As shown, opening 210 does not expose a pair of source / drain structures 174, interlayer dielectric layer 192, or hard shield 190 located on either side of the opening along the first direction. Figure 30C As shown, opening 210 does not expose the metal gate 182 on either side of the opening along the second direction. A gate-cut structure filled with gate-cut fill structure 196 separates opening 210 from the semiconductor layer 194 and the metal gate 182 along the second direction. In some forms, the third stage of the CMODE etching process includes a dry etching process. After the third stage of the CMODE etching process, the resulting structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0334] Figure 31A and Figure 31B They are shown separately in Figure 30A and Figure 30CA cross-sectional view of the subsequent processing of the structure shown. A dielectric liner 214 is deposited and conformally lined onto the opening 210. The liner 214 may be or include silicon nitride, silicon oxide, silicon oxynitride, silicon carbon nitride, the like, or combinations thereof, and may be deposited via atomic layer deposition, chemical vapor deposition, or another conformal deposition technique. In some embodiments, the liner 214 comprises silicon oxide, and the liner 214 is formed by flowing a precursor gas (e.g., SiCl4 and O2) along with a carrier gas (e.g., Ar) into a processing chamber in which this structure is disposed. The flow rate of the SiCl4 precursor may be less than about 100 sccm, the flow rate of the O2 precursor may be less than about 100 sccm, and the flow rate of the carrier gas may be in the range of about 50 sccm to about 500 sccm. A dielectric filler material 216 is deposited in the opening 210. The filler material 216 may be an insulating material. In some embodiments, the filler material 216 may be a single insulating material, while in other embodiments, the filler material 216 may include a variety of different insulating materials, such as in a multilayer configuration. The filler material 216 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof, and may be deposited via chemical vapor deposition, physical vapor deposition, atomic layer deposition, or another deposition technique. After the deposition of the filler material, the resulting structure may be cleaned using a wet cleaning process, such as the wet cleaning process described herein. Figure 32A and Figure 32B This demonstrates planarization via processes such as chemical mechanical polishing. Figure 31A and Figure 31B The structure is obtained by the structure shown in the figure.

[0335] Figure 33A , Figure 34A , Figure 35A , Figure 36A , Figure 37A , Figure 38A and Figure 39A Multiple cross-sections of several successive stages of a method for manufacturing a semiconductor device (including multiple wafer field-effect transistor devices) according to some embodiments are shown. Figure 33A , Figure 34A , Figure 35A , Figure 36A , Figure 37A , Figure 38A ,and Figure 39A The multiple cross sections shown are cut along a stack of thin-film field-effect transistor devices, wherein the stack of thin-film devices extends in a first direction. Figure 33B , Figure 34B , Figure 35B , Figure 36B , Figure 37B , Figure 38B ,and Figure 39BShowing along respectively in Figure 33A , Figure 34A , Figure 35A , Figure 36A , Figure 37A , Figure 38A and Figure 39A The structure shown is a sacrificial gate structure with multiple cross-sections, wherein the sacrificial gate extends in a second direction intersecting the first direction.

[0336] Figures 33A to 37B The process of forming an opening in a wafer stack and removing the sacrificial gate 218 is shown. This opening electrically isolates multiple adjacent wafer stack field-effect transistors. This opening may also be referred to as a CPODE region because the formation process involves cutting the polysilicon sacrificial gate at the edge of the active region.

[0337] exist Figure 33A and Figure 33B The structure shown includes a substrate 222, which includes a sheet stack 224. Figure 33B A shallow trench isolation region 220 is shown around the bottom of the wafer stack 224. A dielectric layer 226 is formed over the shallow trench isolation region 220. In some forms, the dielectric layer is formed of or comprises an insulating oxide, such as silicon oxide, and may be formed via a deposition process, spin coating, or the like. A cladding layer 228 is formed on the sides of the dielectric layer. In some forms, the cladding layer may comprise silicon germanium. The cladding layer may be formed via a conformal deposition process, such as atomic layer deposition, chemical vapor deposition, or the like. A high-dielectric-constant dielectric region 230 is formed over the dielectric layer 226. In some forms, the high-dielectric-constant dielectric region may comprise hafnium oxide, zirconium oxide, aluminum oxide, aluminum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like. A conformal dielectric layer 232 is formed over the wafer stack 224 and a plurality of the tops of the high-dielectric-constant dielectric regions 230. In some forms, conformal dielectric layers comprise one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high dielectric constant dielectrics.

[0338] As in Figure 33A and Figure 33BAs shown, the upper portion of the sheet stack 224 includes alternating first semiconductor layers 234 and second semiconductor layers 236. In some forms, the first semiconductor layer is formed of, or comprises, SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or similar materials. In some aspects, the second semiconductor layer is formed of, or comprises, combinations of, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or similar materials. In some forms, the second layer comprises the same material as the substrate. Figure 33A and Figure 33B In this process, the sheet stack 224 also includes a portion of a substrate 222 beneath the alternating first and second layers.

[0339] As in Figure 33A As shown, recesses 235 are formed between multiple stacked thin sheets 224 and filled with source / drain structures 237, which can be epitaxially grown. Internal spacers 238 are disposed between the source / drain structures 237 and the first semiconductor layer 234. In some forms, the internal spacers are formed of, or comprise, SiOCN, SiON, SiOC, SiCN, or similar materials. Figure 33A An interlayer dielectric layer 240 is shown above the source / drain structure. A contact etch stop layer 242 is provided in the region between the top of the source / drain structure 237 and the interlayer dielectric layer 240, and on the sidewalls of the interlayer dielectric layer. In some forms, the contact etch stop layer comprises silicon nitride.

[0340] Figure 33A and Figure 33B The image shows a sacrificial gate 218 formed on top of the 224 veneer stack. In some forms, the sacrificial gate comprises polycrystalline silicon or amorphous silicon. Figure 33A A sacrificial gate 218 is shown between multiple source / drain structures 237. A low-dielectric-constant dielectric layer 244 forms sidewalls on the sacrificial gate 218. Figure 33A and Figure 33B A hard mask 246 is shown, deposited over the sacrificial gate 218, the contact etch stop layer 242, the interlayer dielectric layer 240, and the low-dielectric-constant dielectric spacer 244. In some forms, the hard mask is formed of or includes silicon nitride, silicon oxynitride, or the like. After the hard mask is deposited, the resulting structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0341] Figure 34A and Figure 34B The structure after depositing a three-layer mask layer 248 over a hard mask 246 is shown. The three-layer mask layer 248 includes a bottom layer 250, an intermediate layer 252 above the bottom layer, and a top layer 254 above the intermediate layer. In some forms, the top layer is formed of a photoresist, the bottom layer is formed of a cross-linked photoresist, and the intermediate layer is formed of an inorganic dielectric material. An opening 256 is formed in the top layer 254. The opening can be formed using photolithography, such as extreme ultraviolet photolithography.

[0342] Figure 35A and Figure 35B The structure obtained by performing the first stage of a CPODE etching process using a mask layer 246 as an etching mask is shown. In some forms, the first stage of the CPODE process includes a dry etching process. In the illustrated embodiment, the first stage of the CPODE process forms an opening 258 in the hard mask 246, exposing the bottom of the opening, the sacrificial gate 218. Figure 35A and Figure 35B After the structure shown in the document is completed, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described in this document.

[0343] Figure 36A and Figure 36B The diagram illustrates a structure obtained by extending the opening 258 through a second stage of the CPODE etching process using a hard mask 246 as an etching mask to remove the sacrificial gate between multiple interlayer dielectric layers 240 and expose a conformal dielectric layer 232. In some forms, the second stage of the CPODE etching process includes an anisotropic dry etching process that preserves the vertical sidewalls of the sacrificial gate 218, as shown in... Figure 36B As shown in [the image]. Figure 36A and Figure 36B In the structure shown, opening 258 can be referred to as a through-gate trench. Figure 36A and Figure 36B The sheet stack 224 below the opening 258 shown in the diagram can be referred to as a sacrificial sheet stack. (In obtaining...) Figure 36A and Figure 36B After the structure shown in the document is completed, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described in this document.

[0344] Figure 37A and Figure 37B This demonstrates the third stage of the CPODE etching process to remove [the residue / material]. Figure 36A and Figure 36BThe structure shown is obtained by stacking a conformal dielectric layer and sacrificial sheets. The third stage of the CPODE etching process can be anisotropic and selective dry etching, which preserves the shallow trench isolation region 220, the dielectric layer 226 formed on the shallow trench isolation region, the cladding layer 228 formed on the sides of the dielectric layer, and the high dielectric constant dielectric region 230 formed above the dielectric layer. The opening 256 extends to... Figure 37A Within the substrate and below the source / drain structure 237, and extending into Figure 37B The level of the bottom surface of the shallow trench isolation region 220. In other forms, the trench extends below the level of the bottom of one or more shallow trench isolation regions. (This is used to obtain the level of the bottom surface of the shallow trench isolation region.) Figure 37A and Figure 37B After the structure shown in the document is completed, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described in this document.

[0345] Figure 38A and Figure 38B Shown in Figure 37A and Figure 37B The structure shown is formed after the deposition of dielectric material in the opening 258. A dielectric liner layer 260 conforms to the bottom and sidewalls of the opening, and a dielectric layer 262 fills the opening. In some forms, the dielectric liner is formed of or comprises silicon oxide. In some aspects, the dielectric layer is formed of or comprises silicon nitride. Other materials, such as SiC, SiON, SiCN, SiOCN, or similar materials, may also be used to form one or more of the dielectric liner and dielectric layer. Figure 39A and Figure 39B The structure is shown after multiple surfaces of the sacrificial gate 218, dielectric pad 260, dielectric layer 262, and other layers have been planarized using a chemical mechanical polishing process.

[0346] Figure 40A , Figure 41A , Figure 42A , Figure 43A , Figure 44A ,and Figure 45A Multiple cross-sections of several successive stages of a method for manufacturing a semiconductor device (including multiple wafer field-effect transistor devices) according to some embodiments are shown. Figure 40A , Figure 41A , Figure 42A , Figure 43A , Figure 44A ,and Figure 45A The multiple cross sections shown are cut along a stack of thin-film field-effect transistor devices that extend in a first direction. Figure 40B , Figure 41B , Figure 42B , Figure 43B , Figure 44B ,and Figure 45B Showing respectively in Figure 40A , Figure 41A , Figure 42A , Figure 43A , Figure 44A ,and Figure 45A The structure shown is divided into multiple sections along the sacrificial gate structure, wherein the sacrificial gate extends in a second direction intersecting the first direction.

[0347] Figures 40A to 45B The process of forming the opening and removing the sacrificial gate 264 is shown. This opening electrically isolates multiple adjacent slab stacked field-effect transistors. This opening can also be referred to as the CPODE region because the formation process involves cutting the sacrificial gate at the edge of the active region.

[0348] exist Figure 40A and Figure 40B The structure shown includes a substrate 268 and a sheet stack 270 formed on top of the substrate. Figure 25B Shallow trench isolation region 266 is shown, which is formed and filled with one or more dielectric layers around the wafer stack. The upper portion of the wafer stack includes alternating first layer 272 and second layer 274. The first and second layers may comprise any material or combination of materials, or be formed from any material or combination of materials, and may be formed via any process or combination of processes for forming the first and second layers, such as any material, process, or combination thereof described herein in conjunction with the first and second layers of the wafer stack. In some forms, the second layer comprises the same material as the substrate and the base of the wafer stack. Figure 40A and Figure 40B An interlayer oxide layer 276 is also shown conformally formed over the first layer 272 and the second layer 274. In some forms, the interlayer oxide layer is formed of or includes silicon oxide and can be formed via deposition processes, spin coating, or the like.

[0349] Figure 40A A recess 278 is shown, formed between multiple sheet stacks 270 and filled with a source / drain structure 280. In some forms, the source / drain structure is epitaxially grown. An internal spacer 282 is disposed between the source / drain structure 280 and the first semiconductor layer 272. Figure 40A An interlayer dielectric layer 284 formed over the source / drain structure 280 is shown. A contact etch stop layer 286 is provided in the region between the top of the source / drain structure 280 and the interlayer dielectric layer 284, and on the sidewalls of the interlayer dielectric layer. In some forms, the contact etch stop layer comprises silicon nitride. Figure 40A and Figure 40BA sacrificial gate 264 is shown, formed above the top of a vesicle stack 270 and between multiple source / drain regions 280. In some forms, the sacrificial gate comprises polycrystalline silicon or amorphous silicon. Figure 40A Gate sidewall spacers 288 are shown, formed on opposing sides of the sacrificial gate 264 and contacting the contact etch stop layer 286. The source / drain structure, interlayer dielectric, contact etch stop layer, gate sidewall spacers, and internal spacers can comprise or be formed of any material or combination of materials, and can be formed by any process or combination of processes for forming the source / drain structure, interlayer dielectric, contact etch stop layer, gate sidewall spacers, or internal spacers, such as any material, process, or combination thereof described herein in conjunction with the source / drain structure, interlayer dielectric, contact etch stop layer, gate sidewall spacers, or internal spacers.

[0350] Figure 40A and Figure 40B A hard mask 290 is shown, deposited over a sacrificial gate 264, a contact etch stop layer 286, and sidewall spacers 288. The hard mask can comprise or be formed of any material or combination of materials, and can be formed via any process or combination of processes used to form the hard mask, such as any material, process, or combination thereof described herein in conjunction with the hard mask. Following the deposition of the hard mask, the resulting structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0351] Figure 41A and Figure 41B The structure is shown after a three-layer mask layer 292 has been deposited over a hard mask 290. The three-layer mask layer 292 includes a bottom layer 294, an intermediate layer 296 above the bottom layer, and an upper layer 298 above the intermediate layer. An opening 300 is formed in the upper layer 298 of the mask layer and extends across a region corresponding to a plurality of sheet stacks 270, as shown in Figure 41B The cross-section is shown in the image. The opening can be formed using photolithography techniques, such as extreme ultraviolet photolithography.

[0352] Figure 42A and Figure 42B It shows the effect of using in Figure 41A and Figure 41B The mask layer 292 in the diagram is the structure obtained by performing the first stage of the CPODE etching process as an etching mask. In some forms, the first stage of the CPODE process includes a dry etching process. In the illustrated embodiment, the first stage of the CPODE process forms an opening 302 in the hard mask 290 and exposes the sacrificial gate 264 at the bottom of the opening 302. After obtaining the structure... Figure 42A and Figure 42B After the structure shown in the document is completed, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described in this document.

[0353] Figure 43A and Figure 43B The structure is shown as obtained by a second stage of a CPODE etching process using a hard mask 290 as an etching mask to extend the opening 302 through the sacrificial gate 264 between multiple interlayer dielectric layers 284 to expose the conformal oxide layer 276. Figure 43B In the structure shown, the top portion of the sheet stack protrudes from the shallow trench isolation region 266 and is covered by a conformal oxide layer 276. In some forms, the second stage of the CPODE process includes a dry etching process. After obtaining... Figure 43A and Figure 43B After the structure shown in the document is completed, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described in this document.

[0354] Figure 44A and Figure 44B This demonstrates the third stage of the CPODE etching process to remove [the residue / material]. Figure 43A and Figure 43B The structure obtained is shown by the interlayer oxide layer 276. The third stage of the CPODE etching process can be a selective dry etching process, which preserves the shallow trench isolation region 266, the sheet stack 270, and the sidewall spacers 288. After obtaining the structure... Figure 44A and Figure 44B After the structure shown in the document is completed, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described in this document.

[0355] Figure 45A and Figure 45B This demonstrates the fourth stage of the CPODE etching process to remove [the material / material]. Figure 44A and Figure 44B The thin sheets exposed in the opening shown are stacked to extend the opening 302 into the substrate 268 and are lower than the substrate 268. Figure 45A The source / drain structure in 280 and below Figure 45B The structure was obtained by shallow trench isolation region 266. The CPODE etching process did not expose the source / drain structure 280 or the interlayer dielectric layer 284. Figure 45A and Figure 45B After the structure shown in the diagram is completed, it can be cleaned using a wet cleaning process, such as the wet cleaning process described herein. For example, in... Figure 45A and Figure 45BThe opening 302 in the structure shown can be filled with one or more dielectric materials, such as those provided herein.

[0356] Figure 46A , Figure 47A , Figure 48A , Figure 49A , Figure 50A , Figure 51A and Figure 52A Multiple cross-sections of several successive stages of a method for manufacturing a semiconductor device (including multiple wafer field-effect transistor devices) according to some embodiments are shown. Figure 46A , Figure 47A , Figure 48A , Figure 49A , Figure 50A , Figure 51A and Figure 52A The multiple cross sections shown are cut along a stack of thin-film field-effect transistor devices, wherein the stack of thin-film devices extends in a first direction. Figure 46B , Figure 47B , Figure 48B , Figure 49B , Figure 50B , Figure 51B and Figure 52B Showing respectively in Figure 46A , Figure 47A , Figure 48A , Figure 49A , Figure 50A , Figure 51A and Figure 52A The structure shown is divided into multiple sections along the metal gate structure, wherein the metal gate structure extends in a second direction intersecting the first direction.

[0357] Figure 46A and Figure 46B A cross-section of a structure having a sheet stack 306 formed above a substrate 304 is shown. The sheet stack includes a substrate 308 and a plurality of sheets 310 disposed above the substrate. In some forms, the sheets have the same composition as the substrate. Shallow trench isolation regions 312 are formed around the substrate 308 of the stack 306. The shallow trench isolation regions include a first dielectric layer 314 conformally deposited in a recess around the substrate, and a second dielectric layer 316 formed above the first layer 314. The shallow trench isolation regions (including the first and second dielectric layers), the sheets, and the substrate may comprise or be formed of any material or combination of materials, and may be formed via any process or combination of processes for forming the substrate, sheets, or shallow trench isolation regions, such as any material, process, or combination thereof described herein in connection with the substrate, sheets, or shallow trench isolation regions.

[0358] Figure 46BA conformal semiconductor layer 318 deposited in a trench above the shallow trench isolation region 312 is also shown. In some forms, the conformal semiconductor layer is formed of or includes a semiconductor material such as silicon germanium, and is formed using processes such as atomic layer deposition, chemical vapor deposition, or similar methods. A dielectric layer 320 is formed over the conformal layer 318. In some forms, the dielectric layer is formed of or includes an insulating oxide such as silicon oxide, and can be formed via a deposition process, spin coating, or similar methods. A high-k dielectric layer 322 is formed over the dielectric layer 320. A gate dielectric layer 324 is formed over the top of the wafer stack 306, around the wafer 310, and on multiple sides of the conformal layer 318 and the high-k dielectric layer 322. The high dielectric constant dielectric layer and the gate dielectric layer may comprise any material or combination of materials or formed from any material or combination of materials, and may be formed via any process or combination of processes for forming the high dielectric constant dielectric or the gate dielectric layer, such as any material, process, or combination thereof described herein in connection with the high dielectric constant dielectric or the gate dielectric layer respectively.

[0359] Figure 46A and Figure 46B A metal gate 326 is shown, formed above a stack 306 and around a sheet 310 within a gate dielectric layer 324 and a channel region. The metal gate includes or is formed of any material or combination of materials, and can be formed via any process or combination of processes for forming the metal gate, such as any material, process, or combination thereof described herein in conjunction with the metal gate.

[0360] Figure 46A Multiple source / drain structures 328 are shown between multiple stacks 306 and on multiple opposite sides of a sheet 310, with multiple portions of a metal gate 326 between these sheets. Figure 46A An internal spacer 330 is also shown, disposed between regions of the metal gate 326 between the source / drain structure 328 and the wafer 310. The source / drain structure and the internal spacer may comprise or be formed of any material or combination of materials, and may be formed via any process or combination of processes for forming the source / drain structure or the internal spacer, such as any material, process, or combination thereof described herein in connection with the source / drain structure or the internal spacer.

[0361] Figure 46AAn interlayer dielectric layer 332 formed over the source / drain structure 328 is also shown. A contact etch stop layer 334 is provided in the region between the top of the source / drain structure 328 and the interlayer dielectric layer 332, and on the sidewalls of the interlayer dielectric layer. In some forms, the contact etch stop layer comprises silicon nitride. Figure 46A The opposing sides of the metal gate are further covered by gate sidewall spacers 336. The interlayer dielectric layer, the contact etch stop layer, and the gate sidewall spacers may comprise or be formed of any material or combination of materials, and may be formed via any process or combination of processes for forming the interlayer dielectric layer, the contact etch stop layer, or the gate sidewall spacers, such as any material, process, or combination thereof described herein in connection with the interlayer dielectric layer, the contact etch stop layer, or the gate sidewalls.

[0362] Figure 46B This is shown after performing a metal gate dicing process to form a gate isolation notch 338 through the metal gate 326 to expose a high-dielectric-constant dielectric layer 322 formed over the shallow trench isolation region 312. The sheet stack between the multiple isolation notches becomes a sacrificial stack after the notch formation. Figure 46A A hard mask layer 340 is shown formed over the metal gate 326, the contact etch stop layer 334, the interlayer dielectric layer 332, and the gate sidewall spacer 336. Figure 46B A hard mask layer 340 is shown formed over a metal gate 326 and filling a gate isolation notch 338. The hard mask layer may comprise or be formed from any material or combination of materials, and may be formed via any process or combination of processes for forming the hard mask layer, such as any material, process, or combination thereof described herein in conjunction with the hard mask layer. After the hard mask is formed, this structure may be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0363] Figure 47A and Figure 47B Showing respectively in Figure 46A and Figure 46B The structure shown is formed after a three-layer mask layer 342 is formed above a hard mask 340. The three-layer mask layer includes a bottom layer 344, an intermediate layer 346 above the bottom layer, and a top layer 348 above the intermediate layer. In some forms, the top layer includes a photoresist, the intermediate layer includes an oxide such as silicon oxide, and the bottom layer includes a carbon-based layer. Any useful mask layer can be applied to… Figure 47A and Figure 47BThe structure shown is illustrated. The masking layer may include any material or combination of materials or formed from any material or combination of materials, and may be formed via any process or combination of processes for forming the masking layer, such as any material, process, or combination thereof described herein in connection with the masking layer. Figure 47A and Figure 47B The image shows the upper layer 348 after patterning to form opening 350, the upper layer 348 comprising a photoresist. The upper layer can be patterned using any suitable photolithography process described herein to form one or more openings therein. Figure 47A and Figure 47B The multiple openings in the metal gate 326 will be cut at multiple locations using the CMODE process.

[0364] Figure 48A and Figure 48B An embodiment of a semiconductor device structure is shown where a section of a hard mask 340 is removed via a first stage of a CMODE etching process using a mask layer to form an opening 352 in the hard mask 340. In some forms, the first stage of the CMODE process is a dry etching process. After the first stage of the CMODE process, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0365] Figure 49A and Figure 49B The structure is shown after multiple segments of the metal gate 326 and gate dielectric layer 324 are extended in the second stage of the CMODE etching process. The second stage of the CMODE etching process removes the metal gate and gate dielectric layer between multiple sheets 310. The second stage of the CMODE etching process may include dry etching. Alternatively, this structure is obtained via a wet etching process. Figure 49A and Figure 49B The structures within can be cleaned using wet cleaning processes, such as the wet cleaning process described in this article.

[0366] Figure 50A and Figure 50B Showing the Figure 49A and Figure 49B The structure shown performs the third stage of the CMODE process to extend the opening 352 into the substrate 304. The opening 352 extends below the source / drain structure 328 and the shallow trench isolation region 312 and into the substrate 304. The third stage of the CMODE process may include an oriented anisotropic dry etching process. (As shown in...) Figure 50AAs shown, the third stage of the CMODE process retains at least a plurality of portions of the internal spacers 330, with a plurality of portions of the sheet 310 between them, and the opening 352 does not expose the source / drain structure 328. Furthermore, the opening 352 does not expose the interlayer dielectric layer 332 and the contact etch stop layer 334, and retains at least a portion of the gate sidewall spacers 336 lining the walls of the opening 352. Figure 50B In the third stage of the CMODE process, the extended opening 352 removes multiple portions of the substrate 304 located beneath the trench defined by the hard mask 340, while avoiding damage to the conformal semiconductor layer 318, dielectric layer 320, and high-dielectric-constant dielectric layer 322. Following the third stage of the CMODE etching process, this structure can be cleaned using a wet cleaning process, such as the wet cleaning process described herein.

[0367] Figure 51A and Figure 51B The diagram shows the structure after a conformal pad 354 is formed in the opening 352 and a dielectric filler 356 is deposited over the pad 354. The conformal dielectric pad and dielectric filler can comprise or be formed of any material or combination of materials, and can be formed via any process or combination of processes for forming the conformal dielectric pad or dielectric filler respectively, such as any material, process, or combination thereof described herein in connection with the conformal dielectric pad and dielectric filler respectively. Figure 52A and Figure 52B The planarization process using, for example, chemical mechanical polishing, is shown to affect the planarization process in... Figure 51A and Figure 51B The structure shown is the result of flattening the original structure.

[0368] In embodiments of this disclosure, openings are formed in the structure of the semiconductor device without damaging or exposing it. Structure near the opening Examples include source / drain structures, interlayer dielectrics, hard masking layers above the interlayer dielectrics, metal gates, and sacrificial gates. Openings can have high aspect ratios by minimizing etchant head loss. Openings can be formed deep within the substrate below the source / drain regions and below the shallow trench isolation regions to address current leakage issues. It should be understood that not all advantages need to be discussed herein, and not all implementations or embodiments require specific advantages; other implementations or embodiments may offer different advantages.

[0369] According to embodiments of this disclosure, a method of manufacturing a semiconductor device includes performing an etching process on a structure. The structure includes a substrate, a shallow trench isolation region disposed above the substrate, and a plurality of fins spaced apart above the substrate and projecting from the shallow trench isolation region. The plurality of fins extend in a first direction and include a plurality of channel regions and a plurality of recesses on opposite sides of these channel regions. A plurality of metal gates are disposed above the substrate and the shallow trench isolation region. The plurality of metal gates extend in a second direction intersecting the first direction and contacting the channel regions. A source / drain structure is disposed in the recesses. The etching process includes extending an opening through one of the plurality of metal gates by removing a segment of the metal gate extending in the second direction; extending an opening through one of the plurality of fins by removing a segment of the fin extending in the first direction; extending an opening through one of the shallow trench isolation regions by removing a portion of the shallow trench isolation region; and extending the opening into the substrate by removing a portion of the substrate. The opening extends to a depth in the substrate below the shallow trench isolation region and the source / drain structure. During the etching process, one or more of the following conditions are met: the etching pressure when the extension opening passes through the metal gate is lower than the etching pressure when the extension opening passes through the fin; the etching pressure when the extension opening passes through the fin is lower than the etching pressure when the extension opening passes through the shallow trench isolation region; the etching pressure when the extension opening passes through the shallow trench isolation region is lower than the etching pressure when the extension opening enters the substrate; the etching temperature when the extension opening passes through the metal gate is higher than the etching temperature when the extension opening passes through the fin; the etching temperature when the extension opening passes through the fin is higher than the etching temperature when the extension opening passes through the shallow trench isolation region; and the etching temperature when the extension opening passes through the shallow trench isolation region is higher than the etching temperature when the extension opening enters the substrate. When the extension opening passes through the metal gate, the etch selectivity of silicon relative to one or more silicon oxides and silicon nitrides is lower than the etch selectivity when the extension opening passes through the fin. When the extension opening passes through the fin, the etch selectivity of silicon relative to one or more silicon oxides and silicon nitrides is lower than the etch selectivity when the extension opening passes through the shallow trench isolation region. When the extended opening passes through the shallow trench isolation region, the etch selectivity of silicon relative to one or more silicon oxides and silicon nitrides is lower than the etch selectivity when the extended opening extends into the substrate; and the etch pressure is less than 50 mTorr during the periods when the extended opening passes through the metal gate, through the fin, through the shallow trench isolation region, and into one or more of the substrate. In one embodiment, this section of the fin is removed, forming the opening between a pair of source / drain structures in a plurality of source / drain structures, without exposing the pair of source / drain structures along the first direction. In one embodiment, prior to the etching process, the structure further includes a hard mask layer that isolates a section of the metal gate along the second direction from a remaining portion of the metal gate.In one embodiment, extending the opening by removing the segment of the metal gate does not expose the remaining portion of the metal gate along the second direction. In one embodiment, prior to the etching process, the structure further includes a segment of a semiconductor layer above the segment of the metal gate and the remaining portion of the semiconductor layer above the remaining portion of the metal gate, and the segment of the semiconductor layer is isolated from the remaining portion of the semiconductor layer via a hard mask layer. In one embodiment, the etching process further includes removing the segment of the semiconductor layer without exposing the remaining portion of the semiconductor layer along the second direction. In one embodiment, the etching temperature when the extended opening passes through the metal gate is higher than the etching temperature when the extended opening passes through the fin. In one embodiment, the etching temperature when the extended opening passes through the shallow trench isolation region is higher than the etching temperature when the extended opening extends into the substrate. In one embodiment, the etching pressure when the extended opening passes through the metal gate is lower than the etching pressure when the extended opening passes through the fin. In one embodiment, the etching pressure when the extended opening passes through the shallow trench isolation region is lower than the etching pressure when the extended opening extends into the substrate.

[0370] According to another embodiment, a method of manufacturing a semiconductor device includes performing an etching process on the structure of the semiconductor device. The structure of the semiconductor device includes a substrate, fins configured to extend across the substrate in a first direction and include a channel region. A shallow trench isolation region is disposed around the fins, with the fins protruding from the shallow trench isolation region. A gate structure extends along a second direction intersecting the first direction. The gate structure covers the channel region. Source / drain structures are formed on opposite sides of the gate structure in the channel region. The etching process includes extending an opening through the gate structure by removing a segment of the gate structure extending in the second direction, extending an opening through the fins by removing a segment of the fins extending in the first direction between the plurality of source / drain structures without exposing these source / drain structures, extending an opening through the shallow trench isolation region by removing a portion of the shallow trench isolation region, and extending an opening into the substrate by removing a portion of the substrate. This opening extends to a depth in the substrate below the shallow trench isolation region and the source / drain structures. During the etching process, one or more of the following conditions are met: the etching pressure when extending the opening through the gate structure is lower than the etching pressure when extending the opening via removing the stacked section; the etching pressure when extending the opening via removing the stacked section is lower than the etching pressure when extending the opening through the shallow trench isolation region; the etching pressure when extending the opening through the shallow trench isolation region is lower than the etching pressure when extending the opening into the substrate; the etching temperature when extending the opening through the gate structure is higher than the etching temperature when extending the opening via removing the stacked section; the etching temperature when extending the opening via removing the stacked section is higher than the etching temperature when extending the opening through the shallow trench isolation region; and the etching temperature when extending the opening through the shallow trench isolation region is higher than the etching temperature when extending the opening into the substrate. In one embodiment, the structure further includes a hard mask layer that isolates this section of the gate structure along the second direction from the remainder of the gate structure. In one embodiment, removing this section of the gate structure does not expose the remainder of the gate structure along the second direction. In one embodiment, the etching pressure when extending the opening through the gate structure is lower than the etching pressure when extending the opening by removing this section of the stack. In one embodiment, the etching temperature when extending the opening through the gate structure is lower than the etching temperature when extending the opening by removing this section of the stack. In one embodiment, the etching temperature when extending the opening through the shallow trench isolation region is higher than the etching temperature when extending the opening into the substrate.

[0371] In another embodiment, a method of manufacturing a semiconductor device includes performing an etching process on a structure of the semiconductor device. The structure includes a substrate, a plurality of stacks including multiple layers of semiconductor material formed over the substrate. The stacks extend along a first direction and include a channel region. A plurality of gate structures are formed over the substrate and extend along a second direction intersecting the first direction, the gate structures covering the channel region. A plurality of source / drain structures are formed along the first direction on opposite sides of the channel region. A plurality of shallow trench isolation regions are disposed around the plurality of stacks. The etching process includes extending an opening through a gate structure of the plurality of gate structures by removing a segment of a gate structure extending in the second direction, extending an opening without exposing the pair of source / drain structures along the first direction by removing a segment of a plurality of stacks between a pair of source / drain structures in the plurality of source / drain structures, extending an opening through a shallow trench isolation region of the plurality of shallow trench isolation regions by removing a portion of the shallow trench isolation region, and extending an opening into the substrate by removing a portion of the substrate. The opening extends to a depth in the substrate below the plurality of shallow trench isolation regions and the source / drain structures. During the etching process, one or more of the following conditions are met: the etching pressure when the extended opening passes through the gate structure is lower than the etching pressure when the opening is extended by removing the stacked segment; the etching pressure when the opening is extended by removing the stacked segment is lower than the etching pressure when the extended opening passes through the shallow trench isolation region; the etching pressure when the extended opening passes through the shallow trench isolation region is lower than the etching pressure when the extended opening extends into the substrate; the etching temperature when the extended opening passes through the gate structure is higher than the etching temperature when the opening is extended by removing the stacked segment; the etching temperature when the opening is extended by removing the stacked segment is higher than the etching temperature when the extended opening passes through the shallow trench isolation region; the etching temperature when the extended opening passes through the shallow trench isolation region is higher than the etching temperature when the extended opening extends into the substrate. The etching temperature at which the opening extends into the substrate is such that the etch selectivity of silicon relative to one or more silicon oxides and silicon nitrides is lower when the opening extends through the gate structure than when extending the opening via the removal of the stacked section, when extending the opening via the removal of a section of the stack, when extending the opening through the shallow trench isolation region, when extending the opening via the shallow trench isolation region, and when extending the opening into the substrate, and the etch pressure is less than 50 mTorr. In one embodiment, the structure further includes a hard mask layer that isolates this section of the gate structure along the second direction from a remaining portion of the gate structure. In one embodiment, removing this section of the gate structure does not expose the remaining portion of the gate structure along the second direction.In one embodiment, the etch pressure when extending the opening through the gate structure is lower than the etch pressure when extending the opening by removing this stacked segment.

[0372] In another embodiment, the semiconductor device includes a substrate and a plurality of shallow trench isolation regions disposed on the substrate. The device also includes a plurality of fins spaced apart on the substrate and projecting from the plurality of shallow trench isolation regions. The plurality of fins extend in a first direction and include channel regions and a plurality of recesses disposed on opposite sides of the channel regions. The device also includes a plurality of metal gates disposed above the substrate and the shallow trench isolation regions. The plurality of metal gates extend in a second direction and contact the channel regions of the plurality of fins. The device also includes source / drain structures disposed in the recesses. The device includes an opening filled with a dielectric structure. The opening extends into the substrate to a depth below the shallow trench isolation regions and the source / drain structures. The opening divides one of the plurality of fins between a pair of source / drain structures in the plurality of source / drain structures along the first direction, and divides one of the plurality of metal gates along the second direction. When viewed in a cross-section taken along the second direction, the width of the opening decreases from a level at the top of the plurality of fins to a level at the bottom of the plurality of shallow trench isolation regions. In one embodiment, the dielectric structure does not contact the paired source / drain structures along a first direction. In one embodiment, the dielectric structure does not contact the metal gates along a second direction. In one embodiment, the semiconductor device further includes an interlayer dielectric layer disposed above the source / drain structures, and the dielectric structure does not contact the interlayer dielectric layer disposed above the paired source / drain structures on opposite sides of the opening along the first direction. In one embodiment, the semiconductor device further includes a first hard mask layer disposed above the interlayer dielectric layer, and the dielectric structure does not contact the first hard mask layer formed on the interlayer dielectric layer disposed above the paired source / drain structures. In one embodiment, the semiconductor device further includes a semiconductor layer formed above the plurality of metal gates and around the interlayer dielectric layer and the first hard mask layer. In one embodiment, the semiconductor device further includes a gate dicing structure that spaces the opening from the semiconductor layer and the metal gates along a second direction. In one embodiment, the semiconductor device further includes a second hard mask layer lining the gate dicing structure. In one embodiment, the opening includes a plurality of trenches that pass through a shallow trench isolation region and a substrate within a plurality of shallow trench isolation regions, and the plurality of trenches are spaced apart along a second direction. In one embodiment, the width of the opening gradually and continuously decreases from a level at the top of the plurality of fins to a level at the bottom of the plurality of shallow trench isolation regions.

[0373] In another embodiment, the semiconductor device includes a substrate and a field-effect transistor (FET) device disposed on the substrate. The FET device includes fins disposed across the substrate in a first direction. The fins include a channel region. The FET device also includes a shallow trench isolation region disposed around the fins, with the fins protruding from the shallow trench isolation region. The FET device further includes a gate structure extending along a second direction intersecting the first direction. The gate structure covers the channel region. The FET device also includes a plurality of source / drain structures formed on opposite sides of the gate structure in the channel region. The FET device further includes an opening filled with a dielectric structure, and this opening extends into the substrate to a depth below the source / drain structures and below the shallow trench isolation region. The opening divides the fins along the first direction and the gate structure along the second direction. When viewed in a cross-section taken along the second direction, the width of the opening decreases from a level at the top of the fins to a level at the bottom of the shallow trench isolation region. In one embodiment, the gate structure includes a gate dielectric structure or a metal gate. In one embodiment, the dielectric structure does not contact the plurality of source / drain structures along a first direction. In one embodiment, the semiconductor device further includes an interlayer dielectric layer formed over the source / drain structures, and the dielectric structure does not contact the interlayer dielectric layer along the first direction. In one embodiment, the semiconductor device further includes a semiconductor layer formed over a gate structure, and the dielectric structure does not contact the semiconductor layer along a second direction. In one embodiment, the width of the opening gradually and continuously decreases from a level at the top of the fin to a level at the bottom of the shallow trench isolation region.

[0374] In another embodiment, the semiconductor device includes a substrate and a plurality of adjacent field-effect transistor (FET) devices on the substrate. Each of the adjacent FET devices includes a stack comprising multiple layers of semiconductor material, such that the stack extends along a first direction and includes a channel region. Each of the adjacent FET devices also includes a metal gate extending along a second direction intersecting the first direction, such that the metal gate covers the channel region. Each of the adjacent FET devices also includes a plurality of source / drain epitaxial structures formed on multiple opposing sides of the gate in the channel region. Each of the adjacent FET devices also includes a plurality of shallow trench isolation regions disposed around the stack. The semiconductor device also includes an opening filled with a dielectric structure. The opening is formed between the adjacent FET devices. The opening extends into the substrate to a depth below the source / drain epitaxial structures and the shallow trench isolation regions. When viewed from a cross-section taken along the second direction, the width of the opening decreases from a level at the top of the plurality of stacks of adjacent FET devices to a level at the bottom of the shallow trench isolation regions. In one embodiment, the dielectric structure does not contact the metal gates of two adjacent field-effect transistor devices along the second direction. In one embodiment, the semiconductor device further includes a hard mask layer along the second direction between the opening and the metal gates of the two adjacent field-effect transistor devices. In one embodiment, the semiconductor device further includes an interlayer dielectric layer formed over the source / drain structure such that the dielectric structure does not contact the interlayer dielectric layer along the first direction. In one embodiment, the width of the opening gradually and continuously decreases from a level at the top of the stack to a level at the bottom of the shallow trench isolation region.

[0375] The foregoing outlines features of several implementation methods or embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they may readily use this disclosure as a basis for the design and modification of other processes and structures to achieve the same purpose and / or the same advantages as the implementation methods or embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: One substrate; Multiple shallow trench isolation zones are disposed on this substrate. Multiple fins are spaced apart above the substrate and protrude from the multiple shallow trench isolation regions, the multiple fins extending along a first direction and including multiple channel regions and multiple recesses on multiple opposite sides of the multiple channel regions; Multiple metal gates are disposed above the substrate and the shallow trench isolation region, the multiple metal gates extending along a second direction and contacting the multiple channel regions of the multiple fins; Multiple source / drain structures are disposed in the multiple recesses; as well as An opening, filled with a dielectric structure, extends into the substrate to a depth below the plurality of shallow trench isolation regions and the plurality of source / drain structures. The opening divides one of the plurality of fins between a pair of source / drain structures along the first direction. The opening divides one of the plurality of metal gates along the second direction. When viewed from a cross-section taken along the second direction, the width of the opening decreases from one level at the tops of the plurality of fins to one level at the bottoms of the plurality of shallow trench isolation regions.

2. The semiconductor device as claimed in claim 1, characterized in that, The dielectric structure does not contact the paired source / drain structure along the first direction.

3. The semiconductor device as claimed in claim 1, characterized in that, The dielectric structure does not contact the metal gate along the second direction.

4. The semiconductor device as claimed in claim 1, characterized in that, It also includes a plurality of interlayer dielectric layers disposed above the plurality of source / drain structures, wherein the dielectric structures do not contact the plurality of interlayer dielectric layers disposed above the paired source / drain structures on opposite sides of the opening along the first direction.

5. The semiconductor device as claimed in claim 4, characterized in that, It also includes a plurality of first hard masking layers disposed above the interlayer dielectric layer, wherein the dielectric structure does not contact the plurality of first hard masking layers formed on the interlayer dielectric layer disposed above the paired source / drain structures.

6. The semiconductor device as claimed in claim 1, characterized in that, The width of the opening gradually and continuously decreases from the level at the tops of the plurality of fins to the level at the bottoms of the plurality of shallow groove isolation areas.

7. A semiconductor device, characterized in that, Include: A substrate; and A field-effect transistor (FET) device is disposed on the substrate, the FET device comprising: A fin is disposed across the substrate in a first direction, the fin including a channel region; A shallow groove isolation area is provided around the fin, the fin protruding from the shallow groove isolation area; A gate structure extends along a second direction intersecting the first direction, and the gate structure covers the channel region; Multiple source / drain structures are formed on multiple opposite sides of the gate structure in the channel region; and An opening is filled with a dielectric structure and extends into the substrate to a depth below the plurality of source / drain structures and below the shallow trench isolation region. The opening divides the fin along the first direction and the gate structure along the second direction. Specifically, when viewed at a cross-section taken along the second direction, the width of the opening decreases from a level at the top of the fin to a level at the bottom of the shallow groove isolation area.

8. The semiconductor device as claimed in claim 7, characterized in that, The width of the opening gradually and continuously decreases from the level at the top of the fin to the level at the bottom of the shallow groove isolation area.

9. A semiconductor device, characterized in that, Include: One substrate; A plurality of adjacent field-effect transistor devices are disposed on the substrate; and each of the plurality of adjacent field-effect transistor devices includes: A stack comprising multiple layers of semiconductor material, the stack extending along a first direction and including a channel region; A metal gate extends along a second direction intersecting the first direction, and the metal gate covers the channel region; Multiple source / drain epitaxial structures are formed on multiple opposite sides of the gate in the channel region; and Multiple shallow trench isolation zones are set around the stack; as well as An opening filled with a dielectric structure is formed between the plurality of adjacent field-effect transistor devices and extends into the substrate to a depth below the plurality of source / drain epitaxial structures and the plurality of shallow trench isolation regions. When viewed from a cross-section taken along the second direction, the width of the opening decreases from one level at the top of the plurality of stacks of the plurality of adjacent field-effect transistor devices to one level at the bottom of the plurality of shallow trench isolation regions.

10. The semiconductor device as claimed in claim 9, characterized in that, The semiconductor device also includes a hard mask layer along the second direction between the opening and the metal gates of the plurality of adjacent field-effect transistor devices.

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