Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises at least one transistor disposed on a base, the transistor comprising: a bottom electrode disposed on the base, comprising at least one of a first electrode and a second electrode; an auxiliary conductive part disposed on a side of the bottom electrode away from the base; an active layer disposed on a side of the auxiliary conductive part away from the base and in contact with the auxiliary conductive part, comprising a channel region and source-drain connection regions located on both sides of the channel region, the first electrode and the second electrode being connected with the source-drain connection regions respectively; a second insulating layer disposed on a side of the active layer away from the base; a normal projection of the second insulating layer on the base covers a normal projection of the channel region on the base; a gate electrode disposed on a side of the second insulating layer away from the base; the channel region is an area where the gate electrode and the active layer intersect in a direction perpendicular to the base; wherein a normal projection of the auxiliary conductive part on the base is located within a range of a normal projection of the source-drain connection region on the base.

Description

Technical Field

[0001] This utility model relates to, but is not limited to, display technology, and particularly to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. With the continuous development of display technology, display devices using OLEDs as light-emitting elements and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Utility Model Content

[0003] In a first aspect, embodiments of the present invention provide a display substrate, comprising: at least one transistor disposed on a substrate, the transistor comprising: a bottom electrode disposed on the substrate, including at least one of a first electrode and a second electrode; an auxiliary conductive portion disposed on the side of the bottom electrode away from the substrate; an active layer disposed on the side of the auxiliary conductive portion away from the substrate and in contact with the auxiliary conductive portion, including a channel region and source-drain connection regions located on both sides of the channel region, the first electrode and the second electrode being respectively connected to the source-drain connection regions; a second insulating layer disposed on the side of the active layer away from the substrate; the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the channel region on the substrate; a gate electrode disposed on the side of the second insulating layer away from the substrate; the channel region being the region where the gate electrode and the active layer overlap in a direction perpendicular to the substrate; wherein the orthographic projection of the auxiliary conductive portion on the substrate is located within the range of the orthographic projection of the source-drain connection regions on the substrate.

[0004] In one exemplary embodiment, a light-shielding portion is further included, which is disposed in the same layer as the bottom electrode, and the orthographic projection of the light-shielding portion on the substrate covers the orthographic projection of the channel region on the substrate.

[0005] In one exemplary embodiment, a first insulating layer is further included, which is located on the side of the light-shielding portion and the bottom electrode away from the substrate, and on the side of the auxiliary conductive portion close to the substrate.

[0006] In one exemplary embodiment, the source-drain connection region includes a first connection region and a second connection region located on both sides of the channel region; the first electrode and the second electrode are respectively connected to the source-drain connection region, including: one of the first electrode and the second electrode is connected to the first connection region, and the other is connected to the second connection region.

[0007] In one exemplary embodiment, the first insulating layer includes a plurality of vias, and the bottom electrode is connected to the corresponding source-drain connection region through the vias.

[0008] In one exemplary embodiment, the minimum size of the via is greater than or equal to 3.6 micrometers in the plane of the substrate.

[0009] In one exemplary embodiment, the auxiliary conductive portion includes at least one of a first auxiliary conductive portion and a second auxiliary conductive portion; one of the first auxiliary conductive portion and the second auxiliary conductive portion is connected to the first connection region, and the other is connected to the second connection region.

[0010] In one exemplary embodiment, a third insulating layer is further included, disposed on the side of the gate electrode away from the substrate; the orthographic projection of the third insulating layer on the substrate covers the orthographic projection of the at least one transistor on the substrate.

[0011] In one exemplary embodiment, the bottom electrode includes one of the first electrode and the second electrode, the other of which is located on the side of the third insulating layer away from the substrate.

[0012] In one exemplary embodiment, a first signal line is further included; the first signal line is connected to the first or second terminal of at least one of the transistors.

[0013] In one exemplary embodiment, the first signal line is integrally structured with the first or second electrode of at least one of the transistors.

[0014] In one exemplary embodiment, a second signal line is further included; the second signal line is connected to the gate electrode of at least one of the transistors.

[0015] In one exemplary embodiment, the second signal line and the gate electrode of at least one of the transistors are integrally formed.

[0016] In one exemplary embodiment, the active layer is made of an oxide semiconductor.

[0017] The second invention, according to an embodiment of the present invention, also provides a display device, including: a display substrate as described above.

[0018] Other advantages of this invention can be realized and obtained through the solutions described in the specification and drawings. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solution of this utility model and do not constitute a limitation on the technical solution of this utility model.

[0020] Figure 1 This is a schematic diagram of a top-gate thin-film transistor.

[0021] Figure 2 This is a top view of the display substrate in an exemplary embodiment;

[0022] Figure 3 As an exemplary implementation Figure 2 Sectional view along direction AA;

[0023] Figure 4 This is a top view of the display substrate after the light-shielding layer pattern has been formed in an exemplary embodiment;

[0024] Figure 5 As an exemplary implementation Figure 4 A sectional view along direction AA;

[0025] Figure 6 This is a top view of a display substrate after an auxiliary conductive layer pattern has been formed in an exemplary embodiment.

[0026] Figure 7 As an exemplary implementation Figure 6 Sectional view along direction AA;

[0027] Figure 8 This is a top view of a display substrate after a semiconductor layer pattern has been formed in an exemplary embodiment;

[0028] Figure 9 As an exemplary implementation Figure 8 A sectional view along direction AA;

[0029] Figure 10 After forming the second insulating layer and gate electrode layer pattern in one exemplary embodiment Figure 2 A sectional view along direction AA;

[0030] Figure 11 In one exemplary embodiment, the active layer is made conductive. Figure 2 A sectional view along direction AA. Detailed Implementation

[0031] This utility model describes several embodiments, but these descriptions are exemplary and not restrictive, and many more embodiments and implementations are possible within the scope of the embodiments described herein, which will be apparent to those skilled in the art. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with or in lieu of any other feature or element in any other embodiment.

[0032] This invention includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this invention can also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this invention can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0033] Furthermore, in describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this utility model.

[0034] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, one aspect of the invention is not necessarily limited to these dimensions, and the shape and size of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of the invention is not limited to the shapes or values ​​shown in the drawings.

[0035] The ordinal numbers "first," "second," and "third" used in this specification are provided to avoid confusion among the constituent elements, not to limit the quantity. In this utility model, "multiple" refers to two or more items.

[0036] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this utility model. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as needed.

[0037] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0038] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0039] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the meaning of these terms in this invention according to the context. "Electrical connection" includes situations where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the term "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0040] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0041] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0042] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0043] In this utility model, "approximately" refers to a value that is not strictly limited and is within the range of allowable process and measurement errors.

[0044] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0045] In display technology, thin-film transistors (TFTs) are widely used in various display devices as integrated elements for switching control, pixel driving circuits, and peripheral driving circuits. TFTs include amorphous silicon TFTs, polycrystalline silicon TFTs, and oxide semiconductor TFTs. Amorphous silicon's low mobility, typically below 1 cm² / V·s, limits its performance. Polycrystalline silicon suffers from poor uniformity, complex and costly fabrication processes, and sensitivity to visible light, making it unsuitable for large-size and high-resolution flat panel displays. In contrast, oxide TFTs utilize oxide semiconductors as their active layer. Oxide TFTs offer higher mobility, better uniformity, lower processing temperatures, high transmittance in the visible light region, and suitability for flexible displays, demonstrating broad application prospects.

[0046] Thin-film transistors (TFTs) are classified into bottom-gate TFTs and top-gate TFTs based on the positional relationship between the gate electrode and the active layer. In bottom-gate TFTs, the gate electrode is located below the active layer, while in top-gate TFTs, the gate electrode is located above the active layer. During fabrication, bottom-gate TFTs are fabricated using back-channel etching (BCE), which can easily lead to over-etching, affecting the device channel and negatively impacting TFT performance. Furthermore, the back-side exposure technique used in bottom-gate TFTs makes self-alignment difficult, resulting in large overlapping areas and significant overlap capacitance. This hinders channel size reduction and reduces the operating speed of the driving circuit, making them unsuitable for driving high-resolution active-matrix organic light-emitting diode (AMOLED) displays.

[0047] Figure 1 This is a schematic diagram of a top-gate thin-film transistor. Figure 1 As shown, the top-gate thin-film transistor includes an active layer 21, a gate electrode 22, a first electrode 23, and a second electrode 24 sequentially disposed on a substrate 10. The first electrode 23 and the second electrode 24 are disposed on the same layer and are respectively connected to both ends of the active layer 21. A first insulating layer 11 is disposed between the substrate 10 and the active layer 21, a second insulating layer 12 is disposed between the active layer 21 and the gate electrode 22, and a third insulating layer 13 and a fourth insulating layer 14 are disposed between the gate electrode 22 and the first electrode 23. The first insulating layer 11 can be called a buffer layer, the second insulating layer 12 can be called a gate insulating (GI) layer, the third insulating layer 13 can be called a passivation (PVX) layer, and the fourth insulating layer 14 can be called an interlayer insulating (ILD) layer. Figure 1 After the gate electrode 22 is formed in the thin-film transistor, the active layer 21 needs to be conductiveized from the side of the gate electrode 22 away from the substrate 10, such as through plasma treatment or hydrogen doping. During the conductiveization process, the gate electrode 22 can shield the active layer 21 located below it. The active layer 21 shielded by the gate electrode 22 forms a channel region, while the active layer 21 not shielded by the gate electrode 22 can form good contact with the subsequently formed first electrode 23 and second electrode 24 after the conductiveization process. It can be seen that during the conductiveization process of the active layer 21, the gate electrode 22 of the top-gate thin-film transistor can play a self-aligning role, which can avoid the formation of overlapping regions and significantly improve the alignment accuracy between the gate electrode and the channel region below. The second insulating layer 12 can also protect the active layer 21, preventing over-etching damage to the active layer 21, resulting in better electrical characteristics of the top-gate thin-film transistor.

[0048] However, during the conductive treatment of the active layer 21, hydrogen easily diffuses into the channel region, causing the size of the transistor's channel region to decrease. For example... Figure 1As shown, within the plane of substrate 10, the active layer 21, shielded by gate electrode 22, has a size of L1 + 2 * L2. This size represents the ideal channel region size of the transistor. However, due to hydrogen diffusion, hydrogen also appears in the L2 region at the edge of the channel region, resulting in a final channel region size of L1. Changes in the channel region size affect the electrical characteristics of the transistor and ultimately the display effect of the display substrate. Furthermore, the higher the resolution (PPI) of the display substrate, the greater the impact.

[0049] This utility model embodiment provides a display substrate, including at least one transistor disposed on the substrate, the transistor comprising:

[0050] A bottom electrode, disposed on the substrate, includes at least one of a first electrode and a second electrode;

[0051] An auxiliary conductive part is disposed on the side of the bottom electrode away from the substrate;

[0052] An active layer is disposed on the side of the auxiliary conductive portion away from the substrate and in contact with the auxiliary conductive portion, including a channel region and source-drain connection regions located on both sides of the channel region, wherein the first electrode and the second electrode are respectively connected to the source-drain connection regions;

[0053] A second insulating layer is disposed on the side of the active layer away from the substrate; the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the channel region on the substrate.

[0054] A gate electrode is disposed on the side of the second insulating layer away from the substrate; the channel region is the area where the gate electrode and the active layer overlap in a direction perpendicular to the substrate;

[0055] Wherein, the orthographic projection of the auxiliary conductive part on the substrate is within the range of the orthographic projection of the source-drain connection region on the substrate.

[0056] The display substrate provided in this embodiment of the present invention provides an auxiliary conductive part on the side of the source-drain connection region of the active layer close to the substrate, and a second insulating layer covering the channel region on the side of the active layer away from the substrate. The auxiliary conductive part and the second insulating layer can protect the channel region. During the conductive treatment of the active layer, it helps to prevent hydrogen atoms or hydrogen ions from diffusing into the channel region, which can ensure the accuracy of the channel region's dimensions, thereby helping to ensure the electrical characteristics of the transistor.

[0057] Figure 2This is a top view of a display substrate in an exemplary embodiment, illustrating the structure of the light-shielding part and the transistor, and the bottom electrode includes only one of the first electrode 24 and the second electrode 25, and the auxiliary conductive part includes the first auxiliary conductive part 34 and the second auxiliary conductive part 35. Figure 3 As an exemplary implementation Figure 2 A sectional view along direction AA.

[0058] like Figure 2 As shown, the display substrate includes a first signal line 32, a second signal line 220, a light-shielding portion 31, and a transistor. The light-shielding portion 31 at least blocks the channel region of the transistor. The transistor includes a first electrode 24, a second electrode 25, a first auxiliary conductive portion 34, a second auxiliary conductive portion 35, an active layer 21, and a gate electrode 22. The first signal line 32 can be connected to either the first electrode 24 or the second electrode 25 of the transistor; for example, the first signal line 32 can be integrally formed with the first electrode 24 or the second electrode 25 of the transistor located in its own extending direction. The second signal line 220 can be connected to the gate electrode 22 of the transistor; for example, the second signal line 220 can be integrally formed with the gate electrode 22 of the transistor located in its own extending direction. In the direction perpendicular to the substrate 10, the portion where the second signal line 220 overlaps with the active layer 21 can form the gate electrode 22. The orthographic projection of the gate electrode 22 onto the substrate 10 can be located between the orthographic projections of the first auxiliary conductive portion 34 and the second auxiliary conductive portion 35 onto the substrate 10.

[0059] Combination Figure 3 As shown, in a direction perpendicular to the substrate 10, the display substrate may include a light-shielding layer, a first insulating layer 11, an auxiliary conductive layer, an active layer 21, a second insulating layer 12, a gate electrode layer, and a third insulating layer 13, sequentially disposed therefrom. The light-shielding layer includes the bottom electrode of the transistor (…). Figure 3The diagram shows a first electrode 24 or a second electrode 25, a light-shielding portion 31, and a first signal line 32. The auxiliary conductive layer includes a first auxiliary conductive portion 33 and a second auxiliary conductive portion 34. The gate electrode layer includes a gate electrode 22 and a second signal line 220. The orthographic projections of the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34 onto the substrate 10 at least partially overlap with the orthographic projection of the active layer 21 onto the substrate 10. For example, the orthographic projections of the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34 onto the substrate 10 may be within the range of the orthographic projection of the active layer 21 onto the substrate 10. The orthographic projections of the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34 onto the substrate 10 may also be within the range of the orthographic projection of the second insulating layer 12 onto the substrate 10. In a plane perpendicular to the substrate 10, the active layer 21 includes a channel region G and source-drain connection regions located on both sides of the channel region G. The orthographic projections of the first auxiliary conductive part 33 and the second auxiliary conductive part 34 on the substrate 10 can be located within the range of the orthographic projections of the source-drain connection regions on the substrate 10, and the orthographic projection of the channel region G on the substrate 10 can be located within the range of the orthographic projections of the second insulating layer 12 on the substrate 10. Research has shown that hydrogen atoms or hydrogen ions move more easily in the direction perpendicular to the substrate 10, leading to hydrogen diffusion. In this embodiment, a first auxiliary conductive part 33 and a second auxiliary conductive part 34 are provided on the side of the source-drain connection region of the active layer 21 near the substrate 10, and a second insulating layer 12 covering the channel region G is provided on the side of the active layer 21 away from the substrate 10. The first auxiliary conductive part 33, the second auxiliary conductive part 34, and the second insulating layer 12 can protect the channel region G on both sides in the direction perpendicular to the substrate 10. During the conductive treatment of the active layer 21, it helps to prevent hydrogen atoms or hydrogen ions from diffusing into the channel region G, which can ensure the accuracy of the dimensions of the channel region G, thereby helping to ensure the electrical characteristics of the transistor. Even when the resolution of the display substrate is high and the size of a single transistor is small, the size of the channel region G of each transistor can be guaranteed to be uniform, ensuring the display effect of the display substrate. Furthermore, the active layer 21 is in contact with the first auxiliary conductive part 33 and the second auxiliary conductive part 34 respectively. The first auxiliary conductive part 33 and the second auxiliary conductive part 34 are conductive materials, which helps to improve the conductivity of the active layer 21 in the source-drain connection region, reduce the impedance of the transistor, and improve the electrical performance of the transistor. Figure 2 and Figure 3 The illustration takes an example where a first auxiliary conductive part 33 and a second auxiliary conductive part 34 are respectively provided on both sides of the channel region G along the direction parallel to the substrate 10. In this case, both sides of the channel region G along the direction parallel to the substrate 10 can be effectively protected. Combined with... Figure 1Regarding the dimensional relationships mentioned above, in this embodiment, the final channel region G has a size of L1 + 2 * L2, and the alignment between the channel region G and the gate electrode 22 is precise. In other embodiments, only one of the first auxiliary conductive part 33 and the second auxiliary conductive part 34 can be provided on the display substrate, and the final channel region G has a size of L1 + L2, compared to... Figure 1 The solution can also increase the size of the channel region G by L2.

[0060] In an exemplary embodiment, the source-drain connection region includes a first connection region S1 and a second connection region S2. One of the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34 is connected to the first connection region S1, and the other is connected to the second connection region S2. One of the first electrode 24 and the second electrode 25 is connected to the first connection region S1, and the other is connected to the second connection region S2.

[0061] In an exemplary embodiment, the active layer 21 and the first electrode 24 are connected via vias, and the active layer 21 and the second electrode 25 are connected via vias. By setting the bottom electrode and the light-shielding part 31 in the same layer, the active layer 21 only needs to be connected to the bottom electrode through a via provided on the first insulating layer 11, which can eliminate the need for a fourth insulating layer, reduce the number of film layers in the display substrate, thereby reducing the number of masks used in the manufacturing process of the display substrate, reducing production costs, and increasing production capacity. Figure 2 and Figure 3 The illustration uses one of the first electrode 24 and the second electrode 25 as an example of a bottom electrode. The other of the first electrode 24 and the second electrode 25 can be located on the side of the third insulating layer 13 away from the substrate 10, and can be connected to another source / drain connection region of the active layer 21 through a via, thereby facilitating subsequent connection with structures such as light-emitting elements. In other embodiments, the bottom electrode may include the first electrode 24 and the second electrode 25. The active layer 21 only needs to be connected to the first electrode 24 and the second electrode 25 through a via provided on the first insulating layer 11, which helps to save fabrication steps. The first electrode 24 or the second electrode 25 can be subsequently connected to other structures through the via.

[0062] In an exemplary embodiment, the first signal line 32 can transmit data signals and the second signal line 220 can transmit scanning signals to drive the light-emitting element to emit light. The signals transmitted by the first signal line 32 and the second signal line 220 can be designed according to the type of display substrate, and this utility model does not limit this.

[0063] Research has found that, assuming all other structures are identical, Figure 1 The hydrogen diffusion length L2 of the transistor in the display substrate shown is approximately 1.52 micrometers, while Figure 3The transistors in the display substrate with the structure shown do not experience hydrogen diffusion, and... Figure 1 The sheet resistance of the active layer of the transistor in the display substrate shown is approximately 1000 Ω / hole. In comparison, Figure 3 The sheet resistance of the active layer of the transistor in the display substrate shown is approximately 400 Ω / Ω. It can be seen that, compared to... Figure 1 The transistors in the display substrate shown in the diagram. Figure 3 The transistors in the display substrate with the structure shown have superior electrical characteristics.

[0064] The following is an illustrative description of the fabrication process of a display substrate. The "patterning process" described in this invention includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This invention does not limit the methods used. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." In this invention, "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In an exemplary embodiment of this invention, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0065] In an exemplary embodiment Figure 2 and Figure 3 The fabrication process of the display substrate can include the following steps.

[0066] (1) Forming a light-shielding layer pattern. In an exemplary embodiment, forming a light-shielding layer pattern may include:

[0067] A first conductive thin film is deposited on a substrate 10, and the first conductive thin film is patterned to form a light-shielding portion 31, a first signal line 32, and a bottom electrode, thereby forming a light-shielding layer pattern. The light-shielding layer pattern may include at least the light-shielding portion 31, the first signal line 32, and the bottom electrode, and the bottom electrode may include a first electrode 24 or a second electrode 25. Figure 4 This is a top view of the display substrate after a light-shielding layer pattern has been formed in an exemplary embodiment. Figure 5 As an exemplary implementation Figure 4 A sectional view along direction AA.

[0068] like Figure 4 and Figure 5 As shown, the light-shielding part 31 and the first signal line 32 are spaced apart from each other, and either the first pole 24 or the second pole 25 can be connected to the first signal line 32. For example, either the first pole 24 or the second pole 25 can be integrated with the first signal line 32. Figure 4 The diagram only illustrates the case of a single transistor. In the extension direction of the first signal line 32, the first signal line 32 can be connected to multiple transistors, and this invention does not impose any limitations on this. Figure 4 The example shown is that both the light-shielding part 31 and the bottom electrode are quadrilaterals, and the rectangle of the light-shielding part 31 has rounded corners. In other embodiments, the shapes of the light-shielding part 31 and the bottom electrode can be different, such as circles, ellipses, triangles, other shapes of quadrilaterals, polygons and irregular shapes.

[0069] In an exemplary embodiment, the substrate 10 can be a rigid substrate or a flexible substrate. The rigid substrate can be made of materials such as glass or quartz, and the flexible substrate can be made of materials such as polyimide (PI). The flexible substrate can be a single-layer structure or a laminated structure composed of inorganic material layers and flexible material layers. This utility model does not limit the specific application of this technology.

[0070] In an exemplary embodiment, the first conductive film may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), tungsten (W) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb) or molybdenum-nickel-titanium alloy (MTD). It may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc. The present invention does not limit this.

[0071] (2) Forming a pattern for the first insulating layer and the auxiliary conductive layer. In an exemplary embodiment, forming the auxiliary conductive layer pattern may include:

[0072] A first insulating film and a second conductive film are sequentially deposited on the substrate 10 on which the aforementioned pattern is formed. First, a first opening K1 is formed on the first insulating film and the second conductive film, exposing the surface of the bottom electrode away from the substrate 10. Then, the second conductive film is patterned to form a first insulating layer 11 and a first auxiliary conductive portion 33 and a second auxiliary conductive portion 34 disposed on the first insulating layer 11. The pattern of the auxiliary conductive layer may include the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34. Figure 6 This is a top view of the display substrate after an auxiliary conductive layer pattern has been formed in an exemplary embodiment. Figure 7 As an exemplary implementation Figure 6 A sectional view along direction AA.

[0073] like Figure 6 and Figure 7 As shown, the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34 can be spaced apart from each other, and the orthographic projections of the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34 on the substrate 10 can both overlap with the light-shielding portion 31. The orthographic projections of the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34 on the substrate 10 do not overlap with the orthographic projections of the subsequently formed gate electrode on the substrate 10, so that the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34 will not affect the channel region. Furthermore, the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34 are in contact with the active layer, which can improve the conductivity of the active layer, reduce the impedance, and improve the electrical performance of the transistor.

[0074] In an exemplary implementation, such as Figure 6 and Figure 7 As shown, the first opening K1 can be a square with a side length of b, where b can be greater than or equal to 3.6 micrometers and less than or equal to 6.6 micrometers. For example, b can be greater than or equal to 4 micrometers and less than or equal to 6 micrometers. This size setting ensures sufficient contact area between the first electrode 24 and the second electrode 25 and the subsequently formed active layer, thereby forming good contact. The first opening K1 can also take various shapes as mentioned in step (1) above for the light-shielding part 31.

[0075] In an exemplary implementation, such as Figure 7 As shown, in the direction perpendicular to the substrate 10, the thickness of the first auxiliary conductive part 33 and the second auxiliary conductive part 34 can be d1, which can be greater than or equal to 18 nanometers and less than or equal to 110 nanometers. For example, d1 can be greater than or equal to 20 nanometers and less than or equal to 100 nanometers.

[0076] In an exemplary embodiment, the first insulating film can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single-layer, double-layer, or multi-layer structure. The second conductive film can be made of a transparent conductive material, such as indium tin oxide (ITO).

[0077] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include:

[0078] A semiconductor thin film is deposited on the substrate 10 on which the aforementioned pattern is formed, and the semiconductor thin film is patterned by a patterning process to form an active layer 21 of multiple transistors on the substrate 10. The semiconductor layer pattern may include the active layer 21 of multiple transistors. Figure 8 This is a top view of a display substrate after a semiconductor layer pattern has been formed in an exemplary embodiment. Figure 9 As an exemplary implementation Figure 8 A sectional view along direction AA.

[0079] like Figure 8 and Figure 9 As shown, the orthographic projection of the active layer 21 onto the substrate 10 can cover the orthographic projections of the first auxiliary conductive part 33 and the second auxiliary conductive part 34 onto the substrate 10, thereby forming good contact with the first auxiliary conductive part 33 and the second auxiliary conductive part 34. The orthographic projection of the active layer 21 onto the substrate 10 can cover the orthographic projection of the first opening K1 onto the substrate 10, and the active layer 21 is connected to the first electrode 24 and the second electrode 25 through the first opening K1, respectively. The orthographic projection of the active layer 21 onto the substrate 10 can at least partially overlap with the orthographic projection of the first electrode 24 onto the substrate 10, and the orthographic projection of the active layer 21 onto the substrate 10 can at least partially overlap with the orthographic projection of the second electrode 25 onto the substrate 10. For example, the orthographic projection of the active layer 21 onto the substrate 10 can cover the orthographic projections of the first electrode 24 and the second electrode 25 onto the substrate 10.

[0080] In an exemplary embodiment, the material of the semiconductor thin film can be an amorphous oxide semiconductor (AOS), such as indium tin oxide, aluminum zinc oxide (AZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc. Indium gallium zinc oxide can be, for example, amorphous indium gallium zinc oxide (a-IGZO) or indium gallium zinc tin oxide (IGZTO), etc.

[0081] (4) Forming a second insulating layer and a gate electrode layer pattern. In an exemplary embodiment, forming the second insulating layer and the gate electrode layer pattern may include:

[0082] A second insulating film and a third conductive film are sequentially deposited on the substrate 10 on which the aforementioned pattern is formed. First, a second insulating layer 12 is formed on the substrate 10 using a patterning process, and then a second signal line 220 is formed. In the direction perpendicular to the substrate 10, the portion of the second signal line 220 that overlaps with each active layer 21 serves as the gate electrode 22 of the transistor. A top view of the display substrate after the second insulating layer and gate electrode layer patterns are formed can be found in [reference needed]. Figure 2 As shown, Figure 10 After forming the second insulating layer and gate electrode layer pattern in one exemplary embodiment Figure 2 A sectional view along direction AA.

[0083] Combination Figure 2 and Figure 10 As shown, the second signal line 220 can overlap with multiple active layers 21 in its extension direction, thereby connecting the gate electrodes 22 of multiple transistors to each other. The orthographic projection of each gate electrode 22 on the substrate 10 is located between the orthographic projections of the first auxiliary conductive portion 33 and the second auxiliary conductive portion 34 of the transistor on the substrate 10. The orthographic projection of the second insulating layer 12 on the substrate 10 may not overlap with the orthographic projection of the first electrode 24 on the substrate 10, and the orthographic projection of the second insulating layer 12 on the substrate 10 may not overlap with the orthographic projection of the second electrode 25 on the substrate 10.

[0084] In an exemplary embodiment, the material of the second insulating film can be referred to the foregoing description of the material of the first insulating film, and the material of the third conductive film can be referred to the foregoing description of the material of the first conductive film, and will not be repeated here.

[0085] (5) Conducting a conductive process on the active layer. In an exemplary embodiment, conducting a conductive process on the active layer includes:

[0086] Using an ion implantation method, with the gate electrode 22 as a shield, the active layer 21 is ion implanted to form an active layer pattern including the source-drain connection region and the channel region. Figure 11 In one exemplary embodiment, the active layer is made conductive. Figure 2 A sectional view along direction AA.

[0087] In an exemplary implementation, such as Figure 11 As shown, the area of ​​the active layer 21 that is shielded by the gate electrode 22 forms a channel region G, and the area of ​​the active layer 21 that is not shielded by the gate electrode 22 forms a source-drain connection region. The source-drain connection region is located on both sides of the channel region G and includes a first connection region S1 and a second connection region S2. One of the first auxiliary conductive part 33 and the second auxiliary conductive part 34 is connected to the first connection region S1, and the other is connected to the second connection region S2.

[0088] In an exemplary implementation, such as Figure 11 As shown, the ion implantation method can be to treat the active layer 21 with plasma in a direction perpendicular to the substrate 10. The plasma can be helium (He) gas or a mixture of helium and argon (Ar) gas. The type and variety of ions implanted can be selected as needed, and this invention does not limit this. In other embodiments, other forms of ion implantation methods or other methods can be used to conduct the active layer 21, and this invention does not limit this.

[0089] (6) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include:

[0090] A third insulating film is deposited on the substrate 10 on which the aforementioned pattern is formed, and a third insulating layer 13 is formed on the substrate 10. The cross-sectional structure of the display substrate after the formation of the third insulating layer can be referenced. Figure 3 As shown.

[0091] In an exemplary implementation, such as Figure 3 As shown, the orthographic projection of the third insulating layer 13 on the substrate 10 can cover the orthographic projection of the transistor film layer on the substrate 10. For example, the orthographic projection of the third insulating layer 13 on the substrate 10 can cover the orthographic projection of the other film layers formed on the substrate 10.

[0092] In an exemplary embodiment, the material of the third insulating film can be referred to the foregoing description of the material of the first insulating film, and will not be repeated here.

[0093] Thus, as Figure 3 The display substrate shown has been fabricated.

[0094] In an exemplary implementation, subsequent steps can be taken... Figure 3 The display substrate shown has a via exposed to the first connection area S1, and a top electrode is formed thereafter. The top electrode can be connected to the first connection area S1 through the via. The top electrode may include another of the first electrode 24 and the second electrode 25.

[0095] This utility model embodiment also provides a display device, including the display substrate described in any of the above embodiments. The display device can be any product or component with display function, such as an OLED display, QLED display, LED display, LCD display, projector, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc., and this utility model embodiment is not limited thereto. When the display device is an LCD display, the display substrate described in any of the above embodiments can be an array substrate of the LCD display.

[0096] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A display substrate, characterized in that, Includes at least one transistor disposed on a substrate, the transistor comprising: A bottom electrode, disposed on the substrate, includes at least one of a first electrode and a second electrode; An auxiliary conductive part is disposed on the side of the bottom electrode away from the substrate; An active layer is disposed on the side of the auxiliary conductive portion away from the substrate and in contact with the auxiliary conductive portion, including a channel region and source-drain connection regions located on both sides of the channel region, wherein the first electrode and the second electrode are respectively connected to the source-drain connection regions; A second insulating layer is disposed on the side of the active layer away from the substrate; the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the channel region on the substrate. A gate electrode is disposed on the side of the second insulating layer away from the substrate; the channel region is the area where the gate electrode and the active layer overlap in a direction perpendicular to the substrate; Wherein, the orthographic projection of the auxiliary conductive part on the substrate is within the range of the orthographic projection of the source-drain connection region on the substrate.

2. The display substrate according to claim 1, characterized in that, It also includes a light-shielding part, which is disposed in the same layer as the bottom electrode, and the orthogonal projection of the light-shielding part on the substrate covers the orthogonal projection of the channel region on the substrate.

3. The display substrate according to claim 2, characterized in that, It also includes a first insulating layer, which is located on the side of the light-shielding portion and the bottom electrode away from the substrate, and on the side of the auxiliary conductive portion close to the substrate.

4. The display substrate according to claim 3, characterized in that, The source-drain connection region includes a first connection region and a second connection region located on both sides of the channel region; the first electrode and the second electrode are respectively connected to the source-drain connection region, including: One of the first pole and the second pole is connected to the first connection region, and the other is connected to the second connection region.

5. The display substrate according to claim 4, characterized in that, The first insulating layer includes a plurality of vias, and the bottom electrode is connected to the corresponding source-drain connection region through the vias.

6. The display substrate according to claim 5, characterized in that, Within the plane of the substrate, the minimum size of the via is greater than or equal to 3.6 micrometers.

7. The display substrate according to claim 4, characterized in that, The auxiliary conductive part includes at least one of a first auxiliary conductive part and a second auxiliary conductive part; One of the first auxiliary conductive part and the second auxiliary conductive part is connected to the first connection region, and the other is connected to the second connection region.

8. The display substrate according to claim 3, characterized in that, It also includes a third insulating layer disposed on the side of the gate electrode away from the substrate; the orthogonal projection of the third insulating layer on the substrate covers the orthogonal projection of the at least one transistor on the substrate.

9. The display substrate according to claim 8, characterized in that, The bottom electrode includes one of the first electrode and the second electrode, and the other of the first electrode and the second electrode is located on the side of the third insulating layer away from the substrate.

10. The display substrate according to claim 3, characterized in that, It also includes a first signal line; the first signal line is connected to the first or second terminal of at least one of the transistors.

11. The display substrate according to claim 10, characterized in that, The first signal line is integrally structured with the first or second electrode of at least one of the transistors.

12. The display substrate according to claim 3, characterized in that, It also includes a second signal line; the second signal line is connected to the gate electrode of at least one of the transistors.

13. The display substrate according to claim 12, characterized in that, The second signal line is integral with the gate electrode of at least one of the transistors.

14. The display substrate according to claim 1, characterized in that, The active layer is made of an oxide semiconductor.

15. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 14.

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