Duty cycle taking large output control circuit and device based on pure hardware circuit structure

Abstract

The utility model discloses a kind of duty cycle takes big output control circuit and equipment based on pure hardware circuit structure, the circuit includes: single-pole double-throw analog switch U1, operational amplifier comparator U2 and RC filter subcircuit;Signal PWM1 and signal PWM2 are connected after RC filter subcircuit to operational amplifier comparator U2, the output end of operational amplifier comparator U2 is connected to the 6-pin input end of single-pole double-throw analog switch U1, and the output of the 4-pin output end of single-pole double-throw analog switch U1 is determined by the 6-pin input of single-pole double-throw analog switch U1;The circuit uses pure hardware circuit structure to screen PWM signal duty cycle, and circuit structure is simple and easy to realize, easy to operate, avoids using complex software program.

Description

Technical Field

[0001] This utility model relates to the field of PWM output control technology, and in particular to a duty cycle-based output control circuit with a pure hardware circuit structure. Background Technology

[0002] Current technology often involves one or more fans sharing a power supply, with each power supply outputting a PWM signal to regulate the fan speed. The goal is to use the PWM signal with the higher duty cycle to control the fan speed. However, current technologies require complex software control to determine the relationship between the two power supplies. There is no purely hardware-based control circuit that prioritizes the higher duty cycle output. Software control is complex, difficult to develop, and impractical for application. Therefore, there is an urgent need for a purely hardware-based control circuit that prioritizes the higher duty cycle output. Utility Model Content

[0003] The technical problem to be solved by this utility model is to propose a duty cycle large output control circuit based on a pure hardware circuit structure. This circuit uses a pure hardware circuit structure to filter the duty cycle of the PWM signal. The circuit structure is simple to implement and easy to operate, avoiding the use of complex software programs.

[0004] To solve the above-mentioned technical problems, this utility model provides a duty cycle large output control circuit based on a pure hardware circuit structure, including: a single-pole double-throw analog switch U1, an operational amplifier comparator U2, and an RC filter sub-circuit; signals PWM1 and PWM2 are connected to the operational amplifier comparator U2 after passing through the RC filter sub-circuit, the output terminal of the operational amplifier comparator U2 is connected to the 6th pin input terminal of the single-pole double-throw analog switch U1, and the output of the 4th pin output terminal of the single-pole double-throw analog switch U1 is determined by the 6th pin input of the single-pole double-throw analog switch U1.

[0005] Preferably, signals PWM1 and PWM2 are connected to pins 1 and 3 of the single-pole double-throw analog switch U1, respectively.

[0006] Preferably, the RC filter sub-circuit includes a first resistor R1 and a first capacitor C1. The first resistor R1 is connected to the non-inverting input terminal of the signal PWM1 and the operational amplifier comparator U2, and the first capacitor C1 is connected to ground at the non-inverting input terminal.

[0007] Preferably, the RC filter sub-circuit further includes a second resistor R2 and a first capacitor C2. The second resistor R2 is connected to the inverting input terminal of the signal PWM2 and the operational amplifier comparator U2, and the second capacitor C2 is connected to ground at the inverting input terminal.

[0008] Preferably, a third resistor R3 is connected between the output terminal of the operational amplifier comparator U2 and pin 6 of the single-pole double-throw analog switch U1, a fifth resistor R5 is connected between the output terminal of the operational amplifier comparator U2 and the power supply, and a third capacitor C3 is connected between pin 6 of the single-pole double-throw analog switch U1 and ground.

[0009] Preferably, the non-inverting input and output terminals of the operational amplifier comparator U2 are connected to a hysteresis circuit, which includes a fourth resistor R4 and a diode group.

[0010] To solve the above-mentioned technical problems, this utility model also provides a power electronic device, including the duty cycle large output control circuit based on the pure hardware circuit structure described above.

[0011] After adopting the above circuit, the duty cycle large output control circuit based on the pure hardware circuit structure includes a single-pole double-throw analog switch U1, an operational amplifier comparator U2, and an RC filter sub-circuit. Signals PWM1 and PWM2 are connected to the operational amplifier comparator U2 after passing through the RC filter sub-circuit. The output terminal of the operational amplifier comparator U2 is connected to the 6th pin input terminal of the single-pole double-throw analog switch U1. The output terminal of the single-pole double-throw analog switch U1 is determined by the 6th pin input terminal of the single-pole double-throw analog switch U1. This circuit uses a pure hardware circuit structure to filter the duty cycle of the PWM signal. The circuit structure is simple to implement and easy to operate, avoiding the use of complex software programs. Attached Figure Description

[0012] Figure 1 This is the overall circuit diagram of a duty cycle-based output control circuit with a high output efficiency, which is based on a pure hardware circuit structure according to this utility model. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for explaining the present utility model and are not intended to limit the present utility model.

[0014] Example 1

[0015] Please see Figure 1 , Figure 1 This is the overall circuit diagram of a duty cycle-maximizing output control circuit based on a pure hardware circuit structure according to this utility model.

[0016] This embodiment discloses a duty cycle large output control circuit based on a pure hardware circuit structure, including: a single-pole double-throw analog switch U1, an operational amplifier comparator U2, and an RC filter sub-circuit 10; signals PWM1 and PWM2 are connected to the operational amplifier comparator U2 after passing through the RC filter sub-circuit, and the output terminal of the operational amplifier comparator U2 is connected to the 6th pin input terminal of the single-pole double-throw analog switch U1. The output of the 4th pin output terminal of the single-pole double-throw analog switch U1 is determined by the 6th pin input of the single-pole double-throw analog switch U1.

[0017] The op-amp comparator U2 outputs a high or low level, which determines the output of the single-pole double-throw switch U1, selecting the desired signal.

[0018] Example 2

[0019] This embodiment is based on Embodiment 1. In this embodiment, signal PWM1 and signal PWM2 are connected to pin 1 and pin 3 of the single-pole double-throw analog switch U1, respectively.

[0020] Example 3

[0021] This embodiment is based on embodiment one. In this embodiment, the RC filter sub-circuit 10 includes a first resistor R1 and a first capacitor C1. The non-inverting input terminal of the signal PWM1 and the operational amplifier comparator U2 is connected to the first resistor R1, and the non-inverting input terminal is connected to the first capacitor C1 to ground.

[0022] The RC filter sub-circuit 10 also includes a second resistor R2 and a first capacitor C2. The second resistor R2 is connected to the inverting input terminal of the signal PWM2 and the operational amplifier comparator U2, and the second capacitor C2 is connected to ground at the inverting input terminal.

[0023] Example 4

[0024] This embodiment is based on embodiment one. In this embodiment, a third resistor R3 is connected between the output terminal of the operational amplifier comparator U2 and pin 6 of the single-pole double-throw analog switch U1, a fifth resistor R5 is connected between the output terminal of the operational amplifier comparator U2 and the power supply, and a third capacitor C3 is connected between pin 6 of the single-pole double-throw analog switch U1 and ground.

[0025] Example 5

[0026] This embodiment is based on Embodiment 1. In this embodiment, the non-inverting input and output terminals of the operational amplifier comparator U2 are connected to a hysteresis circuit, which includes a fourth resistor R4 and a diode group.

[0027] Example 6

[0028] This embodiment is based on Embodiment 1. In this embodiment, a power electronic device is disclosed, including the duty cycle large output control circuit based on a pure hardware circuit structure as described in any one of Embodiments 1 to 4.

[0029] This duty cycle-based output control circuit, which uses a pure hardware circuit structure to select the duty cycle of the PWM signal, is simple to implement and easy to operate, avoiding the need for complex software programs.

[0030] It should be understood that the above are merely preferred embodiments of the present utility model and should not be construed as limiting the patent scope of the present utility model. Any equivalent structural or procedural transformations made based on the contents of the present utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present utility model.

Claims

1. A duty cycle-maximizing output control circuit based on a purely hardware circuit structure, characterized in that: include: Single-pole double-throw analog switch U1, operational amplifier comparator U2, and RC filter sub-circuit; Signals PWM1 and PWM2 are connected to operational amplifier comparator U2 after passing through the RC filter sub-circuit. The output of operational amplifier comparator U2 is connected to the input of pin 6 of single-pole double-throw analog switch U1. The output of pin 4 of single-pole double-throw analog switch U1 is determined by the input of pin 6 of single-pole double-throw analog switch U1.

2. The duty cycle-maximizing output control circuit based on a pure hardware circuit structure according to claim 1, characterized in that: Signals PWM1 and PWM2 are connected to pins 1 and 3 of the single-pole double-throw analog switch U1, respectively.

3. The duty cycle-maximizing output control circuit based on a pure hardware circuit structure according to claim 1, characterized in that: The RC filter sub-circuit includes a first resistor R1 and a first capacitor C1. The non-inverting input terminal of the signal PWM1 and the operational amplifier comparator U2 is connected to the first resistor R1, and the non-inverting input terminal is connected to ground by the first capacitor C1.

4. The duty cycle-maximizing output control circuit based on a pure hardware circuit structure according to claim 3, characterized in that: The RC filter sub-circuit also includes a second resistor R2 and a first capacitor C2. The second resistor R2 is connected to the inverting input terminal of the signal PWM2 and the operational amplifier comparator U2, and the second capacitor C2 is connected to ground at the inverting input terminal.

5. The duty cycle-maximizing output control circuit based on a pure hardware circuit structure according to claim 1, characterized in that: A third resistor R3 is connected between the output terminal of the operational amplifier comparator U2 and pin 6 of the single-pole double-throw analog switch U1. A fifth resistor R5 is connected between the output terminal of the operational amplifier comparator U2 and the power supply. A third capacitor C3 is connected between pin 6 of the single-pole double-throw analog switch U1 and ground.

6. The duty cycle-maximizing output control circuit based on a pure hardware circuit structure according to claim 1, characterized in that: The non-inverting input and output of the operational amplifier comparator U2 are connected to a hysteresis circuit, which includes a fourth resistor R4 and a diode group.

7. A device, characterized in that: Includes the duty cycle large output control circuit based on a pure hardware circuit structure as described in any one of claims 1 to 6.

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