Highly reliable planar gate silicon carbide vdmos
By designing a highly reliable planar gate silicon carbide VDMOS structure, the problems of reduced insulating dielectric quality and decreased gate control capability in silicon carbide VDMOS devices were solved, thereby improving the reliability and gate control capability of the device under high voltage and reducing conduction losses.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GLOBAL POWER TECH CO LTD
- Filing Date
- 2025-05-28
- Publication Date
- 2026-06-05
AI Technical Summary
The gate reliability of silicon carbide VDMOS devices is affected when the quality of the insulating dielectric silicon dioxide decreases, and the gate control capability decreases under thick insulating dielectric.
A highly reliable planar gate silicon carbide VDMOS structure was designed, including a structure in which a second P-type source region wraps a P-type well region and a P-type well region wraps an N-type source region. The design combines the first and second protrusions with the same width as the P-type well region. There is a thick insulating dielectric under the gate metal layer to construct an alternating structure of Schottky diode and parasitic pn junction diode, which enhances the reliability and gate control capability of the device.
It improves the reliability of the device under high voltage, reduces the electric field strength near the gate and source, enhances the gate reliability and resistance to external shocks, and reduces conduction losses.
Smart Images
Figure CN224329835U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a high-reliability planar gate silicon carbide VDMOS. Background Technology
[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally possess the advantages of low gate charge and high switching speed compared to silicon VDMOS devices. However, due to the characteristics of silicon carbide materials, there are two problems: first, the quality of its insulating dielectric silicon dioxide is relatively reduced, which will affect the gate reliability of the device; second, it can only guarantee gate reliability when the insulating dielectric is thicker, but the gate control capability will decrease. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a highly reliable planar gate silicon carbide VDMOS, which improves the reliability of the device when the drain withstands voltage.
[0004] This invention provides a high-reliability planar gate silicon carbide VDMOS, comprising:
[0005] silicon carbide substrate;
[0006] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer has protrusions and grooves; the protrusions have gate protection zones;
[0007] A first P-type source region, the lower side of which is connected to the upper side of the drift layer;
[0008] A Schottky metal layer, the lower part of which is disposed in the groove, and the inner side of the first P-type source region is connected to the outer side of the Schottky metal layer;
[0009] The second P-type source region has its lower side connected to the upper side of the drift layer, its outer side connected to the inner side of the Schottky metal layer, a P-type well region on the second P-type source region, an N-type source region on the P-type well region, and both the inner side of the second P-type source region and the inner side of the P-type well region connected to the outer side of the protrusion.
[0010] An insulating dielectric layer is provided, the lower side of which is connected to the upper side of the N-type source region, the upper side of the P-type well region, the upper side of the protrusion, and the upper side of the gate protection region, respectively; the insulating dielectric layer is provided with a hollow groove.
[0011] A gate metal layer, wherein the gate metal layer is disposed within the hollow groove;
[0012] A source metal layer, wherein the source metal layer is respectively connected to the first P-type source region, the Schottky metal layer, the second P-type source region, the P-type well region and the N-type source region;
[0013] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0014] The advantages of this utility model are:
[0015] I. This utility model constructs a structure in which a second P-type source region surrounds a P-type well region, and the P-type well region surrounds an N-type source region. Under the condition that the drain is subjected to a large voltage, the electric field strength near the gate and source of the device can be gradually reduced, thereby improving the reliability of the device.
[0016] II. This utility model constructs a first protrusion and a second protrusion, which are equal in width to the P-type well region between the lower N-type source region and the protrusion, thus achieving good gate control capability. There is a thick insulating medium below the gate metal layer, which can improve the gate reliability of the device. Correspondingly below it is a P-type gate protection zone with the same doping concentration and thickness as the P-type well region, which can improve the gate reliability of the device when the drain of the device is subjected to a large voltage.
[0017] Third, an insulating dielectric is covered on top of the gate metal layer of the device, and a source metal layer is covered on top of the insulating dielectric, which can improve the device's ability to withstand external impacts.
[0018] Fourth, an alternating structure of a first P-type source region, a Schottky metal layer, and a second P-type source region is constructed in the body diode region of the device. The Schottky diode and the parasitic pn junction diode share the current flow, which reduces the current flow capability and conduction loss of the body diode. The depth of the Schottky diode in the device is greater than the thickness of the first P-type source region. This is to increase the contact surface of the Schottky diode, improve the current flow capability of the Schottky diode, and improve the low conduction loss of the body diode while ensuring the voltage withstand capability of the device. Attached Figure Description
[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0020] Figure 1 This is a schematic diagram of a high-reliability planar gate silicon carbide VDMOS according to the present invention.
[0021] Figure 2 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 1 .
[0022] Figure 3 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 2 .
[0023] Figure 4 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 3 .
[0024] Figure 5 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 4 .
[0025] Figure 6 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 5 .
[0026] Figure 7 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 6 .
[0027] Figure 8 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 7 .
[0028] Figure 9 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 8 .
[0029] Figure 10 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 9 .
[0030] Figure 11 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 10 .
[0031] Figure 12 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 10 one.
[0032] Figure 13 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 10 two.
[0033] Figure 14 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS according to the present invention. Figure 10 three. Detailed Implementation
[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0038] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0039] like Figure 1 As shown, this application embodiment provides a high-reliability planar gate silicon carbide VDMOS, comprising:
[0040] Silicon carbide substrate 1;
[0041] A drift layer 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1; the drift layer 2 is provided with a protrusion 21 and a groove 22; a gate protection zone 211 is provided on the protrusion 21;
[0042] The first P-type source region 3, the lower side of the first P-type source region 3 is connected to the upper side of the drift layer 2;
[0043] Schottky metal layer 4, the lower part of which is disposed in the groove 22, and the inner side of the first P-type source region 3 is connected to the outer side of the Schottky metal layer 4;
[0044] The second P-type source region 5 has its lower side connected to the upper side of the drift layer 2, its outer side connected to the inner side of the Schottky metal layer 4, a P-type well region 51 on the second P-type source region 5, an N-type source region 511 on the P-type well region 51, and its inner side and the inner side of the second P-type source region 5 are both connected to the outer side of the protrusion 21.
[0045] An insulating dielectric layer 6 is provided, the lower side of which is connected to the upper side of the N-type source region 511, the upper side of the P-type well region 51, the upper side of the protrusion 21, and the upper side of the gate protection region 211; a hollow groove 61 is provided in the insulating dielectric layer 6.
[0046] Gate metal layer 7, the gate metal layer 7 being disposed within the hollow groove 61;
[0047] Source metal layer 8, which is connected to the first P-type source region 3, the Schottky metal layer 4, the second P-type source region 5, the P-type well region 51 and the N-type source region 511 respectively;
[0048] And a drain metal layer 9, which is connected to the lower side of the silicon carbide substrate 1.
[0049] In this embodiment, preferably, the lower part of the gate metal layer 7 is provided with a first protrusion 71 and a second protrusion 72; the first protrusion 71 and the second protrusion 72 are located directly above the P-type well region 51 between the protrusion 21 and the N-type source region 511, the width of the first protrusion 71 is equal to the width of the second protrusion 72, and the width of the first protrusion 71 is equal to the distance between the protrusion 21 and the N-type source region 511.
[0050] In this embodiment, preferably, the doping concentration of the first P-type source region 3 is greater than the doping concentration of the drift layer 2; the doping concentration of the second P-type source region 5 is greater than the doping concentration of the P-type well region 51; and the doping concentration of the first P-type source region 3 is equal to the doping concentration of the second P-type source region 5.
[0051] In this embodiment, preferably, the doping concentration of the P-type well region 51 is less than the doping concentration of the N-type source region 511.
[0052] In this embodiment, preferably, the thickness of the gate protection zone 211 is equal to the thickness of the P-type well zone 51.
[0053] like Figures 1 to 14 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:
[0054] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 9; grow epitaxially on the upper side of silicon carbide substrate 1 to form drift layer 2;
[0055] Step 2: Form a barrier layer 100 above the drift layer 2, etch the barrier layer 100 to form a via, and implant ions to form a P-type region 200.
[0056] Step 3: Remove the barrier layer 100 from Step 2, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form a P-type region 300.
[0057] Step 4: Remove the barrier layer 100 from step 3, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form a P-type well region 51, a gate protection zone 211, and a protrusion 21, respectively.
[0058] Step 5: Remove the barrier layer 100 from step 4, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form an N-type source region 511.
[0059] Step 6: Remove the barrier layer 100 from step 5, reform the barrier layer 100, etch the barrier layer 100 to form a via, and etch the P-type region 200 and the drift layer 2 to obtain the first P-type source region 3, the second P-type source region 5 and the groove 22, and deposit the Schottky metal layer 4.
[0060] Step 7: Remove the barrier layer 100 from step 6, reform the barrier layer 100, etch the barrier layer 100 to form a via, and deposit the first insulating layer 62.
[0061] Step 8: Remove the barrier layer 100 from step 7, reform the barrier layer 100, etch the barrier layer 100 to form a through hole, deposit metal, and form the first protrusion 71 and the second protrusion 72.
[0062] Step 9: Remove the barrier layer 100 from step 8, reform the barrier layer 100, etch the barrier layer 100 to form a via, and deposit the second insulating layer 63.
[0063] Step 10: Remove the barrier layer 100 from step 9, reform the barrier layer 100, etch the barrier layer 100 to form a via, deposit metal, and form the gate metal layer 7.
[0064] Step 11: Remove the barrier layer 100 from step 10, reform the barrier layer 100, etch the barrier layer 100 to form a via, and deposit the third insulating layer 64. The insulating dielectric layer 6 includes the first insulating layer 62, the second insulating layer 63, and the third insulating layer 64.
[0065] Step 12: Remove the barrier layer 100 from step 11, deposit metal, and form the source metal layer 8.
[0066] In another embodiment of this invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 2 is 6-10e16cm. -3 The doping concentration of the P-type well region 51 is 1-5e15cm. -3 The doping concentration of the first P-type source region 3 and the second P-type source region 5 is 1-5e19cm. -3 The insulating dielectric layer 6 can be made of silicon dioxide, and the doping concentration of the N-type source region 511 is 2-8e18cm. -3 The doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 9, thereby reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 2 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. The doping concentration of the first P-type source region 3 is to reduce the contact resistance between the first P-type source region 3 and the source metal layer 8, thereby reducing the conduction loss of the parasitic pn junction diode of the device. The doping concentration of the second P-type source region 5 is to reduce the diffusion rate of the space charge region when it diffuses to the device gate and source when the drain voltage is high. The doping concentration of the P-type well region 51 is to reduce the gate control charge of the device gate, improve the switching speed of the device, and form a buffer zone between the second P-type source region 5 and the N-type source region 511, thereby reducing the electric field strength near the N-type source region 511 and improving the reliability of the device near the N-type source region 511.
[0067] The thickness of the N-type silicon carbide substrate 1 is 1 μm, and the thickness of the N-type drift layer 2 is 50-100 μm, adjusted within this range according to different requirements for the device's withstand voltage characteristics. The thickness of the insulating medium below the first protrusion 71 and the second protrusion 72 is 50 nm to ensure the device's gate control capability. The thickness of the insulating medium below the gate metal layer 7 is 200 nm to ensure the reliability of the middle region of the gate, while reducing the gate-drain capacitance and improving the device's switching speed. The width of the insulating medium on the left and right sides of the gate metal layer 7 is 500 nm to achieve isolation from the source metal layer 8; its width does not affect the device characteristics. The maximum thickness of the first P-type source region 3 and the second P-type source region 5 is 600 nm, the thickness of the N-type source region 511 is 150 nm, and the thickness of the P-type well region 5... The maximum thickness of the Schottky metal layer 4 is 300 nm, and the thickness of the Schottky metal layer 4 is 800 nm. This is to improve the Schottky metal contact surface, improve the freewheeling capability of the Schottky diode, and reduce the freewheeling loss of the body diode. The width of the first protrusion 71 and the second protrusion 72 are both 500 nm, and the thickness is both 250 nm. The width of the gate metal layer 7 is 3 μm, and the thickness in the middle of the gate metal layer 7 is 100 nm. The maximum thickness of the source metal layer 8 is 600 nm. The width of the Schottky metal layer 4 and the first P-type source region 3 are both 500 nm. The width of the N-type source region 511 is 500 nm. The width of the P-type well region inside the N-type source region 511 is 500 nm. The width of the P-type gate protection region 211 is 1 μm. This is to ensure the conductive channel of the device while protecting the gate metal layer 7 of the device.
[0068] This invention constructs a structure in which a second P-type source region 5 encloses a P-type well region 51, and the P-type well region 51 encloses an N-type source region 511. Under the condition that the drain is subjected to a large voltage, the electric field strength near the gate and source of the device can be gradually reduced, thereby improving the reliability of the device.
[0069] This invention constructs a first protrusion 71 and a second protrusion 72, which are equal in width to the P-type well region 51 between the lower N-type source region 511 and the protrusion 21, thus achieving good gate control capability. There is a thick insulating medium below the gate metal layer 7, which can improve the gate reliability of the device. Correspondingly below it is a P-type gate protection zone 211 with the same doping concentration and thickness as the P-type well region 51, which can improve the gate reliability of the device when the drain of the device is subjected to a large voltage.
[0070] An insulating dielectric is covered on top of the gate metal layer 7 of the device, and a source metal layer 8 is covered on top of the insulating dielectric, which can improve the device's ability to withstand external impacts.
[0071] An alternating structure of first P-type source region 3, Schottky metal layer 4, and second P-type source region 5 is constructed in the body diode region of the device. The Schottky diode and the parasitic pn junction diode share the current flow, which reduces the current flow capability and conduction loss of the body diode. The depth of the Schottky diode in the device is greater than the thickness of the first P-type source region 3. This is to increase the contact surface of the Schottky diode and improve its current flow capability, thereby improving the low conduction loss of the body diode while ensuring the device's withstand voltage.
[0072] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A high-reliability planar gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate; A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer has protrusions and grooves; the protrusions have gate protection zones; A first P-type source region, the lower side of which is connected to the upper side of the drift layer; A Schottky metal layer, the lower part of which is disposed in the groove, and the inner side of the first P-type source region is connected to the outer side of the Schottky metal layer; The second P-type source region has its lower side connected to the upper side of the drift layer, its outer side connected to the inner side of the Schottky metal layer, a P-type well region on the second P-type source region, an N-type source region on the P-type well region, and both the inner side of the second P-type source region and the inner side of the P-type well region connected to the outer side of the protrusion. An insulating dielectric layer is provided, the lower side of which is connected to the upper side of the N-type source region, the upper side of the P-type well region, the upper side of the protrusion, and the upper side of the gate protection region, respectively; the insulating dielectric layer is provided with a hollow groove. A gate metal layer, wherein the gate metal layer is disposed within the hollow groove; A source metal layer, wherein the source metal layer is respectively connected to the first P-type source region, the Schottky metal layer, the second P-type source region, the P-type well region and the N-type source region; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The high-reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The lower part of the gate metal layer is provided with a first protrusion and a second protrusion; the first protrusion and the second protrusion are located directly above the P-type well region between the protrusion and the N-type source region, the width of the first protrusion is equal to the width of the second protrusion, and the width of the first protrusion is equal to the distance between the protrusion and the N-type source region.
3. The high-reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the first P-type source region is greater than the doping concentration of the drift layer; the doping concentration of the second P-type source region is greater than the doping concentration of the P-type well region; the doping concentration of the first P-type source region is equal to the doping concentration of the second P-type source region.
4. A high-reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type well region is less than the doping concentration of the N-type source region.
5. A high-reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the gate protection zone is equal to the thickness of the P-type well zone.