Intelligent power module

Abstract

The utility model provides a kind of intelligent power module.The intelligent power module, multiple power chips and multiple gate drive chips are attached on lead frame and are arranged into two rows along the first direction, multiple power chips include multiple groups of power chips sequentially arranged along the first direction, a group of power chips includes one high-side power chip and one low-side power chip, the order of high-side power chip and low-side power chip in the first direction in each group of power chips is same and is connected with one gate drive chip by bonding wire, and multiple gate drive chips are same chip with same pin layout.Because the order of high-side power chip and low-side power chip in the first direction in each group of power chips is same, multiple gate drive chips can use same chip, which helps to reduce the design and development cycle of intelligent power module.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to an intelligent power module. Background Technology

[0002] Intelligent power modules (IPMs) mainly consist of two parts: a power circuit and a drive protection circuit. They integrate logic, control, detection, and protection circuits, significantly reducing size and improving power cycle life compared to traditional power modules. They also offer advantages such as high reliability, high integration, and ease of use, playing an indispensable role in various fields including industrial automation, home appliances, new energy vehicles, renewable energy, energy storage systems, and automotive electronics.

[0003] Figure 1 This is a schematic diagram of the internal structure of an intelligent power module. Figure 2 This is a circuit topology diagram of an intelligent power module. Utility model patent CN219893187U discloses an intelligent power module, see reference... Figure 1 and Figure 2 As shown, in this intelligent power module, the third low-side power chip Q32 and the second low-side power chip Q22 are arranged adjacent to each other, and the second high-side power chip Q21 and the first high-side power chip Q11 are spaced apart between the non-adjacent second low-side power chip Q22 and the first low-side power chip Q12; the third high-side power chip Q31 and the third low-side power chip Q32 are connected to the first gate driver chip A1, the second high-side power chip Q21 and the second low-side power chip Q22 are connected to the second gate driver chip A2, and the first high-side power chip Q11 and the first low-side power chip Q12 are connected to the third gate driver chip A3, wherein the first gate driver chip A1 and the third gate driver chip A3 are the same chip, and the second gate driver chip A2 is a different chip from the first gate driver chip A1 and the third gate driver chip A3. Utility Model Content

[0004] This invention provides an intelligent power module in which multiple gate driver chips can be compatible as a single chip, which helps to reduce the design and development cycle of intelligent power modules.

[0005] To achieve the above objectives, the intelligent power module provided by this utility model includes a lead frame, multiple power chips, and multiple gate driver chips; the multiple power chips are mounted on the lead frame and arranged sequentially along a first direction; the multiple gate driver chips are mounted on the lead frame and arranged sequentially along the first direction; wherein, the multiple power chips and the multiple gate driver chips are arranged in two rows; the multiple power chips include multiple groups of power chips arranged sequentially along the first direction, each group of power chips includes a high-side power chip and a low-side power chip, the high-side power chip and the low-side power chip in each group of power chips are arranged in the same order in the first direction and are all connected to a gate driver chip through bonding wires, and the multiple gate driver chips are the same type of chip with the same pin layout.

[0006] Optionally, the plurality of power chips include a third high-side power chip, a third low-side power chip, a second high-side power chip, a second low-side power chip, a first high-side power chip, and a first low-side power chip arranged sequentially along the first direction.

[0007] Optionally, the pins of the gate driver chip include a high-side drive signal output terminal, a high-side drive floating power supply ground terminal, a low-side drive reference ground terminal, and a low-side drive signal output terminal arranged sequentially along the first direction; the control terminal of the high-side power chip is connected to the high-side drive signal output terminal of the corresponding gate driver chip, the second terminal of the high-side power chip is connected to the high-side drive floating power supply ground terminal of the corresponding gate driver chip, the second terminal of the low-side power chip is connected to the low-side drive reference ground terminal of the corresponding gate driver chip, and the control terminal of the low-side power chip is connected to the low-side drive signal output terminal of the corresponding gate driver chip.

[0008] Optionally, the pins of the gate driver chip further include a high-side drive floating power supply terminal located between the high-side drive floating power supply ground terminal and the low-side drive reference ground terminal. The high-side drive signal output terminal, the high-side drive floating power supply ground terminal, the high-side drive floating power supply terminal, the low-side drive reference ground terminal, and the low-side drive signal output terminal are all disposed on the side of the gate driver chip close to the power chip.

[0009] Optionally, the lead frame includes multiple base islands spaced apart from each other, and multiple power chips and multiple gate driver chips are mounted on corresponding base islands; the first ends of the high-side power chip and the low-side power chip are both connected to the corresponding base islands.

[0010] Optionally, the lead frame includes a first base island, a second base island, a third base island, a fourth base island, and a fifth base island separated from each other; the second base island, the third base island, the fourth base island, and the fifth base island are located on the same side of the first base island; the second base island has a first protrusion, a second protrusion, a third protrusion protruding in a direction away from the first base island, and a connecting portion connecting two adjacent protrusions, the third base island portion is located between the first protrusion and the second protrusion, and the fourth base island portion is located between the second protrusion and the third protrusion.

[0011] Optionally, a plurality of the gate driving chips are mounted on the first base island; a first high-side power chip is mounted on the third protrusion, a second high-side power chip is mounted on the second protrusion, and a third high-side power chip is mounted on the first protrusion; a third low-side power chip, a second low-side power chip, and a first low-side power chip are respectively mounted on the third base island, the fourth base island, and the fifth base island.

[0012] Optionally, the lead frame further includes a first conductive strip located between the first base island and the second base island and extending in the first direction, with at least one end of the first conductive strip extending a pin outside the plastic package of the smart power module; the second end of the first low-side power chip is connected to the first conductive strip via a bonding wire, and the first conductive strip is connected to the low-side drive reference ground of the gate drive chip corresponding to the first low-side power chip via a bonding wire.

[0013] Optionally, the power chip is an RC-IGBT, the gate of the RC-IGBT serves as the control terminal of the power chip, the collector of the RC-IGBT serves as the first terminal of the power chip and is located on the base island corresponding to each power chip, and the emitter of the RC-IGBT serves as the second terminal of the power chip.

[0014] Optionally, the power chip is a MOS transistor, with the gate of the MOS transistor serving as the control terminal of the power chip, the drain of the MOS transistor serving as the first terminal of the power chip, and the source of the MOS transistor serving as the second terminal of the power chip.

[0015] Optionally, the power chip includes an IGBT and a fast recovery diode. The gate of the IGBT serves as the control terminal of the power chip. The emitter of the IGBT is electrically connected to the anode of the fast recovery diode and serves as the second terminal of the power chip. The collector of the IGBT is electrically connected to the cathode of the fast recovery diode and serves as the first terminal of the power chip. The collector of the IGBT and the cathode of the fast recovery diode are located on the base islands corresponding to each power chip.

[0016] Optionally, the smart power module further includes a molding compound that encapsulates a plurality of the power chips, a plurality of the gate driver chips, and a portion of the lead frame, the lead frame including a plurality of pins, portions of which are exposed from the molding compound.

[0017] The intelligent power module provided by this utility model includes a lead frame and multiple power chips and multiple gate driver chips mounted on the lead frame. The multiple power chips and multiple gate driver chips are arranged in two rows. The multiple power chips include multiple groups of power chips arranged sequentially along a first direction. Each group of power chips includes a high-side power chip and a low-side power chip. In each group of power chips, the high-side power chips and low-side power chips are arranged in the same order in the first direction and are all connected to a gate driver chip through bonding wires. The multiple gate driver chips are the same type of chip with the same pin layout. Because the multiple power chips in this application are arranged sequentially along the first direction and the high-side power chips and low-side power chips in each group of power chips are arranged in the same order in the first direction, the multiple gate driver chips can use the same chip, which helps to reduce the design and development cycle of the intelligent power module. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the internal structure of an intelligent power module.

[0019] Figure 2 This is a circuit topology diagram of an intelligent power module.

[0020] Figure 3 This is a schematic diagram of the internal structure of an intelligent power module provided in an embodiment of the present invention.

[0021] Figure 4 The circuit topology diagram of the intelligent power module provided in one embodiment of this utility model is shown.

[0022] Figure 5 This is a schematic diagram of the pin layout on the front side of a gate driver chip according to an embodiment of the present invention.

[0023] Figure 6 This is a top view schematic diagram of a power chip provided in an embodiment of the present invention.

[0024] Figure 7 This is a three-dimensional schematic diagram of an intelligent power module provided in an embodiment of the present invention.

[0025] Figure 8 A three-dimensional schematic diagram of an intelligent power module provided in another embodiment of this utility model.

[0026] Explanation of reference numerals in the attached drawings: 100-lead frame; 100a-first side; 100b-second side; 101-first base island; 102-second base island; 102a-first protrusion; 102b-second protrusion; 102c-third protrusion; 102d-connection portion; 103-third base island; 104-fourth base island; 105-fifth base island; 106-pin; 107-first conductive strip; 200-gate driver chip; 201-first gate driver chip; 202-second gate driver chip; 203-third gate driver chip; 301-gate of IGBT; 302-emitter of IGBT; 400-bonding wire; 500-molding package. Detailed Implementation

[0027] The intelligent power module proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.

[0028] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used in this invention, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used in this invention, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used in this invention, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0029] Figure 3 This is a schematic diagram of the internal structure of an intelligent power module provided in an embodiment of the present invention. Figure 4 This is a circuit topology diagram of an intelligent power module provided in one embodiment of the present invention. Figure 3 and Figure 4As shown, the intelligent power module provided in this application includes a lead frame 100, multiple power chips, and multiple gate driver chips 200. The multiple power chips are mounted on the lead frame 100 and arranged sequentially along the first direction X; the multiple gate driver chips 200 are mounted on the lead frame 100 and arranged sequentially along the first direction X; wherein, the multiple power chips and the multiple gate driver chips 200 are arranged in two rows in the Y direction; the multiple power chips include multiple groups of power chips arranged sequentially along the first direction X, each group of power chips includes a high-side power chip and a low-side power chip, the high-side power chip and the low-side power chip in each group of power chips are arranged in the same order in the first direction X and are all connected to a gate driver chip 200 through bonding wires, and the multiple gate driver chips 200 are the same type of chip with the same pin layout.

[0030] It should be noted that in the existing technology, reference Figure 1 As shown, the third high-side power chip Q31 and the third low-side power chip Q32 form the third group of power chips; the second high-side power chip Q21 and the second low-side power chip Q22 form the second group of power chips; and the first high-side power chip Q11 and the first low-side power chip Q12 form the first group of power chips. The high-side and low-side power chips within these three groups of power chips... Figure 1 The horizontal order from right to left is high-side power chip to low-side power chip, low-side power chip to high-side power chip, and high-side power chip to low-side power chip. The order of the high and low sides of the second group of power chips Q22 and Q21 is different from that of the first group of power chips Q11 and Q12 and the third group of power chips Q31 and Q32. If the gate driver chips in this smart power module are the same chip with the same pin layout, such as the first gate driver chip A1, then when connecting the second low-side power chip Q22 and the second high-side power chip Q21 to the gate driver chip via wire bonding, the bonding wires between the second low-side power chip Q22 and the gate driver chip will cross with the bonding wires between the second high-side power chip Q21 and the gate driver chip. This can easily lead to a short circuit between the bonding wires, causing the smart power module to fail. Therefore, the gate driver chips connected to the second low-side power chip Q22 and the second high-side power chip Q21 must be different from the other gate driver chips in this smart power module.

[0031] In the intelligent power module of this application, multiple power chips are arranged sequentially along the first direction X, and the high-side power chips and low-side power chips in each group of power chips are arranged in the same order in the first direction X. Therefore, when the gate driver chip and the power chip are connected by bonding wires, there will be no bonding wire crossing. Thus, the multiple gate driver chips 200 of the intelligent power module can be the same type of chip with the same pin layout, which can reduce the design and development cycle of the intelligent power module.

[0032] In this embodiment, reference Figure 3 As shown, the multiple power chips include a third high-side power chip Q31, a third low-side power chip Q32, a second high-side power chip Q21, a second low-side power chip Q22, a first high-side power chip Q11, and a first low-side power chip Q12 arranged sequentially along the first direction X. The third high-side power chip Q31 and the third low-side power chip Q32 form one group; the second high-side power chip Q21 and the second low-side power chip Q22 form another group; and the first high-side power chip Q11 and the first low-side power chip Q12 form yet another group. In the three groups of power chips, the high-side and low-side power chips are arranged in the same order along the first direction X, both being high-low. It should be noted that this embodiment uses three groups of power chips and three gate driver chips as an example for illustration. However, in other embodiments of this application, the number of power chip groups in the intelligent power module can also be two or more groups.

[0033] refer to Figure 3 As shown, the lead frame 100 includes multiple base islands separated from each other, and multiple power chips and multiple gate driver chips 200 are mounted on the corresponding base islands.

[0034] For example, the lead frame 100 may include a first base island 101, a second base island 102, a third base island 103, a fourth base island 104, and a fifth base island 105 separated from each other; wherein the second base island 102, the third base island 103, the fourth base island 104, and the fifth base island 105 are located on the same side of the first base island 101; the third base island 103, the fourth base island 104, and the fifth base island 105 are arranged sequentially in the first direction X.

[0035] More specifically, the lead frame 100 may include a first side 100a and a second side 100b extending along a first direction X and opposite to each other, wherein the first side 100a and the second side 100b may be the long side of the lead frame 100. The first base island 101 may be a long base island disposed near the first side 100a and extending along the first direction X. The second base island 102, the third base island 103, the fourth base island 104 and the fifth base island 105 may be disposed near the second side 100b, and the second base island 102 may have a first protrusion 102a, a second protrusion 102b, a third protrusion 102c protruding in a direction away from the first base island 101 and a connecting portion 102d connecting two adjacent protrusions. The third base island 103 is partially located between the first protrusion 102a and the second protrusion 102b, and the fourth base island 104 is partially located between the second protrusion 102b and the third protrusion 102c.

[0036] The lead frame also includes a first conductive strip 107, which is located between the first base island 101 and the second base island 102 and extends in a first direction X, with at least one end of the first conductive strip extending a pin to the outside of the plastic package of the smart power module.

[0037] Continue to refer to Figure 3 As shown, multiple gate driver chips 200 are mounted on the first base island 101; multiple high-side power chips are mounted on the second base island 102, with the first high-side power chip Q11 located on the third protrusion 102c of the second base island, the second high-side power chip Q21 located on the second protrusion 102b of the second base island, and the third high-side power chip Q31 located on the first protrusion 102a of the second base island; multiple low-side power chips are mounted on the third base island 103, the fourth base island 104, and the fifth base island 105, respectively, that is, the third low-side power chip Q32 is mounted on the third base island 103, the second low-side power chip Q22 is mounted on the fourth base island 104, and the first low-side power chip Q12 is mounted on the fifth base island 105.

[0038] refer to Figure 3 As shown in this embodiment, a group of power chips corresponds to one gate driver chip 200. For example, the first high-side power chip Q11 and the first low-side power chip Q12 correspond to the first gate driver chip 201 on the right, the second high-side power chip Q21 and the second low-side power chip Q22 correspond to the second gate driver chip 202 in the middle, and the third high-side power chip Q31 and the third low-side power chip Q32 correspond to the third gate driver chip 203 on the left. It should be noted that, for ease of describing the internal connection relationship of the intelligent power module, the three gate driver chips of the intelligent power module are named the first gate driver chip 201, the second gate driver chip 202, and the third gate driver chip 203, respectively. However, the first gate driver chip 201, the second gate driver chip 202, and the third gate driver chip 203 are the same type of chip.

[0039] The gate driver chip 200 can be positioned close to its corresponding high-side power chip and low-side power chip, which facilitates wire bonding between the gate driver chip 200 and the power chip and helps to shorten the bonding wire length.

[0040] Figure 5 This is a schematic diagram of the pin layout on the front side of a gate driver chip according to an embodiment of the present invention. (Reference) Figure 3 and Figure 5As shown, the back side of the gate driver chip 200 is mounted on the first base island 101, and the front side of the gate driver chip 200 has multiple pins. For example, the pins on the front side of the gate driver chip 200 may include a high-side drive signal output terminal HO, a high-side drive floating power supply ground terminal VS, a high-side drive floating power supply terminal VB, a low-side drive reference ground terminal VSS, a low-side drive signal output terminal LO, and a signal ground terminal COM arranged sequentially along the first direction X. The high-side drive signal output terminal HO, the high-side drive floating power supply ground terminal VS, the high-side drive floating power supply terminal VB, the low-side drive reference ground terminal VSS, the low-side drive signal output terminal LO, and the signal ground terminal COM are all located on the side of the gate driver chip 200 closest to the power chip.

[0041] refer to Figure 5 As shown, the pins of the gate driver chip 200 may further include a fault alarm signal output / enable input terminal Vfo / SD, an overcurrent detection input terminal CSC, a temperature signal output terminal VOT, a power supply terminal Vcc, a low-side signal input terminal LIN, and a high-side signal input terminal HIN, arranged sequentially along the first direction X and located on the side of the gate driver chip 200 away from the power chip. Another fault alarm signal output / enable input terminal Vfo / SD may also be provided between the high-side signal input terminal HIN and the signal ground terminal COM.

[0042] Figure 7 This is a three-dimensional schematic diagram of an intelligent power module provided in an embodiment of the present invention. Figure 8 A perspective view of an intelligent power module provided according to another embodiment of the present invention. (Reference) Figure 3 , Figure 7 and Figure 8 As shown, the intelligent power module may further include a molding compound 500, which may encapsulate multiple power chips, multiple gate driver chips 200, and a portion of the lead frame 100. The lead frame 100 includes multiple pins 106, with portions of the pins 106 exposed from the molding compound 500. Figure 7 and Figure 8 As shown, one end of multiple pins 106 extends from the sidewall of the molding compound 500.

[0043] In one embodiment, when pin 106 needs to be soldered to the surface of other components to achieve electrical connection, such as... Figure 7 As shown, the end of pin 106 exposed from the molded body 500 can extend in a plane perpendicular to the thickness direction (i.e., the Z direction) of the molded body 500, which facilitates the soldering of pin 106 to the surface of other components.

[0044] In one embodiment, when pin 106 needs to be inserted into other components to achieve electrical connection, such as... Figure 8As shown, the end of pin 106 exposed in the molding compound 500 can extend along the thickness direction (i.e., the Z direction) of the molding compound 500 so that pin 106 can be inserted into other components.

[0045] In this application, references Figure 3 , Figure 7 and Figure 8 As shown, a plurality of pins 106 of the lead frame 100 extend from the first side 100a and the second side 100b of the lead frame 100.

[0046] Table 1 lists the pin names and descriptions of the lead frame.

[0047]

[0048]

[0049] For details, please refer to Figure 3 , Figure 7 , Figure 8 As shown in Table 1, the multiple pins 106 include the second U-phase DC power supply negative pin NU2, the common ground pin COM, the W-phase power supply pin Vccw, the W-phase low-side signal input pin INWL, the W-phase high-side signal input pin INWH, the fault alarm signal output / enable input pin Vfo / SD, the overcurrent detection input pin CSC, the temperature signal output pin VOT, the V-phase power supply pin Vccv, the V-phase low-side signal input pin INVL, the V-phase high-side signal input pin INVH, the U-phase power supply pin Vccu, the U-phase low-side signal input pin INUL, the U-phase high-side signal input pin INUH, the common ground pin COM, and the first U-phase DC power supply negative pin NU1.

[0050] The multiple pins 106 also include a first DC power supply positive pin P, a W-phase high-side drive floating power supply pin VBw, a W-phase output pin / W-phase high-side drive floating power supply ground pin W,VSw, a W-phase DC power supply negative pin NW, a V-phase DC power supply negative pin NV, a V-phase output pin / V-phase high-side drive floating power supply ground pin V,VSv, a V-phase high-side drive floating power supply pin VBv, a U-phase high-side drive floating power supply pin VBu, and a U-phase output pin / U-phase high-side drive floating power supply ground pin U,VSu.

[0051] For details, please refer to Figure 3As shown, among the multiple pins of the lead frame 100, the second U-phase DC power supply negative pin NU2 and the first U-phase DC power supply negative pin NU1 are the two ends of the first conductive strip 107, which passes between the first base island 101 and the second base island 102. Both common ground pins COM are led out from the first base island 101. Pins 3 to 14 are independent pins and are arranged on the side of the first base island 101 away from the second base island 102. The first DC power supply positive pin P is led out from the second base island 102. The W-phase high-side drive floating power supply pin VBw is partially located between the first protrusion 102a of the second base island 102 and the third base island 103. The W-phase output pin / W-phase high-side drive floating power supply ground pins W,VSw are led out from the third base island 103. The W-phase DC power supply negative pin NW and the V-phase DC power supply negative pin NV are independent pins located between the third base island 103 and the fourth base island 104. The V-phase output pin / V-phase high-side drive floating power supply ground pin V,VSv is led out from the fourth base island 104. The V-phase high-side drive floating power supply pin VBv extends from between the fourth base island 104 and the third protrusion 102c to the side of the fourth base island 104 near the connection portion 102d. The U-phase high-side drive floating power supply pin VBu is partially located between the third protrusion 102c and the fifth base island 105. The U-phase output pin / U-phase high-side drive floating power supply ground pin U,VSu is led out from the fifth base island 105.

[0052] refer to Figure 3 , Figure 4 and Figure 5 As shown, in this embodiment, the control terminals of the first high-side power chip Q11, the second high-side power chip Q21, and the third high-side power chip Q31 are all connected to the high-side drive signal output terminal HO of the corresponding gate driver chip 200 via bonding wires 400. The first terminals of the first high-side power chip Q11, the second high-side power chip Q21, and the third high-side power chip Q31 are all connected to the second base island 102. The second terminals of the first high-side power chip Q11, the second high-side power chip Q21, and the third high-side power chip Q31 are all connected to the high-side drive floating power supply ground terminal VS of the corresponding gate driver chip 200 via bonding wires. The first high-side power chip Q11 is connected to the fifth base island 105 via a bonding wire 400 to connect with the U-phase output pin / U-phase high-side drive floating power supply ground pins U,VSu. The second high-side power chip Q21 is connected to the fourth base island 104 via a bonding wire 400 to connect with the V-phase output pin / V-phase high-side drive floating power supply ground pins V,VSv. The second high-side power chip Q31 is connected to the third base island 103 via a bonding wire 400 to connect with the W-phase output pin / W-phase high-side drive floating power supply ground pins W,VSw.

[0053] The control terminals of the first low-side power chip Q12, the second low-side power chip Q22, and the third low-side power chip Q32 are all connected to the low-side drive signal output terminal LO of the corresponding gate driver chip 200 via bonding wire 400. The first terminals of the first low-side power chip Q12, the second low-side power chip Q22, and the third low-side power chip Q32 are electrically connected to the fifth base island 105, the fourth base island 104, and the third base island 103, respectively. The second terminals of the first low-side power chip Q12, the second low-side power chip Q22, and the third low-side power chip Q32 are connected to the low-side drive reference ground terminal of the corresponding gate driver chip 200. VSS is electrically connected via bonding wire 400; wherein, the second end of the first low-side power chip Q12 is connected via bonding wire 400 to the first conductive strip 107 between the second U-phase DC power supply negative pin NU2 and the first U-phase DC power supply negative pin NU1, and the first conductive strip 107 is connected via bonding wire 400 to the low-side drive reference ground terminal VSS of the first gate driver chip 201; the second end of the second low-side power chip Q22 is also connected via bonding wire 400 to the V-phase DC power supply negative pin NV; the second end of the third low-side power chip Q32 is also connected via bonding wire 400 to the W-phase DC power supply negative pin NW.

[0054] Figure 6 This is a top view schematic diagram of a power chip provided according to an embodiment of the present invention. In this embodiment, reference is made to... Figure 3 and Figure 6 As shown, the power chip (including high-side power chip and low-side power chip) can be an IGBT. The gate 301 of the IGBT serves as the control terminal of the power chip, the collector of the IGBT serves as the first terminal of the power chip and is located on the base island corresponding to each power chip, and the emitter 302 of the IGBT serves as the second terminal of the power chip.

[0055] In another embodiment of this application, the power chip can be a MOS transistor, with the gate of the MOS transistor serving as the control terminal of the power chip, the drain of the MOS transistor serving as the first terminal of the power chip, and the source of the MOS transistor serving as the second terminal of the power chip.

[0056] Continue to refer to Figure 3 As shown, the high-side driving floating power supply terminal VB of the third gate driver chip 203 is connected to the high-side driving floating power supply pin VBw of the W phase via a bonding wire; the high-side driving floating power supply terminal VB of the second gate driver chip 202 is connected to the high-side driving floating power supply pin VBv of the V phase via a bonding wire; and the high-side driving floating power supply terminal VB of the first gate driver chip 201 is connected to the high-side driving floating power supply pin VBu of the U phase via a bonding wire.

[0057] refer to Figure 3 and Figure 5As shown, the signal ground terminal COM of the gate driver chip 200 is connected to the first base island 101 via bonding wires. The fault alarm signal output terminal / enable input terminal Vfo / SD of the third gate driver chip 203 and the second gate driver chip 202, which is close to the fault alarm signal output terminal / enable input pin Vfo / SD, is connected to the fault alarm signal output terminal / enable input pin Vfo / SD via bonding wires. One fault alarm signal output terminal / enable input terminal Vfo / SD of the first gate driver chip 201 is connected to another fault alarm signal output terminal / enable input terminal Vfo / SD of the second gate driver chip 202 via bonding wires.

[0058] For the first gate driver chip 201, its high-side signal input terminal HIN is connected to the U-phase high-side signal input pin INUH via a bonding wire, its low-side signal input terminal LIN is connected to the U-phase low-side signal input pin INUL via a bonding wire, and its power supply terminal Vcc is connected to the U-phase power supply pin Vccu via a bonding wire.

[0059] For the second gate driver chip 202, its high-side signal input terminal HIN is connected to the V-phase high-side signal input pin INVH via a bonding wire, its low-side signal input terminal LIN is connected to the V-phase low-side signal input pin INVL via a bonding wire, its power supply terminal Vcc is connected to the V-phase power supply pin Vccv via a bonding wire, its overcurrent detection input terminal CSC is connected to the overcurrent detection input pin CSC of the lead frame via a bonding wire, and its temperature signal output terminal VOT is connected to the temperature signal output pin VOT of the lead frame.

[0060] For the third gate driver chip 203, its high-side signal input terminal HIN is connected to the high-side signal input pin INWH of phase W through a bonding wire, its low-side signal input terminal LIN is connected to the low-side signal input pin INWL of phase W through a bonding wire, and its power supply terminal Vcc is connected to the power supply pin Vccw of phase W through a bonding wire.

[0061] In this application, the bonding wire can be a metal wire such as aluminum wire, copper wire, gold wire, or gold-palladium-copper wire.

[0062] The intelligent power module provided by this utility model includes a lead frame 100, multiple power chips, and multiple gate driver chips 200. The multiple power chips and multiple gate driver chips 200 are arranged in two rows. The multiple power chips include multiple groups of power chips arranged sequentially along a first direction. Each group of power chips includes a high-side power chip and a low-side power chip. In each group of power chips, the high-side power chip and the low-side power chip are arranged in the same order in the first direction and are all connected to a gate driver chip 200 through a bonding wire 400. The multiple gate driver chips 200 are the same type of chip with the same pin layout. Since the high-side power chip and the low-side power chip in each group of power chips are arranged in the same order in the first direction in this application, the multiple gate driver chips 200 can use the same chip, which helps to reduce the design and development cycle of the intelligent power module.

[0063] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.

Claims

1. A smart power module, characterized in that, include: Lead frame; Multiple power chips are mounted on the lead frame and arranged sequentially along a first direction; Multiple gate driver chips are mounted on the lead frame and arranged sequentially along the first direction; The plurality of power chips and the plurality of gate driver chips are arranged in two rows; the plurality of power chips include multiple groups of power chips arranged sequentially along the first direction, each group of power chips including a high-side power chip and a low-side power chip, wherein the high-side power chip and the low-side power chip in each group of power chips are arranged in the same order in the first direction and are all connected to a gate driver chip through bonding wires, and the plurality of gate driver chips are the same type of chip with the same pin layout.

2. The intelligent power module as described in claim 1, characterized in that, The plurality of power chips include a third high-side power chip, a third low-side power chip, a second high-side power chip, a second low-side power chip, a first high-side power chip, and a first low-side power chip arranged sequentially along a first direction.

3. The intelligent power module as described in claim 1, characterized in that, The pins of the gate driver chip include a high-side drive signal output terminal, a high-side drive floating power supply ground terminal, a low-side drive reference ground terminal, and a low-side drive signal output terminal arranged sequentially along the first direction; the control terminal of the high-side power chip is connected to the high-side drive signal output terminal of the corresponding gate driver chip, the second terminal of the high-side power chip is connected to the high-side drive floating power supply ground terminal of the corresponding gate driver chip, the second terminal of the low-side power chip is connected to the low-side drive reference ground terminal of the corresponding gate driver chip, and the control terminal of the low-side power chip is connected to the low-side drive signal output terminal of the corresponding gate driver chip.

4. The intelligent power module as described in claim 3, characterized in that, The gate driver chip also includes a high-side drive floating power supply terminal located between the high-side drive floating power supply ground terminal and the low-side drive reference ground terminal. The high-side drive signal output terminal, the high-side drive floating power supply ground terminal, the high-side drive floating power supply terminal, the low-side drive reference ground terminal, and the low-side drive signal output terminal are all located on the side of the gate driver chip closer to the power chip.

5. The intelligent power module as described in claim 1, characterized in that, The lead frame includes multiple base islands separated from each other, and multiple power chips and multiple gate driver chips are mounted on corresponding base islands; the first ends of the high-side power chip and the low-side power chip are connected to the corresponding base islands.

6. The intelligent power module as described in claim 1, characterized in that, The lead frame includes a first base island, a second base island, a third base island, a fourth base island, and a fifth base island separated from each other; the second base island, the third base island, the fourth base island, and the fifth base island are located on the same side of the first base island; the second base island has a first protrusion, a second protrusion, a third protrusion protruding in a direction away from the first base island, and a connecting portion connecting two adjacent protrusions; the third base island is partially located between the first protrusion and the second protrusion, and the fourth base island is partially located between the second protrusion and the third protrusion.

7. The intelligent power module as described in claim 6, characterized in that, Multiple gate driver chips are mounted on the first base island; a first high-side power chip is mounted on the third protrusion, a second high-side power chip is mounted on the second protrusion, and a third high-side power chip is mounted on the first protrusion; a third low-side power chip, a second low-side power chip, and a first low-side power chip are respectively mounted on the third base island, the fourth base island, and the fifth base island.

8. The intelligent power module as described in claim 7, characterized in that, The lead frame further includes a first conductive strip located between the first base island and the second base island and extending in the first direction. At least one end of the first conductive strip extends a pin to the outside of the plastic package of the smart power module. The second end of the first low-side power chip is connected to the first conductive strip via a bonding wire, and the first conductive strip is connected to the low-side drive reference ground of the gate drive chip corresponding to the first low-side power chip via a bonding wire.

9. The intelligent power module as described in claim 1, characterized in that, The power chip is an RC-IGBT, the gate of the RC-IGBT serves as the control terminal of the power chip, the collector of the RC-IGBT serves as the first terminal of the power chip and is located on the base island corresponding to each power chip, and the emitter of the RC-IGBT serves as the second terminal of the power chip.

10. The intelligent power module as described in claim 1, characterized in that, The power chip is a MOS transistor, with the gate of the MOS transistor serving as the control terminal of the power chip, the drain of the MOS transistor serving as the first terminal of the power chip, and the source of the MOS transistor serving as the second terminal of the power chip.

11. The intelligent power module as described in claim 1, characterized in that, The power chip includes an IGBT and a fast recovery diode. The gate of the IGBT serves as the control terminal of the power chip. The emitter of the IGBT is electrically connected to the anode of the fast recovery diode and serves as the second terminal of the power chip. The collector of the IGBT is electrically connected to the cathode of the fast recovery diode and serves as the first terminal of the power chip. The collector of the IGBT and the cathode of the fast recovery diode are located on the base islands corresponding to each power chip.

12. The intelligent power module as described in claim 1, characterized in that, The intelligent power module also includes a molding compound that encapsulates multiple power chips, multiple gate driver chips, and a portion of the lead frame. The lead frame includes multiple pins, with portions of the pins exposed from the molding compound.

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