Power amplifier circuit, radio frequency chip and electronic device

Abstract

The embodiment of the present disclosure discloses a power amplifier circuit, a radio frequency chip and an electronic device. The power amplifier circuit comprises: at least two stages of power amplifiers in cascade; a low-frequency resonant network comprising a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a ground end; the second capacitor is coupled between a first end of the power amplifier and the ground end; the first inductor is coupled between the first capacitor and the second capacitor; and the first capacitor comprises a decoupling capacitor.

Description

Technical Field

[0001] This disclosure relates to the field of radio frequency power amplifiers, and more particularly to a power amplifier circuit, radio frequency chip, and electronic device. Background Technology

[0002] Due to layout limitations, limited active chip isolation design, DC power network multiplexing, a small number of bypass capacitors, and constraints such as digital-to-analog crosstalk and RF line coupling, existing radio frequency front-end module (RF FEM) chips can experience instability during operation. This is especially true for the radio frequency power amplifier (RF PA) within the RF FEM chip. Improving the stability of the RF power amplifier has become a challenge in RF FEM chip design. Utility Model Content

[0003] In view of this, embodiments of the present disclosure provide a power amplifier circuit, an RF chip, and an electronic device.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a power amplifier circuit, the power amplifier circuit comprising:

[0006] At least two cascaded power amplifiers;

[0007] A low-frequency resonant network includes a first capacitor, a second capacitor, and a first inductor; the first capacitor is coupled between a power supply terminal and a ground terminal; the second capacitor is coupled between a first terminal of the power amplifier and the ground terminal; the first inductor is coupled between the first capacitor and the second capacitor; the first capacitor includes a decoupling capacitor.

[0008] In some embodiments, the power amplifier circuit further includes:

[0009] The first gain reduction network includes a third capacitor, a second inductor, and a first resistor; the second inductor and the first resistor are connected in series between the RF input terminal and the second terminal of the first-stage power amplifier; the third capacitor is connected between the RF input terminal and the second terminal of the first-stage power amplifier.

[0010] In some embodiments, the first gain reduction network further includes:

[0011] A first switch; the first switch is connected in series in the branch where the second inductor is located; the first switch controls the second inductor and the first resistor to be connected to the power amplifier circuit.

[0012] In some embodiments, the power amplifier circuit further includes:

[0013] The second gain reduction network includes a fourth capacitor, a third inductor, and a second resistor connected in series; the second gain reduction network is coupled between the ground terminal and the second terminal of the first-stage power amplifier.

[0014] In some embodiments, the second gain reduction network further includes:

[0015] The second switch is connected in series in the branch where the fourth capacitor is located; the second switch controls the fourth capacitor, the third inductor and the second resistor to be connected to the power amplifier circuit.

[0016] In some embodiments, the second gain reduction network further includes:

[0017] A fifth capacitor and a third switch; the fifth capacitor and the third switch are connected in series between the two ends of the fourth capacitor; the third switch controls the fifth capacitor to be connected to the power amplifier circuit.

[0018] In some embodiments, the power amplifier circuit further includes:

[0019] The third gain reduction network includes multiple series-connected forward diodes and multiple series-connected reverse diodes; the multiple series-connected forward diodes and the multiple series-connected reverse diodes are connected in parallel between the second terminal of the second-stage power amplifier and the ground terminal.

[0020] In some embodiments, the third gain reduction network further includes:

[0021] The switch short-circuit network includes a fourth switch connected in parallel with any of the forward diodes and a fifth switch connected in parallel with any of the reverse diodes; the fourth switch controls the forward diodes to be connected to the power amplifier circuit; the fifth switch controls the reverse diodes to be connected to the power amplifier circuit.

[0022] In some embodiments, the power amplifier circuit further includes:

[0023] The first matching network includes a sixth capacitor and a fourth inductor; the sixth capacitor and the fourth inductor are connected in series between the first terminal of the second-stage power amplifier and the ground terminal.

[0024] In some embodiments, the power amplifier circuit further includes:

[0025] The second matching network includes a seventh capacitor and a fifth inductor; the seventh capacitor and the fifth inductor are connected in parallel between the first terminal and the RF output terminal of the second-stage power amplifier.

[0026] In some embodiments, the first-stage power amplifier includes a driver-stage power amplifier and a final-stage power amplifier.

[0027] Secondly, embodiments of this disclosure provide a radio frequency chip, the radio frequency chip including any of the power amplifier circuits described above.

[0028] Thirdly, embodiments of this disclosure provide an electronic device, which includes any of the power amplifier circuits described above, or the radio frequency chip described above.

[0029] In this embodiment, a low-frequency resonant network is connected between the first terminal of the power amplifier and the power supply terminal. This low-frequency resonant network includes a π-type low-pass filter composed of decoupling capacitors. Thus, the low-frequency resonant network can, on the one hand, filter out the AC component in the DC power supply based on the principle of low-pass filtering, while retaining the DC component. On the other hand, the low-frequency resonant network can utilize the lowest impedance characteristic of the decoupling capacitors at their self-resonant frequency to absorb noise energy at a specific frequency, thereby achieving filtering out specific resonant frequencies. Attached Figure Description

[0030] Figure 1 Here is a circuit diagram of a power amplifier circuit in an example.

[0031] Figure 2 A circuit diagram of a power amplifier circuit provided in an embodiment of this disclosure;

[0032] Figure 3 A circuit diagram of a first type of low-frequency resonant network provided in an embodiment of this disclosure;

[0033] Figure 4 The spectrum diagram of the output signal after suppressing harmonics using a low-frequency resonant network, as provided in the embodiments of this disclosure;

[0034] Figure 5 A circuit diagram of another power amplifier circuit provided for an embodiment of this disclosure;

[0035] Figure 6 A circuit diagram of a second type of low-frequency resonant network provided in an embodiment of this disclosure;

[0036] Figure 7 A circuit diagram of the first reduced-gain network provided in an embodiment of this disclosure;

[0037] Figure 8The spectrum of the signal output after harmonic suppression using a first gain reduction network, as provided in an embodiment of this disclosure;

[0038] Figure 9 A circuit diagram of the second degaussing network provided in an embodiment of this disclosure;

[0039] Figure 10 The spectrum of the signal output after harmonic suppression using a second gain reduction network, as provided in an embodiment of this disclosure;

[0040] Figure 11 A circuit diagram of the third gain reduction network provided in an embodiment of this disclosure;

[0041] Figure 12 Circuit diagrams of the first and second matching networks provided for embodiments of this disclosure;

[0042] Figure 13 The spectrum diagram of the output signal after suppressing harmonics using a first matching network and a second matching network, provided in an embodiment of this disclosure. Detailed Implementation

[0043] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0045] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0050] A cascaded power amplifier is a high-performance amplifier circuit structure, particularly suitable for high-frequency (RF, microwave) and high-gain applications. It effectively overcomes some of the key limitations of single-transistor amplifiers in high-frequency applications by cleverly connecting two active devices (typically transistors) together in a specific manner.

[0051] Figure 1 This is a circuit diagram of a power amplifier circuit in an example.

[0052] like Figure 1 As shown, the power amplifier circuit 100 includes a cascaded driver power amplifier (Driver PA) 101 and a final power amplifier (Final PA) 102. The driver power amplifier 101 is coupled between the RF signal input terminal Term1 and the final power amplifier 102, and is connected to the drive voltage Driver VCC. The driver power amplifier 101 amplifies the RF input signal Rfin received from the RF signal input terminal Term1 and outputs it to the final power amplifier 102 to provide sufficient voltage / current drive capability. The final power amplifier 102 is connected to the final voltage Final VCC, and its output terminal is connected to the RF output terminal Term2. The final power amplifier 102 converts the signal amplified by the driver power amplifier 101 into high-power, low-impedance electrical energy output to drive terminal loads (such as speakers, antennas, motors, etc.).

[0053] It should be noted that, as Figure 1 The single-cascaded power amplifier designs shown are all based on an ideal input of 50 ohms, which results in low return loss. However, in practical module applications, RF reflections are significantly higher than the ideal 50 ohms, and the reflected energy can cause instability in the power amplifier circuit and damage to components.

[0054] In RF front-end module chips, the factors that cause instability in power amplifier circuits are quite complex. In order to improve the stability of power amplifier circuits, it is necessary to consider the effects of RF coupling, DC power supply, digital-to-analog signal crosstalk, and other power amplifier circuits in the module, which involves the problem of multi-frequency resonance.

[0055] In view of the above, embodiments of this disclosure provide a power amplifier circuit, the power amplifier circuit comprising: at least two cascaded power amplifiers; a low-frequency resonant network including a first capacitor, a second capacitor, and a first inductor; the first capacitor being coupled between a power supply terminal and a ground terminal; the second capacitor being coupled between a first terminal of the power amplifier and a ground terminal; the first inductor being coupled between the first capacitor and the second capacitor; the first capacitor including a decoupling capacitor.

[0056] Figure 2 A circuit diagram of a power amplifier circuit 200 provided for an embodiment of this disclosure.

[0057] like Figure 2 As shown, the power amplifier circuit 200 includes a cascaded first-stage power amplifier 201 and a second-stage power amplifier 202. The first-stage power amplifier 201 is coupled to the RF signal input terminal Term1. Specifically, the second terminal of the first-stage power amplifier 201 is coupled to the RF signal input terminal Term1, which is used to receive the RF input signal Rfin. The second-stage power amplifier 202 is coupled to the RF signal output terminal Term2. Specifically, the third terminal of the second-stage power amplifier 202 is coupled to the RF signal output terminal Term2, which is used to output the RF output signal Rfout.

[0058] The low-frequency resonant network 203 is coupled between each power amplifier and the power supply terminal. Specifically, the low-frequency resonant network 203 is coupled between the first terminal of the first-stage power amplifier 201 and the power supply terminal, and the low-frequency resonant network 203 is coupled between the first terminal of the second-stage power amplifier 202 and the power supply terminal, with the power supply terminal connected to the DC power supply VCC.

[0059] In some embodiments, the first-stage power amplifier 201 and the second-stage power amplifier 202 can each be a transistor, such as a heterojunction bipolar transistor (HBT). Thus, the first terminal of the first-stage power amplifier 201 or the second-stage power amplifier 202 can be the collector of the transistor, the second terminal of the first-stage power amplifier 201 or the second-stage power amplifier 202 can be the base of the transistor, and the third terminal of the first-stage power amplifier 201 or the second-stage power amplifier 202 can be the emitter of the transistor.

[0060] Figure 3 A circuit diagram of a first low-frequency resonant network 203 provided in an embodiment of this disclosure.

[0061] like Figure 3As shown, the low-frequency resonant network 203 includes a first capacitor C1, a second capacitor C2, and a first inductor L1. The first capacitor C1 includes a decoupling capacitor and is coupled between the power supply terminal and the ground terminal. The second capacitor C2 is coupled between the first terminal of the power amplifier and the ground terminal. The first inductor L1 is coupled between the first capacitor C1 and the second capacitor C2. Thus, the first capacitor C1, the second capacitor C2, and the first inductor L1 together form a π-type low-pass filter (LPF) coupled between the first terminal and the power supply terminal of the power amplifier.

[0062] It should be noted that, as mentioned above, the RF front-end module suffers from multi-frequency resonance, which affects the stability of the power amplifier circuit. Specifically, the DC power supply VCC connected to the first terminal of the first-stage power amplifier 201 and the first terminal of the second-stage power amplifier 202 may contain low-frequency or high-frequency AC components. These AC components in the DC power supply can affect the normal operation of the power amplifier, thus impacting the stability of the power amplifier circuit.

[0063] Figure 4 This is a spectrum diagram of the signal output after harmonic suppression using a low-frequency resonant network, as provided in an embodiment of this disclosure. Figure 4 As shown, the low-frequency resonant network 203 essentially filters out the AC component in the DC power supply. Furthermore, the low-frequency resonant network 203 utilizes the self-resonant frequency of the decoupling capacitor to suppress the 810MHz resonant frequency.

[0064] In this embodiment, a low-frequency resonant network 203 is connected between the first terminal and the power supply terminal of the cascaded power amplifier. This low-frequency resonant network 203 includes a π-type low-pass filter composed of decoupling capacitors. This allows the low-frequency resonant network 203 to filter out the AC component in the DC power supply VCC while retaining the DC component, based on the principle of low-pass filtering. Furthermore, the low-frequency resonant network 203 can utilize the lowest impedance characteristic of the decoupling capacitor (i.e., the first capacitor C1) at the self-resonant frequency (SRF) to absorb noise energy at specific frequencies, thus achieving filtering out specific resonant frequencies. This effectively improves the stability of the power amplifier circuit.

[0065] In some embodiments, the first-stage power amplifier 201 includes a driver-stage power amplifier and a final-stage power amplifier.

[0066] In some embodiments, the power supply terminals include a first power supply terminal coupled to the first-stage power amplifier 201 and a second power supply terminal coupled to the second-stage power amplifier 202, such as... Figure 2 As shown.

[0067] Continue to refer to Figure 3 When the power supply includes a first power supply terminal and a second power supply terminal, the low-frequency resonant network 203 includes two first capacitors C1, two second capacitors C2, and two first inductors L1. Furthermore, the two first capacitors C1, two second capacitors C2, and two first inductors L1 form two independent π-type low-pass filters. Figure 3 As shown, one of the π-type low-pass filters is connected to the first terminal of the first-stage power amplifier. Figure 3 As shown in the diagram, between PA1_Collector and the first power supply terminal, the first power supply terminal is used to connect to the first power supply voltage, for example, the drive voltage Driver VCC. Another π-type low-pass filter is connected to the first terminal of the second-stage power amplifier (…). Figure 3 The second power supply terminal is used to connect a second power supply voltage, such as the final stage voltage FinalVCC, between PA2_Collector and the second power supply terminal shown in the diagram.

[0068] In another embodiment, the first-stage power amplifier 201 and the second-stage power amplifier 202 are coupled to the same power supply terminal via a low-frequency resonant network 501, which is used to connect to the power supply voltage VCC. Figure 5 As shown, Figure 5 A circuit diagram of another power amplifier circuit 500 provided in an embodiment of this disclosure.

[0069] Figure 6 A circuit diagram of a second low-frequency resonant network 501 provided in an embodiment of this disclosure. (See diagram below.) Figure 6 As shown, when cascaded power amplifiers are connected to the same power supply terminal, the low-frequency resonant network 501 includes a first capacitor C1, two second capacitors C2, and two first inductors L1. The first capacitor C1, together with the second capacitors C2 and the first inductors L1 located in two different branches, forms two π-type low-pass filters. In other words, the two π-type low-pass filters share a first capacitor C1. Thus, one π-type low-pass filter is connected to the first terminal of the first-stage power amplifier (…). Figure 6 Between PA1_Collector (shown in the diagram) and the power supply terminal, another π-type low-pass filter is connected to the first terminal of the second-stage power amplifier. Figure 6 The PA2_Collector shown is located between the power supply terminal and the power supply terminal.

[0070] In this embodiment of the disclosure, the power amplifier circuit can be integrated into the power amplifier chip, and the power amplifier chip can be packaged with other chips or devices to form an RF front-end module chip.

[0071] It should be noted that since the same power amplifier chip may exhibit different characteristics in different RF front-end module chips, using the same power amplifier chip in different RF front-end module chips may result in an excessively long debugging cycle for the RF front-end module chips.

[0072] To shorten the debugging cycle of the RF front-end module chip, in some embodiments, the low-frequency resonant network further includes at least one regulating capacitor C′ and at least one regulating switch k′, the same number as the regulating capacitor C′. The regulating capacitor C′ serves as a decoupling capacitor. Each regulating capacitor C′ and its corresponding regulating switch k′ are connected in series and then in parallel across the first capacitor C1.

[0073] like Figure 6 As shown, the low-frequency resonant network 501 includes an adjusting capacitor C′ and an adjusting switch k′. When the adjusting switch k′ is closed, its branch is conducting, causing the adjusting capacitor C′ to be connected to the power amplifier circuit 500. At this time, two decoupling capacitors are connected in the power amplifier circuit 500, namely the first capacitor C1 and the adjusting capacitor C′. The self-resonant frequencies of the first capacitor C1 and the adjusting capacitor C′ can be used to suppress the two resonant frequencies in the DC power supply.

[0074] In this embodiment, the opening and closing of the adjustment switch k′ can be controlled according to actual needs to connect different numbers of adjustment capacitors C′ in the power amplifier circuit. This allows for flexible adjustment of the suppression frequency, shortening the debugging cycle. Simultaneously, the introduction of the adjustment capacitor C′ enables the low-frequency resonant network to suppress at least two resonant frequencies, thereby solving the multi-stage crosstalk problem.

[0075] In other embodiments, at least one regulating capacitor C′ and an equal number of regulating switches k′ are located within the RF front-end module chip and outside the power amplifier circuit. The regulating capacitor C′ serves as a decoupling capacitor. Each regulating capacitor C′ and its corresponding regulating switch k′ are connected in series and then in parallel across the first capacitor C1. When a regulating switch k′ is closed, its branch is turned on, connecting the regulating capacitor C′ in that branch to the RF front-end module chip. At this point, at least two decoupling capacitors are connected to the RF front-end module chip. The self-resonant frequency of these two decoupling capacitors can suppress at least two resonant frequencies in the DC power supply, thus solving the multi-stage crosstalk problem. Simultaneously, flexible adjustment of the suppression frequency can be achieved, shortening the debugging cycle.

[0076] In this embodiment of the disclosure, the capacitance value of the first capacitor C1 can be set according to actual needs to achieve suppression of a specific resonant frequency. In some embodiments, the first capacitor C1 is used to filter out low-frequency interference frequencies lower than the center frequency f0 of the RF input signal. For example, the first capacitor is used to filter out the interference frequency at (f0 / 2).

[0077] In some embodiments, the capacitance value of the adjusting capacitor C′ is less than the capacitance value of the first capacitor C1.

[0078] In some embodiments, the power amplifier circuit further includes a first drop-gain network 204, such as Figure 2 As shown, the first down-gain network 204 is coupled between the RF signal input terminal Term1 and the first-stage power amplifier 201.

[0079] In some embodiments, the first gain reduction network 204 includes a third capacitor C3, a second inductor L2, and a first resistor R1; the second inductor L2 and the first resistor R1 are connected in series between the RF signal input terminal Term1 and the second terminal of the first-stage power amplifier 201. Figure 7 Between PA1_Base); the third capacitor C3 is connected between the RF signal input terminal Term1 and the second terminal of the first-stage power amplifier 201, such as Figure 7 As shown, Figure 7 A circuit diagram of a first reduced-gain network provided for an embodiment of this disclosure.

[0080] In this embodiment, during the transmission of the RF input signal RFin through the first drop-gain network 204 to the first-stage power amplifier 201, the high-frequency signal in the RF input signal RFin flows through the branch containing the third capacitor C3, which allows the high-frequency signal to pass. The low-frequency signal in the RF input signal RFin flows through the branch containing the second inductor L2 and the first resistor R1. The first resistor R1 causes loss to the low-frequency signal, thereby suppressing low-frequency resonance. Thus, the third capacitor C3, the second inductor L2, and the first resistor R1 together form a high-pass network, such as... Figure 8 As shown, Figure 8 The spectrum diagram of the signal output after suppressing harmonics using a first gain reduction network, as provided in an embodiment of this disclosure.

[0081] Figure 8 The 800MHz frequency point shown is a low-frequency resonant point located outside the passband of the RF input signal, while Figure 8 The 2GHz frequency shown is located within the passband of the RF input signal. According to... Figure 8As can be seen, the first gain reduction network 204 suppresses low-frequency resonance outside the passband while also reducing the gain within the passband. It should be noted that appropriately reducing the gain of the RF input signal within the passband can prevent the overall gain of the power amplifier circuit from becoming too high, thereby improving the stability of the power amplifier circuit.

[0082] Continue to refer to Figure 8 , Figure 8 The diagram shows the spectrum of the signals output by the first drop-gain network 204 corresponding to multiple third capacitors C3 with different capacitance values. Furthermore, the smaller the capacitance value of the third capacitor C3, the less suppression the first drop-gain network 204 provides at the 800MHz and 2GHz frequencies. Therefore, embodiments of this disclosure can select a third capacitor C3 with a specific capacitance value according to actual design requirements to achieve suppression of specific frequencies and adjustment of the gain.

[0083] In some embodiments, the first gain reduction network 204 further includes: a first switch k1; the first switch k1 is connected in series in the branch where the second inductor L2 is located; that is, the first switch k1 is connected in series with the second inductor L2 and the first resistor R1; the first switch k1 controls the second inductor L2 and the first resistor R1 to be connected to the power amplifier circuit, such as... Figure 7 As shown.

[0084] Specifically, when the first switch k1 is open, the branch containing the second inductor L2 and the first resistor R1 is disconnected, and the second inductor L2 and the first resistor R1 are not connected to the power amplifier circuit. At this time, only the third capacitor C3 in the first gain reduction network 204 is connected to the power amplifier circuit, and the third capacitor C3 participates in the input matching of the power amplifier circuit. When the first switch k1 is closed, the branch containing the second inductor L2 and the first resistor R1 is connected, and the third capacitor C3, the second inductor L2, and the first resistor R1 are all connected to the power amplifier circuit. At this time, the third capacitor C3, the second inductor L2, and the first resistor R1 together form a high-pass network, which can suppress low-frequency resonance outside the passband while reducing the gain within the passband.

[0085] In other embodiments, the power amplifier circuit further includes a second drop-gain network 502, such as... Figure 5 As shown, the second down-gain network 502 is coupled between the RF signal input terminal Term1 and the first-stage power amplifier 201.

[0086] In some embodiments, the second drop-gain network 502 includes a fourth capacitor C4, a third inductor L3, and a second resistor R2 connected in series; the second drop-gain network 502 is coupled to the ground terminal and the second terminal of the first-stage power amplifier 201. Figure 9 Between PA1_Base, such as Figure 9 As shown, Figure 9 A circuit diagram of a second degaussing network provided in an embodiment of this disclosure.

[0087] In this embodiment, the fourth capacitor C4, the third inductor L3, and the second resistor R2 together form a series resonant circuit. Utilizing the extremely low impedance characteristic of this series resonant circuit at a specific frequency (resonance point), efficient frequency selection and energy transfer can be achieved. In other words, the second gain-reducing network 502 can suppress harmonics at specific frequencies, thereby improving the stability of the power amplifier circuit 500.

[0088] Figure 10 The spectrum diagram of the output signal after harmonic suppression using the second gain reduction network provided in the embodiments of this disclosure is shown below. Figure 10 As shown, this embodiment of the present disclosure utilizes a second gain reduction network 502 to suppress harmonics at the 790MHz frequency point.

[0089] In this embodiment of the disclosure, in addition to suppressing harmonics at specific frequency points, the second gain reduction network 502 can also be used to participate in input matching.

[0090] In some embodiments, the second gain reduction network 502 further includes: a second switch k2; the second switch k2 is connected in series in the branch where the fourth capacitor C4 is located; the second switch k2 controls the fourth capacitor C4, the third inductor L3, and the second resistor R2 to be connected to the power amplifier circuit, such as... Figure 9 As shown.

[0091] Specifically, when the second switch k2 is in the open state, the branch containing the fourth capacitor C4, the third inductor L3, and the second resistor R2 is disconnected, and these components are not connected to the power amplifier circuit 500. When the second switch k2 is in the closed state, the branch containing the fourth capacitor C4, the third inductor L3, and the second resistor R2 is connected, and these components are connected to the power amplifier circuit 500. In this case, the second gain reduction network 502 can suppress resonance at a specific frequency.

[0092] In some embodiments, the second gain reduction network 502 further includes: a fifth capacitor C5 and a third switch k3; the fifth capacitor C5 and the third switch k3 are connected in series between the two ends of the fourth capacitor C4; the third switch k3 controls the fifth capacitor C5 to be connected to the power amplifier circuit 500, such as... Figure 9 As shown.

[0093] Specifically, when the third switch k3 is in the open state, the fifth capacitor C5 is not connected to the power amplifier circuit 500. When the third switch k3 is in the closed state, the fifth capacitor C5 is connected to the power amplifier circuit 500. At this time, the fourth capacitor C4, the third inductor L3, the second resistor R2, and the fifth capacitor C5 together form a resonant network.

[0094] In some embodiments, the capacitance of the fifth capacitor C5 is less than that of the fourth capacitor C4. The fourth capacitor C4 plays a major role in selecting the suppression frequency, while the fifth capacitor C5 can adjust the suppression frequency within a small range (e.g., offsetting the suppression frequency by 50MHz). Thus, when the suppression frequency corresponding to the series resonant circuit formed by the fourth capacitor C4, the third inductor L3, and the second resistor R2 is not the target frequency, a small-range adjustment of the suppression frequency can be achieved by connecting the fifth capacitor C5 in the second gain reduction network 502, thereby making the adjusted suppression frequency equal to the target frequency. This enables flexible adjustment of the suppression frequency and shortens the debugging cycle of the RF front-end module chip.

[0095] In some embodiments, the power amplifier circuit further includes a third gain reduction network 205, such as Figure 2 and Figure 5 As shown, the third drop-gain network 205 is coupled between the first-stage power amplifier 201 and the second-stage power amplifier 202. Specifically, an interstage matching network 209 is also connected between the first-stage power amplifier 201 and the second-stage power amplifier 202, and the third drop-gain network 205 is coupled between the output terminal of the interstage matching network 209 and the second terminal of the second-stage power amplifier 202.

[0096] In some embodiments, the third gain reduction network 205 includes a plurality of series-connected forward diodes D1 and a plurality of series-connected reverse diodes D2; the plurality of series-connected forward diodes D1 and the plurality of series-connected reverse diodes D2 are connected in parallel to the second terminal of the second-stage power amplifier. Figure 11 Between PA2_Base and ground, such as Figure 11 As shown.

[0097] In this embodiment, a third drop-gain network 205 is coupled between the first terminal of the first-stage power amplifier 201 and the second terminal of the second-stage power amplifier 202. The third drop-gain network 205 is used to limit the signal output from the first terminal of the first-stage power amplifier 201. Specifically, when the voltage V1 output from the first terminal of the first-stage power amplifier 201 is less than the forward voltage drop V of the diode... F When the signal is small, neither the forward diode D1 nor the reverse diode D2 conducts. When the voltage V1 output from the first terminal of the first-stage power amplifier 201 is greater than the forward voltage drop V of the diode... FDuring a large signal period, in the positive half-cycle, the forward diode D1 is turned on, and the reverse diode D2 is turned off in reverse. The voltage V2 output from the third drop-gain network 205 to the second terminal of the second-stage power amplifier 202 is clamped at V. F (Cut off the part above V) F (Partial). During the negative half-cycle, the forward diode D1 is reverse-biased and the reverse diode D2 is turned on. The voltage V2 output from the third drop-gain network 205 to the second terminal of the second-stage power amplifier 202 is clamped at V. F .

[0098] Thus, when the signal output from the first terminal of the first-stage power amplifier 201 is a large signal, the third drop-gain network 205 can not only suppress the voltage fluctuation of the signal output from the first terminal of the first-stage power amplifier 201, thereby improving the stability of the power amplifier circuit; the third drop-gain network 205 can also prevent the second-stage power amplifier 202 from being burned out due to the power exceeding the upper limit.

[0099] In some embodiments, the third gain reduction network 205 includes three to five forward diodes D1 and an equal number of reverse diodes D2. Here, the number of forward diodes D1 and the number of reverse diodes D2 can be selected according to specific requirements. Figure 11 The diagram illustrating the third drop-gain network 205, which includes three forward diodes D1 and three reverse diodes D2, is merely an example.

[0100] In some embodiments, the third gain reduction network 205 further includes: a switch short-circuit network, including a fourth switch k4 connected in parallel with any forward diode D1, and a fifth switch k5 connected in parallel with any reverse diode D2; the fourth switch k4 controls the forward diode D1 to be connected to the power amplifier circuit; the fifth switch k5 controls the reverse diode D2 to be connected to the power amplifier circuit.

[0101] In some embodiments, such as Figure 11 As shown, the third gain reduction network 205 includes a number of fourth switches k4 equal to the number of forward diodes D1, and a number of fifth switches k5 equal to the number of reverse diodes D2. Each fourth switch k4 is connected in parallel with a forward diode D1, and each fifth switch k5 is connected in parallel with a reverse diode D2. Thus, each fourth switch k4 can control the connection of its parallel forward diode D1 to the power amplifier circuit, and each fifth switch k5 can control the connection of its parallel reverse diode D2 to the power amplifier circuit.

[0102] In other embodiments, the number of fourth switches k4 may be less than the number of forward diodes D1, and the number of fifth switches k5 may be less than the number of reverse diodes D2.

[0103] In one example, the third gain reduction network includes N (N>3) forward diodes D1 and N reverse diodes D2. The switching short-circuit network includes a fourth switch k4 connected in parallel with (N-3) arbitrary forward diodes D1 and a fifth switch k5 connected in parallel with (N-3) arbitrary reverse diodes D2. Thus, at least three forward diodes D1 and three reverse diodes D2 in the third gain reduction network are always connected to the power amplifier circuit. Furthermore, when the fourth switch k4 is open, it controls the forward diodes D1 connected in parallel to it to be connected to the power amplifier circuit. When the fourth switch k4 is closed, it controls the forward diodes D1 connected in parallel to it to be disconnected from the power amplifier circuit. When the fifth switch k5 is open, it controls the reverse diodes D2 connected in parallel to it to be connected to the power amplifier circuit. When the fifth switch k5 is closed, it controls the reverse diodes D2 connected in parallel to it to be disconnected from the power amplifier circuit. This allows for flexible adjustment of the number of forward diodes D1 and reverse diodes D2 connected to the power amplifier circuit, shortening the debugging cycle of the RF front-end module chip.

[0104] In some embodiments, the power amplifier circuit 200 further includes: a first matching network 206, including a sixth capacitor C6 and a fourth inductor L4; the sixth capacitor C6 and the fourth inductor L4 are connected in series at the first terminal of the second-stage power amplifier 202. Figure 12 Between PA2_Collector and ground, such as Figure 12 As shown.

[0105] Here, the sixth capacitor C6 and the fourth inductor L4 together form a notch filter. The notch filter can suppress harmonics at specific frequencies in the signal output from the first terminal of the second-stage power amplifier 202, thereby improving the stability of the power amplifier circuit. Furthermore, the first matching network 206 can also be used to form the output matching network 207 of the power amplifier circuit 200. The output matching network 207 is used to convert the external load resistance to the optimal load resistance required by the power amplifier circuit 200 to ensure maximum output power.

[0106] In some embodiments, the first matching network 206 further includes another capacitor C connected in parallel across the sixth capacitor C6 and a switch k (capacitor C and switch k). Figure 12 (Not shown in the diagram), switch k can selectively connect capacitor C to the first matching network 206, thereby enabling flexible adjustment of the suppression frequency and shortening the debugging cycle of the RF front-end module chip.

[0107] In some embodiments, the power amplifier circuit 500 further includes: a second matching network 503, including a seventh capacitor C7 and a fifth inductor L5; the seventh capacitor C7 and the fifth inductor L5 are connected in parallel to the first terminal of the second-stage power amplifier 202. Figure 12 Between PA2_Collector and the RF output terminal, such as Figure 12 As shown.

[0108] Here, the seventh capacitor C7 and the fifth inductor L5 together form a resonant circuit (tank). This resonant circuit can suppress harmonics at specific frequencies in the signal output from the first terminal of the second-stage power amplifier 202, thereby improving the stability of the power amplifier circuit. Furthermore, the second matching network 503 can also be used to form the output matching network 504 of the power amplifier circuit 500. The output matching network 504 is used to convert the external load resistance to the optimal load resistance required by the power amplifier circuit 500 to ensure maximum output power.

[0109] In other embodiments, the power amplifier circuit includes both a first matching network 206 and a second matching network 503, such as... Figure 12 As shown, the first matching network 206 and the second matching network 503 are used to suppress harmonics at different frequencies. For example, the first matching network 206 is used to suppress harmonics at frequency 2f0, and the second matching network 503 is used to suppress harmonics at frequency 3f0. Furthermore, the first matching network 206 and the second matching network 503 can together form the output matching network of the power amplifier circuit.

[0110] refer to Figure 13 , Figure 13 The spectrum diagram of the output signal after suppressing harmonics using a first matching network and a second matching network, provided in an embodiment of this disclosure. Figure 13 Taking f0 as 800MHz as an example, the first matching network 206 and the second matching network 503 are used to suppress the harmonics at the 1.63GHz (approximately 2f0) frequency point and the 2.44GHz (approximately 3f0) frequency point, respectively.

[0111] In some embodiments, the power amplifier circuit 200 further includes an input matching network 208 and an interstage matching network 209, such as Figure 2 As shown.

[0112] The input matching network 208 is used to match the output impedance of the signal source with the input impedance of the first-stage power amplifier 201, so that the first-stage power amplifier 201 obtains the maximum excitation power. The inter-stage matching network 209 can act as a buffer between the first-stage power amplifier 201 and the second-stage power amplifier 202, thereby optimizing impedance transformation and reducing signal reflection.

[0113] It should be noted that the closing and opening of the switches mentioned above in this embodiment are controlled by control signals provided by a control circuit located outside the power amplifier circuit. In practical applications, the closing or opening of the first switch can be controlled by different control signals according to different application scenarios (e.g., applying the power amplifier circuit to different modules), thereby achieving flexible adjustment of the suppression frequency and shortening the debugging cycle of the RF front-end module chip.

[0114] In this embodiment of the disclosure, by means of Figure 1 The single-cascaded power amplifier circuit shown incorporates a low-frequency resonant network, a first reduction-gain network, a second reduction-gain network, a third reduction-gain network, a first matching network, and a second matching network. Analysis of gain, resonant frequency, and DC coupling effectively improves the stability of the power amplifier circuit. Furthermore, the power amplifier circuit of this embodiment can flexibly adjust the suppression frequency and gain for different RF front-end module chips, exhibiting strong versatility, reducing the design difficulty of RF front-end module chips, and shortening the debugging cycle.

[0115] This disclosure also provides an RF chip, which includes any of the power amplifier circuits described above.

[0116] In some embodiments, the radio frequency chip may further include at least one of the following: an antenna switch, a filter, a duplexer and a diplexer, a low-noise amplifier (LNA), etc.

[0117] This disclosure also provides an electronic device, which includes any of the power amplifier circuits described above, or the electronic device includes the radio frequency chip described above.

[0118] In some embodiments, the electronic device may be one of the following: a server, a mobile phone, a tablet computer, a computer with wireless transceiver capabilities, a handheld computer, a desktop computer, a personal digital assistant, a portable media player, a smart speaker, a navigation device, a smartwatch, smart glasses, a smart necklace and other wearable devices, a pedometer, a digital TV, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, a vehicle in a vehicle networking system, in-vehicle equipment, an in-vehicle module, etc.

[0119] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0120] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made under the concept of this disclosure using the contents of this specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A power amplifier circuit, characterized in that, The power amplifier circuit includes: At least two cascaded power amplifiers; A low-frequency resonant network includes a first capacitor, a second capacitor, and a first inductor; the first capacitor is coupled between a power supply terminal and a ground terminal; the second capacitor is coupled between a first terminal of the power amplifier and the ground terminal; the first inductor is coupled between the first capacitor and the second capacitor; the first capacitor includes a decoupling capacitor.

2. The power amplifier circuit according to claim 1, characterized in that, Also includes: The first gain reduction network includes a third capacitor, a second inductor, and a first resistor; the second inductor and the first resistor are connected in series between the RF input terminal and the second terminal of the first-stage power amplifier; the third capacitor is connected between the RF input terminal and the second terminal of the first-stage power amplifier.

3. The power amplifier circuit according to claim 2, characterized in that, The first degaussing network further includes: A first switch; the first switch is connected in series in the branch where the second inductor is located; the first switch controls the second inductor and the first resistor to be connected to the power amplifier circuit.

4. The power amplifier circuit according to claim 1, characterized in that, Also includes: The second gain reduction network includes a fourth capacitor, a third inductor, and a second resistor connected in series; the second gain reduction network is coupled between the ground terminal and the second terminal of the first-stage power amplifier.

5. The power amplifier circuit according to claim 4, characterized in that, The second gain reduction network also includes: The second switch is connected in series in the branch where the fourth capacitor is located; the second switch controls the fourth capacitor, the third inductor and the second resistor to be connected to the power amplifier circuit.

6. The power amplifier circuit according to claim 4, characterized in that, The second gain reduction network also includes: A fifth capacitor and a third switch; the fifth capacitor and the third switch are connected in series between the two ends of the fourth capacitor; the third switch controls the fifth capacitor to be connected to the power amplifier circuit.

7. The power amplifier circuit according to claim 1, characterized in that, Also includes: The third gain reduction network consists of multiple forward diodes connected in series and multiple reverse diodes connected in series. The plurality of series-connected forward diodes and the plurality of series-connected reverse diodes are connected in parallel between the second terminal of the second-stage power amplifier and the ground terminal.

8. The power amplifier circuit according to claim 7, characterized in that, The third gain reduction network also includes: The switch short-circuit network includes a fourth switch connected in parallel with any of the forward diodes and a fifth switch connected in parallel with any of the reverse diodes; the fourth switch controls the forward diodes to be connected to the power amplifier circuit; the fifth switch controls the reverse diodes to be connected to the power amplifier circuit.

9. The power amplifier circuit according to claim 1, characterized in that, Also includes: The first matching network includes a sixth capacitor and a fourth inductor; the sixth capacitor and the fourth inductor are connected in series between the first terminal of the second-stage power amplifier and the ground terminal.

10. The power amplifier circuit according to claim 1, characterized in that, Also includes: The second matching network includes a seventh capacitor and a fifth inductor; the seventh capacitor and the fifth inductor are connected in parallel between the first terminal and the RF output terminal of the second-stage power amplifier.

11. The power amplifier circuit according to claim 1, characterized in that, The first-stage power amplifier includes a driver-stage power amplifier and a final-stage power amplifier.

12. A radio frequency chip, characterized in that, The radio frequency chip includes the power amplifier circuit according to any one of claims 1 to 11.

13. An electronic device, characterized in that, The electronic device includes the power amplifier circuit according to any one of claims 1 to 11, or the electronic device includes the radio frequency chip according to claim 12.

Images