Program reset circuit, key panel and engineering machinery

Abstract

The application provides a program reset circuit, a key panel and a construction machine, and relates to the technical field of construction machines. The circuit comprises a reset key circuit, a logic processing circuit and a reset circuit. The reset key circuit comprises a first key circuit comprising a first reset key, a second key circuit comprising a second reset key and a third key circuit comprising a third reset key. The output ends of the first key circuit, the second key circuit and the third key circuit are respectively connected with the input end of the logic processing circuit. The output end of the logic processing circuit is connected with the input end of the reset circuit. The output end of the reset circuit is connected with an MCU. When the first reset key and the third reset key are pressed at the same time and the second reset key is not pressed, the logic processing circuit outputs a low-level signal to the reset circuit. When the MCU receives the low-level signal transmitted by the reset circuit, the reset operation is completed. The circuit does not need an external port and can improve the simplicity of program reset.

Description

Technical Field

[0001] This application relates to the field of engineering machinery technology, and in particular to a program reset circuit, a keypad, and engineering machinery. Background Technology

[0002] The program reset function is very important in the stages of finished product debugging, factory testing and actual use of button panel products.

[0003] In related technologies, for button panel products, a specific unused port is typically designated as a program reset port. When the application malfunctions, simply shorting this program reset port to ground for more than 3 seconds upon power-up will allow the microcontroller unit (MCU) to erase the application, which the operator can then re-download. However, button panel products typically have limited external ports, with no spare ports designated as program reset ports. Furthermore, when the application malfunctions, manual disassembly is required to short the program reset port to ground, a complex operation that wastes significant time, manpower, and resources.

[0004] Therefore, a program reset solution that does not require an external port and can improve the ease of program reset is needed. Utility Model Content

[0005] This application provides a program reset circuit, a keypad, and engineering machinery that do not require external ports and improve the ease of program reset.

[0006] In a first aspect, embodiments of this application provide a program reset circuit, including: a reset button circuit, a logic processing circuit, and a reset circuit;

[0007] The reset button circuit includes a first button circuit, a second button circuit, and a third button circuit. The first button circuit includes a first reset button, the second button circuit includes a second reset button, and the third button circuit includes a third reset button.

[0008] The output terminals of the first button circuit, the second button circuit, and the third button circuit are respectively connected to the input terminal of the logic processing circuit. The output terminal of the logic processing circuit is connected to the input terminal of the reset circuit. The output terminal of the reset circuit is connected to the microcontroller unit (MCU).

[0009] When the first reset button and the third reset button are pressed simultaneously, and the second reset button is not pressed, the logic processing circuit outputs a low-level signal to the reset circuit. The MCU completes the reset operation when it receives the low-level signal transmitted by the reset circuit.

[0010] In one possible implementation, the first button circuit further includes a first resistor, a second resistor, a first input terminal, a first output terminal, and a second output terminal;

[0011] The first output terminal is connected to the input terminal of the logic processing circuit, and the second output terminal is connected to the MCU;

[0012] The first input terminal is connected to the first output terminal through a first resistor, and the first input terminal is also connected to the second output terminal in sequence through a first resistor and a second resistor;

[0013] The first pin of the first reset button is connected to the first output terminal, the second pin is connected to the second resistor, and the third and fourth pins are grounded.

[0014] In one possible implementation, the second button circuit further includes a third resistor, a fourth resistor, a second input terminal, a third output terminal, and a fourth output terminal;

[0015] The third output terminal is connected to the input terminal of the logic processing circuit, and the fourth output terminal is connected to the MCU;

[0016] The second input terminal is connected to the third output terminal through a third resistor, and the second input terminal is also connected to the fourth output terminal in sequence through a third resistor and a fourth resistor;

[0017] The first pin of the second reset button is connected to the third output terminal, the second pin is connected to the fourth resistor, and the third and fourth pins are grounded.

[0018] In one possible implementation, the third button circuit further includes a fifth resistor, a sixth resistor, a third input terminal, a fifth output terminal, and a sixth output terminal;

[0019] The fifth output terminal is connected to the input terminal of the logic processing circuit, and the sixth output terminal is connected to the MCU;

[0020] The third input terminal is connected to the fifth output terminal through the fifth resistor, and the third input terminal is also connected to the sixth output terminal in sequence through the fifth resistor and the sixth resistor;

[0021] The first pin of the third reset button is connected to the fifth output terminal, the second pin is connected to the sixth resistor, and the third and fourth pins are grounded.

[0022] In one possible implementation, when the first reset button is disconnected, the electrical signal output by the power supply is transmitted to the first output terminal through the first resistor, and the first output terminal outputs a high-level signal.

[0023] When the second reset button is disconnected, the electrical signal output by the power supply is transmitted to the third output terminal through the third resistor, and the third output terminal outputs a high-level signal;

[0024] When the third reset button is disconnected, the electrical signal output by the power supply is transmitted to the fifth output terminal through the fifth resistor, and the fifth output terminal outputs a high-level signal.

[0025] When the first reset button is closed, the electrical signal output by the power supply is grounded through the first resistor and the first reset button, and the first output terminal outputs a low-level signal.

[0026] When the second reset button is closed, the electrical signal output by the power supply is grounded through the third resistor and the second reset button, and the third output terminal outputs a low-level signal.

[0027] When the third reset button is closed, the electrical signal output by the power supply is grounded through the fifth resistor and the third reset button, and the fifth output terminal outputs a low-level signal.

[0028] In one possible implementation, the logic processing circuit includes a first logic OR gate, a transistor, and a second logic OR gate;

[0029] One input terminal of the first logic OR gate is connected to the first output terminal, and the other input terminal is connected to the fifth output terminal. The output terminal of the first logic OR gate is connected to one input terminal of the second logic OR gate.

[0030] One input terminal of the transistor is connected to the third output terminal, the other input terminal is connected to the power supply, and the output terminal of the transistor is connected to the other input terminal of the second logic OR gate;

[0031] The output of the second logic OR gate is connected to the input of the reset circuit.

[0032] In one possible implementation, when either input of the first logic OR gate / second logic OR gate receives a high-level signal, the output outputs a low-level signal.

[0033] When the end of the transistor connected to the third output terminal receives a high-level signal, the output terminal outputs a low-level signal; when the end of the transistor connected to the third output terminal receives a low-level signal, the output terminal outputs a high-level signal.

[0034] In one possible implementation, the reset circuit includes a seventh resistor and an eighth resistor;

[0035] The output of the second logic OR gate is connected to the reset circuit detection pin of the MCU through the seventh resistor;

[0036] An eighth resistor is provided between the seventh resistor and the detection pin of the reset circuit, and the eighth resistor is connected to the power supply.

[0037] Secondly, embodiments of this application provide a button panel, including: a program reset circuit as described in any one of the first aspects.

[0038] Thirdly, embodiments of this application provide an engineering machinery, including: a button panel as described in the second aspect.

[0039] This application provides a program reset circuit, a keypad, and engineering machinery. The program reset circuit may include a reset button circuit, a logic processing circuit, and a reset circuit. The reset button circuit may include three parallel-connected first button circuit, second button circuit, and third button circuit. The first button circuit includes a first reset button, the second button circuit includes a second reset button, and the third button circuit includes a third reset button. The outputs of the first, second, and third button circuits are respectively connected to the inputs of the logic processing circuit. The output of the logic processing circuit is connected to the input of the reset circuit, and the output of the reset circuit is connected to the MCU. When the product application malfunctions, the operator can simultaneously press the first and third reset buttons without pressing the second reset button. The first, second, and third button circuits can output corresponding level signals according to the state of the reset buttons. After receiving the signals transmitted by the three button circuits, the logic processing circuit can output a low-level signal to the reset circuit. The reset circuit transmits the low-level signal to the MCU to pull down the MCU's reset acquisition signal. After detecting the low-level signal, the MCU automatically erases the program, completing the reset operation. With this setup, the button panel does not need to reserve an external port or disassemble the casing to achieve program reset. The operator only needs to press the first reset button and the third reset button at the same time, without pressing the second reset button, to send a program reset signal to the MCU, which improves the ease of program reset. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0041] Figure 1 This is a schematic diagram of the structure of a program reset circuit according to an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of the reset button circuit according to an embodiment of this application;

[0043] Figure 3 This is a schematic diagram of the logic processing circuit according to an embodiment of this application;

[0044] Figure 4 This is a schematic diagram of the structure of a reset circuit according to an embodiment of this application.

[0045] Reference numerals: 1. Reset button circuit; 11. First button circuit; 12. Second button circuit; 13. Third button circuit; 2. Logic processing circuit; 3. Reset circuit; S1. First reset button; S2. Second reset button; S3. Third reset button; R1. First resistor; R2. Second resistor; R3. Third resistor; R4. Fourth resistor; R5. Fifth resistor; R6. Sixth resistor; R13. Seventh resistor; R14. Eighth resistor; IN1. First input terminal; IN2. Second input terminal; IN3. Third input terminal; OUT1. First output terminal; OUT2. Second output terminal; OUT3. Third output terminal; OUT4. Fourth output terminal; OUT5. Fifth output terminal; OUT6. Sixth output terminal; Q1. First logic OR gate; Q2. Transistor; Q3. Second logic OR gate.

[0046] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0047] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0048] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0049] The program reset circuit, keypad, and construction machinery of this application can be used in the field of construction machinery, or in any field other than construction machinery, such as the field of program reset, etc. The application fields of the program reset circuit, keypad, and construction machinery of this application are not limited.

[0050] The program reset circuit, keypad, and construction machinery of this application can be applied to scenarios involving program reset of keypad products. There are no limitations on keypad products; for example, it can be a keypad used to control the operation of construction machinery, or other keypad products. As long as the scenario involves program reset of keypad products, the program reset circuit, keypad, and construction machinery of this application can be applied.

[0051] The program reset function is very important in the stages of finished product debugging, factory testing and actual use of button panel products.

[0052] In related technologies, for button panel products, a certain unused port is usually defined as a program reset port. When the application malfunctions, simply shorting this program reset port to ground for more than 3 seconds during power-on will erase the application, allowing the operator to re-download the application.

[0053] However, button panel products have few external ports and no spare ports are defined as program reset ports. Furthermore, when the application malfunctions, the casing must be manually removed to short-circuit the program reset port to ground for reset, which is complicated and wastes a lot of time, manpower and resources.

[0054] Based on the above-mentioned technical problems, the utility model concept of this application is: how to provide a program reset scheme that does not require an external port and can improve the ease of program reset.

[0055] This application provides a program reset circuit, a keypad, and engineering machinery. The program reset circuit may include a reset button circuit, a logic processing circuit, and a reset circuit. The reset button circuit may include three parallel-connected first button circuit, second button circuit, and third button circuit. The first button circuit includes a first reset button, the second button circuit includes a second reset button, and the third button circuit includes a third reset button. The outputs of the first, second, and third button circuits are respectively connected to the inputs of the logic processing circuit. The output of the logic processing circuit is connected to the input of the reset circuit, and the output of the reset circuit is connected to the MCU. When the product application malfunctions, the operator can simultaneously press the first and third reset buttons without pressing the second reset button. The first, second, and third button circuits can output corresponding level signals according to the state of the reset buttons. After receiving the signals transmitted by the three button circuits, the logic processing circuit can output a low-level signal to the reset circuit. The reset circuit transmits the low-level signal to the MCU to pull down the MCU's reset acquisition signal. After detecting the low-level signal, the MCU automatically erases the program, completing the reset operation. With this setup, the button panel does not need to reserve an external port or disassemble the casing to achieve program reset. The operator only needs to press the first reset button and the third reset button at the same time, without pressing the second reset button, to send a program reset signal to the MCU, which improves the ease of program reset.

[0056] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0057] Figure 1 This is a schematic diagram of the structure of a program reset circuit according to an embodiment of this application, as shown below. Figure 1 As shown, the program reset circuit may include: a reset button circuit 1, a logic processing circuit 2, and a reset circuit 3.

[0058] The reset button circuit 1 includes a first button circuit 11, a second button circuit 12, and a third button circuit 13. The first button circuit 11 includes a first reset button S1, the second button circuit 12 includes a second reset button S2, and the third button circuit 13 includes a third reset button S3.

[0059] The outputs of the first button circuit 11, the second button circuit 12, and the third button circuit 13 are respectively connected to the input of the logic processing circuit 2. The output of the logic processing circuit 2 is connected to the input of the reset circuit 3, and the output of the reset circuit 3 is connected to the MCU.

[0060] When the first reset button S1 and the third reset button S3 are pressed simultaneously and the second reset button S2 is not pressed, the logic processing circuit 2 outputs a low-level signal to the reset circuit 3. The MCU completes the reset operation when it receives the low-level signal transmitted by the reset circuit 3.

[0061] In this embodiment, the input terminals of the first button circuit 11, the second button circuit 12, and the third button circuit 13 can all be connected to the +3V3 power supply of the MCU to provide electrical signals for the button circuits.

[0062] In this embodiment, the specific positions of the first reset button S1, the second reset button S2, and the third reset button S3 on the button panel can be flexibly set by those skilled in the art according to actual needs, and no restrictions are imposed here. Preferably, in order to improve the convenience of operation, the first reset button S1 and the third reset button S3 can be selected as two adjacent buttons on the button panel. To avoid accidental operation, the position of the second reset button S2 can be relatively far from the first reset button S1 and the third reset button S3.

[0063] In this embodiment, the first button circuit 11, the second button circuit 12, and the third button circuit 13 can all output a low-level signal to the logic processing circuit 2 when the reset button is pressed, and output a high-level signal to the logic processing circuit 2 when the reset button is not pressed.

[0064] In this embodiment, the logic processing circuit 2 processes the level signals input from the first button circuit 11, the second button circuit 12, and the third button circuit 13. When it detects a combination state where the first reset button S1 and the third reset button S3 are pressed and the second reset button S2 is not pressed, it outputs a low-level signal to the reset circuit 3. If the logic processing circuit 2 detects that the reset button state does not conform to this combination state, it outputs a high-level signal to the reset circuit 3.

[0065] In this embodiment, the reset circuit 3 can transmit the high / low level signal transmitted by the logic processing circuit 2 to the reset circuit detection pin of the MCU. The reset circuit detection pin of the MCU is in a high level state by default. When the MCU detects the low level signal transmitted by the reset circuit 3 through the reset circuit detection pin, and the duration of the low level signal exceeds the duration threshold (e.g., 3s), the MCU automatically erases the program and completes the program reset operation.

[0066] In this embodiment, the program reset circuit may include a reset button circuit, a logic processing circuit, and a reset circuit. The reset button circuit may include three parallel circuits: a first button circuit, a second button circuit, and a third button circuit. The first button circuit includes a first reset button, the second button circuit includes a second reset button, and the third button circuit includes a third reset button. The outputs of the first, second, and third button circuits are respectively connected to the inputs of the logic processing circuit. The output of the logic processing circuit is connected to the input of the reset circuit, and the output of the reset circuit is connected to the MCU. When the product application malfunctions, the operator can simultaneously press the first and third reset buttons without pressing the second reset button. The first, second, and third button circuits can output corresponding level signals according to the state of the reset buttons. After receiving the signals transmitted by the three button circuits, the logic processing circuit can output a low-level signal to the reset circuit. The reset circuit transmits the low-level signal to the MCU to pull down the MCU's reset acquisition signal. After detecting the low-level signal, the MCU automatically erases the program, completing the reset operation. With this setup, the button panel does not need to reserve an external port or disassemble the casing to achieve program reset. The operator only needs to press the first reset button and the third reset button at the same time, without pressing the second reset button, to send a program reset signal to the MCU, which improves the ease of program reset.

[0067] In one possible implementation, Figure 2 This is a schematic diagram of the reset button circuit according to an embodiment of this application, as shown below. Figure 2 As shown, the first button circuit 11 may also include a first resistor R1, a second resistor R2, a first input terminal IN1, a first output terminal OUT1, and a second output terminal OUT2.

[0068] The first output terminal OUT1 is connected to the input terminal of the logic processing circuit 2, and the second output terminal OUT2 is connected to the MCU.

[0069] The first input terminal IN1 is connected to the first output terminal OUT1 through the first resistor R1. The first input terminal IN1 is also connected to the second output terminal OUT2 through the first resistor R1 and the second resistor R2 in sequence.

[0070] The first pin of the first reset button S1 is connected to the first output terminal OUT1, the second pin is connected to the second resistor R2, and the third and fourth pins are grounded.

[0071] In this embodiment, the first input terminal IN1 can also be connected to the 3V3 power supply of the MCU. The 3V3 power supply of the MCU can be the +3V3 power supply that powers the MCU. The first input terminal IN1 can be connected to this 3V3 power supply and receive a high-level signal.

[0072] In this embodiment, the second output terminal OUT2 can be connected to the MCU to collect the normal key signals during normal operation of the keypad.

[0073] In this embodiment, a first capacitor may also be provided between the second resistor R2 and the second output terminal OUT2, and the first capacitor may be grounded.

[0074] In this embodiment, the button signal can be transmitted to the first output terminal through the first resistor, and to the second output terminal through both the first and second resistors. This configuration allows for the determination of whether to reset without affecting the MCU's regular button signal acquisition. Furthermore, by connecting the first pin of the first reset button to the first output terminal, the second pin to the second resistor, and the third and fourth pins to ground, the circuit can output different level signals when the first reset button is pressed and not pressed.

[0075] In one possible implementation, such as Figure 2 As shown, the second button circuit 12 may also include a third resistor R3, a fourth resistor R4, a second input terminal IN2, a third output terminal OUT3, and a fourth output terminal OUT4.

[0076] The third output terminal OUT3 is connected to the input terminal of logic processing circuit 2, and the fourth output terminal OUT4 is connected to the MCU.

[0077] The second input terminal IN2 is also connected to the third output terminal OUT3 through the third resistor R3, and the second input terminal IN2 is also connected to the fourth output terminal OUT4 through the third resistor R3 and the fourth resistor R4 in sequence.

[0078] The first pin of the second reset button S2 is connected to the third output terminal OUT3, the second pin is connected to the fourth resistor R4, and the third and fourth pins are grounded.

[0079] In this embodiment, the second input terminal IN2 can also be connected to the 3V3 power supply of the MCU. The 3V3 power supply of the MCU can be the +3V3 power supply that powers the MCU. The second input terminal IN2 can be connected to this 3V3 power supply and receive a high-level signal.

[0080] In this embodiment, the fourth output terminal OUT4 can be connected to the MCU to collect the normal key signals during normal operation of the keypad.

[0081] In this embodiment, a second capacitor may also be provided between the fourth resistor R4 and the fourth output terminal OUT4, and the second capacitor may be grounded.

[0082] In this embodiment, the button signal can be transmitted to the third output terminal through the third resistor, and to the fourth output terminal through both the third and fourth resistors. This configuration allows for the determination of whether to reset without affecting the MCU's regular button signal acquisition. Furthermore, by connecting the first pin of the second reset button to the third output terminal, the second pin to the fourth resistor, and grounding the third and fourth pins, the circuit can output different level signals when the second reset button is pressed and not pressed.

[0083] In one possible implementation, such as Figure 2 As shown, the third button circuit 13 may also include a fifth resistor R5, a sixth resistor R6, a third input terminal IN3, a fifth output terminal OUT5, and a sixth output terminal OUT6.

[0084] The fifth output terminal OUT5 is connected to the input terminal of logic processing circuit 2, and the sixth output terminal OUT6 is connected to the MCU.

[0085] The third input terminal IN3 is also connected to the fifth output terminal OUT5 through the fifth resistor R5, and the third input terminal IN3 is also connected to the sixth output terminal OUT6 through the fifth resistor R5 and the sixth resistor R6 in sequence.

[0086] The first pin of the third reset button S3 is connected to the fifth output terminal OUT5, the second pin is connected to the sixth resistor R6, and the third and fourth pins are grounded.

[0087] In this embodiment, the third input terminal IN3 can also be connected to the 3V3 power supply of the MCU. The 3V3 power supply of the MCU can be the +3V3 power supply that powers the MCU. The third input terminal IN3 can be connected to this 3V3 power supply and receive a high-level signal.

[0088] In this embodiment, the sixth output terminal OUT6 can be connected to the MCU to collect the normal key signals during normal operation of the keypad.

[0089] In this embodiment, a third capacitor may also be provided between the sixth resistor R6 and the sixth output terminal OUT6, and this third capacitor may be grounded.

[0090] In this embodiment, the button signal can be transmitted to the fifth output terminal through the fifth resistor, and to the sixth output terminal through both the fifth and sixth resistors. This arrangement allows for the determination of whether to reset without affecting the MCU's regular button signal acquisition. Furthermore, by connecting the first pin of the third reset button to the fifth output terminal, the second pin to the sixth resistor, and grounding the third and fourth pins, the circuit can output different level signals when the third reset button is pressed and not pressed.

[0091] In one possible implementation, such as Figure 2 As shown, when the first reset button S1 is disconnected, the electrical signal output by the power supply is transmitted to the first output terminal OUT1 through the first resistor R1, and the first output terminal OUT1 outputs a high-level signal.

[0092] When the second reset button S2 is disconnected, the electrical signal output by the power supply is transmitted to the third output terminal OUT3 through the third resistor R3, and the third output terminal OUT3 outputs a high-level signal.

[0093] When the third reset button S3 is disconnected, the electrical signal output by the power supply is transmitted to the fifth output terminal OUT5 through the fifth resistor R5, and the fifth output terminal OUT5 outputs a high-level signal.

[0094] When the first reset button S1 is closed, the electrical signal output by the power supply is grounded through the first resistor R1 and the first reset button S1, and the first output terminal OUT1 outputs a low-level signal.

[0095] When the second reset button S2 is closed, the electrical signal output by the power supply is grounded through the third resistor R3 and the second reset button S2, and the third output terminal OUT3 outputs a low-level signal.

[0096] When the third reset button S3 is closed, the electrical signal output by the power supply is grounded through the fifth resistor R5 and the third reset button S3, and the fifth output terminal OUT5 outputs a low-level signal.

[0097] In this embodiment, the power supply can be a +3V3 power supply for the MCU.

[0098] In this embodiment, such as Figure 2 As shown, when the first reset button S1 is not pressed (open), the level signal of the 3V3 power supply input is transmitted to the first output terminal OUT1 through the first resistor R1. At this time, the first output terminal OUT1 outputs a high-level signal and can be set to 1. When the first reset button S1 is pressed (closed), the level signal of the 3V3 power supply input is grounded through the first resistor R1 and the first reset button S1. At this time, the first output terminal OUT1 outputs a low-level signal and can be set to 0.

[0099] In this embodiment, such as Figure 2 As shown, when the second reset button S2 is not pressed (open), the level signal of the 3V3 power supply input is transmitted to the third output terminal OUT3 through the third resistor R3. At this time, the third output terminal OUT3 outputs a high-level signal, which can be set to 1. When the second reset button S2 is pressed (closed), the level signal of the 3V3 power supply input is grounded through the third resistor R3 and the second reset button S2. At this time, the third output terminal OUT3 outputs a low-level signal, which can be set to 0.

[0100] In this embodiment, such as Figure 2 As shown, when the third reset button S3 is not pressed (open), the level signal of the 3V3 power supply input is transmitted to the fifth output terminal OUT5 through the fifth resistor R5. At this time, the fifth output terminal OUT5 outputs a high-level signal, which can be set to 1. When the third reset button S3 is pressed (closed), the level signal of the 3V3 power supply input is grounded through the fifth resistor R5 and the third reset button S3. At this time, the fifth output terminal OUT5 outputs a low-level signal, which can be set to 0.

[0101] In this embodiment, the first reset button, the second reset button, and the third reset button can all output different level signals when they are in two different states: pressed (closed) and not pressed (open).

[0102] In one possible implementation, Figure 3 This is a schematic diagram of the logic processing circuit according to an embodiment of this application, as shown below. Figure 3 As shown, the logic processing circuit 2 may include a first logic OR gate Q1, a transistor Q2, and a second logic OR gate Q3.

[0103] One input of the first logic OR gate Q1 is connected to the first output OUT1, and the other input is connected to the fifth output OUT5. The output of the first logic OR gate Q1 is connected to one input of the second logic OR gate Q3.

[0104] One input terminal of transistor Q2 is connected to the third output terminal OUT3, and the other input terminal is connected to the power supply. The output terminal of transistor Q2 is connected to the other input terminal of the second logic OR gate Q3.

[0105] The output of the second logic OR gate Q3 is connected to the input of the reset circuit 3.

[0106] In this embodiment, input terminal 1 of the first logic OR gate Q1 can be connected to the first output terminal OUT1 of the first button circuit to receive the level signal transmitted by the first output terminal OUT1; input terminal 2 can be connected to the fifth output terminal OUT5 of the third button circuit to receive the level signal transmitted by the fifth output terminal OUT5; input terminal 5 can be connected to the +3V3 power supply that powers the MCU.

[0107] In this embodiment, a resistor R7 can be provided between the input terminal 1 and the first output terminal OUT1 of the first logic OR gate Q1, and a resistor R8 can be provided between the input terminal 2 and the fifth output terminal OUT5.

[0108] In this embodiment, the output terminal 4 of the first logic OR gate Q1 can be connected to the input terminal 1 of the second logic OR gate Q3, and a resistor R9 can be provided between them; the output terminal 3 can be grounded.

[0109] In this embodiment, the input terminal 1 of transistor Q2 can be connected to the third output terminal OUT3 of the second button circuit to receive the level signal transmitted by the third output terminal OUT3, and control the switching on and off of transistor Q2 according to the level signal transmitted by the third output terminal OUT3; the input terminal 2 can be connected to the 3V3 power supply of the MCU.

[0110] In this embodiment, a resistor R10 can be provided between the input terminal 1 and the third output terminal OUT3 of transistor Q2.

[0111] In this embodiment, the output terminal 3 of transistor Q2 can be connected to the input terminal 2 of the second logic OR gate Q3, and a resistor R11 can be provided between them.

[0112] In this embodiment, a pull-down resistor R12 can be provided between the output terminal 3 of transistor Q2 and resistor R11. The pull-down resistor R12 is grounded, so that the output of transistor Q2 is low by default.

[0113] In this embodiment, the input terminal 5 of the second logic OR gate Q3 is connected to the 3V3 power supply of the MCU; the output terminal 3 is grounded; and the output terminal 4 is connected to the input terminal of the reset circuit 3.

[0114] In this embodiment, the first logic OR gate can control the level signal output to the second logic OR gate according to the level signals input by the first button circuit and the third button circuit. The transistor can control its on / off state according to the level signal input by the second button circuit, thereby controlling its output level signal to the second logic OR gate.

[0115] In one possible implementation, when either input of the first logic OR gate Q1 or the second logic OR gate Q3 receives a high-level signal, the output outputs a low-level signal.

[0116] When the end of transistor Q2 connected to the third output terminal OUT3 receives a high-level signal, the output terminal outputs a low-level signal; when the end of transistor Q2 connected to the third output terminal OUT3 receives a low-level signal, the output terminal outputs a high-level signal.

[0117] For example, Table 1 below is a truth table for each structure in the program reset circuit, as shown in Table 1:

[0118] Table 1

[0119]

[0120] In Table 1 above, the button status is the status within 3 seconds of the product being powered on. × represents the button not being pressed, ○ represents the button being pressed, 0 represents low level, and 1 represents high level.

[0121] In this embodiment, the first and second logic OR gates can be configured such that they output a high-level signal whenever either input is a high-level signal, and output a low-level signal only when both inputs are low-level signals. The transistor can be configured to invert the input and output, outputting a low-level signal when the input is a high-level signal and a high-level signal when the input is a low-level signal.

[0122] In one possible implementation, Figure 4 This is a schematic diagram of the structure of a reset circuit according to an embodiment of this application, as shown below. Figure 4 As shown, the reset circuit 3 may include a seventh resistor R13 and an eighth resistor R14.

[0123] The output of the second logic OR gate Q3 is connected to the reset circuit detection pin of the MCU through the seventh resistor R13.

[0124] An eighth resistor R14 is provided between the seventh resistor R13 and the reset circuit detection pin, and the eighth resistor R14 is connected to the power supply.

[0125] In this embodiment, the output terminal 4 of the second logic OR gate Q3 can be connected to the seventh resistor R13, and the seventh resistor R13 is connected to the detection pin of the reset circuit through resistor R15.

[0126] In this embodiment, an eighth resistor R14 is provided between the seventh resistor R13 and the resistor R15, and the eighth resistor R14 is connected to the +3V3 power supply that powers the MCU.

[0127] In this embodiment, the resistance value of the seventh resistor R13 is less than the resistance value of the eighth resistor R14, so that when the second logic OR gate Q3 transmits a low-level signal, the reset circuit detection pin is pulled low.

[0128] In this embodiment, a capacitor can also be provided between the eighth resistor R14 and the 3V3 power supply of the MCU, and the capacitor can also be connected to a point between the seventh resistor R13 and the resistor R15.

[0129] In this embodiment, the eighth resistor can be a pull-up resistor, which sets the reset circuit detection pin to a high level by default. The reset circuit detection pin will only go low after the second logic OR gate outputs a low-level signal, thus preventing MCU malfunction.

[0130] The application process of the program reset circuit of this application will be described below with a specific embodiment.

[0131] (a) such as Figures 1-4 As shown, the program reset circuit of a certain keypad panel includes: reset key circuit 1, logic processing circuit 2, and reset circuit 3.

[0132] The reset button circuit 1 includes a first button circuit 11, a second button circuit 12, and a third button circuit 13. The first button circuit 11 includes a first reset button S1, the second button circuit 12 includes a second reset button S2, and the third button circuit 13 includes a third reset button S3.

[0133] The outputs of the first button circuit 11, the second button circuit 12, and the third button circuit 13 are respectively connected to the input of the logic processing circuit 2. The output of the logic processing circuit 2 is connected to the input of the reset circuit 3, and the output of the reset circuit 3 is connected to the MCU.

[0134] When the first reset button S1 and the third reset button S3 are pressed simultaneously and the second reset button S2 is not pressed, the logic processing circuit 2 outputs a low-level signal to the reset circuit 3. The MCU completes the reset operation when it receives the low-level signal transmitted by the reset circuit 3.

[0135] The first button circuit 11 also includes a first resistor R1, a second resistor R2, a first input terminal IN1, a first output terminal OUT1, and a second output terminal OUT2.

[0136] The first output terminal OUT1 is connected to the input terminal of the logic processing circuit 2, and the second output terminal OUT2 is connected to the MCU.

[0137] The first input terminal IN1 is connected to the 3V3 power supply of the MCU. The first input terminal IN1 is also connected to the first output terminal OUT1 through the first resistor R1. The first input terminal IN1 is also connected to the second output terminal OUT2 through the first resistor R1 and the second resistor R2 in sequence.

[0138] The first pin of the first reset button S1 is connected to the first output terminal OUT1, the second pin is connected to the second resistor R2, and the third and fourth pins are grounded.

[0139] The second button circuit 12 also includes a third resistor R3, a fourth resistor R4, a second input terminal IN2, a third output terminal OUT3, and a fourth output terminal OUT4.

[0140] The third output terminal OUT3 is connected to the input terminal of logic processing circuit 2, and the fourth output terminal OUT4 is connected to the MCU.

[0141] The second input terminal IN2 is connected to the MCU's 3V3 power supply. The second input terminal IN2 is also connected to the third output terminal OUT3 through the third resistor R3. The second input terminal IN2 is also connected to the fourth output terminal OUT4 through the third resistor R3 and the fourth resistor R4 in sequence.

[0142] The first pin of the second reset button S2 is connected to the third output terminal OUT3, the second pin is connected to the fourth resistor R4, and the third and fourth pins are grounded.

[0143] The third button circuit 13 also includes a fifth resistor R5, a sixth resistor R6, a third input terminal IN3, a fifth output terminal OUT5, and a sixth output terminal OUT6.

[0144] The fifth output terminal OUT5 is connected to the input terminal of logic processing circuit 2, and the sixth output terminal OUT6 is connected to the MCU.

[0145] The third input terminal IN3 is connected to the MCU's 3V3 power supply. The third input terminal IN3 is also connected to the fifth output terminal OUT5 through the fifth resistor R5. The third input terminal IN3 is also connected to the sixth output terminal OUT6 through the fifth resistor R5 and the sixth resistor R6 in sequence.

[0146] The first pin of the third reset button S3 is connected to the fifth output terminal OUT5, the second pin is connected to the sixth resistor R6, and the third and fourth pins are grounded.

[0147] The logic processing circuit 2 includes a first logic OR gate Q1, a transistor Q2, and a second logic OR gate Q3.

[0148] One input of the first logic OR gate Q1 is connected to the first output OUT1, and the other input is connected to the fifth output OUT5. The output of the first logic OR gate Q1 is connected to one input of the second logic OR gate Q3.

[0149] One input terminal of transistor Q2 is connected to the third output terminal OUT3, and the other input terminal is connected to the 3V3 power supply of the MCU. The output terminal of transistor Q2 is connected to the other input terminal of the second logic OR gate Q3.

[0150] The output of the second logic OR gate Q3 is connected to the input of the reset circuit 3.

[0151] The reset circuit 3 includes a seventh resistor R13 and an eighth resistor R14.

[0152] The output of the second logic OR gate Q3 is connected to the reset circuit detection pin of the MCU through the seventh resistor R13.

[0153] An eighth resistor R14 is provided between the seventh resistor R13 and the reset circuit detection pin. The eighth resistor R14 is connected to the MCU's 3V3 power supply.

[0154] (II) Working principle of the program reset circuit of this button panel:

[0155] (1) When the first reset button S1 is open, the electrical signal output by the 3V3 power supply is transmitted to the first output terminal OUT1 through the first resistor R1, and the first output terminal OUT1 outputs a high-level signal; when the second reset button S2 is open, the electrical signal output by the 3V3 power supply is transmitted to the third output terminal OUT3 through the third resistor R3, and the third output terminal OUT3 outputs a high-level signal; when the third reset button S3 is open, the electrical signal output by the 3V3 power supply is transmitted to the fifth output terminal OUT5 through the fifth resistor R5, and the fifth output terminal OUT5 outputs a high-level signal.

[0156] (2) When the first reset button S1 is closed, the electrical signal output by the 3V3 power supply is grounded through the first resistor R1 and the first reset button S1, and the first output terminal OUT1 outputs a low-level signal; when the second reset button S2 is closed, the electrical signal output by the 3V3 power supply is grounded through the third resistor R3 and the second reset button S2, and the third output terminal OUT3 outputs a low-level signal; when the third reset button S3 is closed, the electrical signal output by the 3V3 power supply is grounded through the fifth resistor R5 and the third reset button S3, and the fifth output terminal OUT5 outputs a low-level signal.

[0157] (3) When either input of the first logic OR gate Q1 or the second logic OR gate Q3 receives a high-level signal, the output terminal outputs a low-level signal.

[0158] (4) When the end of transistor Q2 connected to the third output terminal OUT3 receives a high-level signal, the output terminal outputs a low-level signal; when the end of transistor Q2 connected to the third output terminal OUT3 receives a low-level signal, the output terminal outputs a high-level signal.

[0159] (5) When the button panel is powered on, if the specific combination of buttons (the first reset button S1 and the third reset button S3 are pressed and the second reset button S2 is not pressed) is not met, the output of the second logic OR gate Q3 is high, the reset circuit detection pin signal is high, and the MCU detects that the reset circuit detection pin signal is high. At this time, the MCU will not perform a reset operation, but will perform normal button signal acquisition to control the operation of the engineering machinery.

[0160] (6) When the button panel is powered on, if a specific combination of buttons is pressed (the first reset button S1 and the third reset button S3 are pressed, and the second reset button S2 is not pressed), the output of the second logic OR gate Q3 is low. At this time, the voltage of the reset circuit detection pin is 3.3V*R13 / (R14+R13). The voltage of the reset circuit detection pin is pulled down to below the MCU VIL voltage. At this time, the MCU detects that the reset circuit detection pin is low for more than 3 seconds, automatically erases the application program, and completes the reset operation.

[0161] One embodiment of this application also provides a button panel, which may include the program reset circuit of various embodiments of this application.

[0162] In this embodiment, the button panel does not require an external port or disassembly to achieve program reset. The operator only needs to press the first reset button and the third reset button simultaneously, without pressing the second reset button, to send a program reset signal to the MCU, which improves the ease of program reset.

[0163] One embodiment of this application also provides an engineering machine that may include the button panel of the embodiment of this application.

[0164] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0165] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the utility model disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the appended claims.

[0166] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A programmable reset circuit, characterized in that, include: Reset button circuit, logic processing circuit, and reset circuit; The reset button circuit includes a first button circuit, a second button circuit, and a third button circuit. The first button circuit includes a first reset button, the second button circuit includes a second reset button, and the third button circuit includes a third reset button. The output terminals of the first button circuit, the second button circuit, and the third button circuit are respectively connected to the input terminal of the logic processing circuit. The output terminal of the logic processing circuit is connected to the input terminal of the reset circuit. The output terminal of the reset circuit is connected to the microcontroller unit (MCU). When the first reset button and the third reset button are pressed simultaneously, and the second reset button is not pressed, the logic processing circuit outputs a low-level signal to the reset circuit. The MCU completes the reset operation when it receives the low-level signal transmitted by the reset circuit.

2. The program reset circuit according to claim 1, characterized in that, The first button circuit also includes a first resistor and a second resistor, a first input terminal, a first output terminal and a second output terminal; The first output terminal is connected to the input terminal of the logic processing circuit, and the second output terminal is connected to the MCU; The first input terminal is connected to the first output terminal through a first resistor, and the first input terminal is also connected to the second output terminal in sequence through a first resistor and a second resistor; The first pin of the first reset button is connected to the first output terminal, the second pin is connected to the second resistor, and the third and fourth pins are grounded.

3. The program reset circuit according to claim 2, characterized in that, The second button circuit also includes a third resistor, a fourth resistor, a second input terminal, a third output terminal, and a fourth output terminal; The third output terminal is connected to the input terminal of the logic processing circuit, and the fourth output terminal is connected to the MCU; The second input terminal is connected to the third output terminal through a third resistor, and the second input terminal is also connected to the fourth output terminal in sequence through a third resistor and a fourth resistor; The first pin of the second reset button is connected to the third output terminal, the second pin is connected to the fourth resistor, and the third and fourth pins are grounded.

4. The program reset circuit according to claim 3, characterized in that, The third button circuit also includes a fifth resistor, a sixth resistor, a third input terminal, a fifth output terminal, and a sixth output terminal; The fifth output terminal is connected to the input terminal of the logic processing circuit, and the sixth output terminal is connected to the MCU; The third input terminal is connected to the fifth output terminal through the fifth resistor, and the third input terminal is also connected to the sixth output terminal in sequence through the fifth resistor and the sixth resistor; The first pin of the third reset button is connected to the fifth output terminal, the second pin is connected to the sixth resistor, and the third and fourth pins are grounded.

5. The program reset circuit according to claim 4, characterized in that, When the first reset button is disconnected, the electrical signal output by the power supply is transmitted to the first output terminal through the first resistor, and the first output terminal outputs a high-level signal. When the second reset button is disconnected, the electrical signal output by the power supply is transmitted to the third output terminal through the third resistor, and the third output terminal outputs a high-level signal; When the third reset button is disconnected, the electrical signal output by the power supply is transmitted to the fifth output terminal through the fifth resistor, and the fifth output terminal outputs a high-level signal. When the first reset button is closed, the electrical signal output by the power supply is grounded through the first resistor and the first reset button, and the first output terminal outputs a low-level signal. When the second reset button is closed, the electrical signal output by the power supply is grounded through the third resistor and the second reset button, and the third output terminal outputs a low-level signal; When the third reset button is closed, the electrical signal output by the power supply is grounded through the fifth resistor and the third reset button, and the fifth output terminal outputs a low-level signal.

6. The program reset circuit according to claim 5, characterized in that, The logic processing circuit includes a first logic OR gate, a transistor, and a second logic OR gate; One input terminal of the first logic OR gate is connected to the first output terminal, and the other input terminal is connected to the fifth output terminal. The output terminal of the first logic OR gate is connected to one input terminal of the second logic OR gate. One input terminal of the transistor is connected to the third output terminal, the other input terminal is connected to the power supply, and the output terminal of the transistor is connected to the other input terminal of the second logic OR gate; The output of the second logic OR gate is connected to the input of the reset circuit.

7. The program reset circuit according to claim 6, characterized in that, When either input of the first OR gate or the second OR gate receives a high-level signal, the output gate outputs a low-level signal. When the end of the transistor connected to the third output terminal receives a high-level signal, the output terminal outputs a low-level signal; when the end of the transistor connected to the third output terminal receives a low-level signal, the output terminal outputs a high-level signal.

8. The program reset circuit according to claim 7, characterized in that, The reset circuit includes a seventh resistor and an eighth resistor; The output of the second logic OR gate is connected to the reset circuit detection pin of the MCU through the seventh resistor; An eighth resistor is provided between the seventh resistor and the detection pin of the reset circuit, and the eighth resistor is connected to the power supply.

9. A button panel, characterized in that, include: The program reset circuit as described in any one of claims 1-8.

10. An engineering machinery, characterized in that, include: The button panel as described in claim 9.

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