FPGA fault injection platform and device based on icap multiplexing and double-path injection

Abstract

The application discloses an FPGA fault injection platform and device based on ICAP multiplexing and double-path injection, which introduces a multiplexer MUX to dynamically switch the ICAP access control right between a SEM IP and a HWICAP IP, realizes resource sharing of an ICAP interface, and avoids repeatedly occupying key configuration port resources of the FPGA; the ICAP access has an atomicity requirement, through AXI control logic on a PS side, only one module is allowed to access the ICAP at the same time, and the data consistency of the injection operation and the system stability are ensured; the MUX structure allows more modules needing to access the ICAP to be added in the future, and improves the functional compatibility and secondary development space of the platform; a double-path injection mechanism is introduced based on a ZYNQ platform to perform classified injection test on two types of key registers in the FPGA; the double-path mechanism not only improves the injection granularity, but also ensures the comprehensiveness of the coverage range, meets different test requirements of the system level and the module level, and effectively overcomes the technical bottleneck that the injection precision is not high and uncontrollable in the traditional platform.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit reliability testing technology, specifically relating to an FPGA fault injection platform architecture and device based on ICAP multiplexing and dual-path injection. Background Technology

[0002] With the widespread application of integrated circuits in aerospace, military equipment, and high-reliability embedded systems, verifying the single-event upset (SEU) resistance of devices is becoming increasingly important. SRAM-based FPGAs, with their reconfigurability and flexibility, have broad application prospects in these fields. However, their configuration logic, based on volatile memory structures, is susceptible to SEU effects under high-irradiation environments, which may lead to functional abnormalities or even system crashes.

[0003] Therefore, the industry widely adopts fault injection technology for robust testing of FPGAs, especially injection platforms based on the ZYNQ architecture, which are becoming increasingly popular due to their ARM+FPGA heterogeneous characteristics. However, current platforms generally have the following shortcomings:

[0004] Inconsistent architectural design limits the accuracy and flexibility of injection.

[0005] The ICAP interface has low utilization efficiency, and SEM and HWICAP cannot work together efficiently.

[0006] The lack of modular design and system integration in embedded deployment platforms results in poor engineering practicality of test equipment.

[0007] Therefore, there is an urgent need for an SRAM-based FPGA fault injection platform architecture that features a dual-path injection mechanism, ICAP resource reuse capability, and highly integrated hardware implementation. Utility Model Content

[0008] In view of this, the purpose of this utility model is to provide an FPGA fault injection platform and device based on ICAP multiplexing and dual-path injection, which combines software architecture innovation and hardware platform integration to support fine-grained injection, automated management and visual deployment of FPGA configuration area and user logic area, thereby improving test efficiency, injection accuracy and system availability.

[0009] An FPGA fault injection platform, comprising:

[0010] The ZYNQ core board is based on the Linux system, on which the core logic of the entire fault injection test system runs and acts as the core processor to schedule the operation of the entire system. The PS end of the core board receives instructions from the host computer via Ethernet and controls various injection modules via the AXI bus.

[0011] SEM IP module: performs continuous batch injection of configuration registers based on linear frame addresses;

[0012] HWICAP IP module: Based on physical frame address operation, it performs single-point injection into user registers and can also reconfigure the PBlock region through this module;

[0013] The MUX module has two input ports identical to the ICAP multiplexing module, which are connected to the output ports of the SEM IP module and the HWICAP IP module, respectively; and a strobe input port, which selects the signal output to the ICAP multiplexing module based on the signal from the strobe input port.

[0014] The ICAP multiplexing module uses the MUX module to dynamically switch the outputs of the SEM IP module and the HWICAP IP module, connecting either the SEM IP module or the HWICAP IP module to the DUT under test.

[0015] The BRAM control module provides DUT excitation and DUT response to injected faults.

[0016] PBlock, a reconfigurable region, is used to deploy user-tested logic and supports dynamic reconfiguration.

[0017] Furthermore, it also includes:

[0018] The FT2232 module virtualizes a serial port device and a JTAG device, allowing users to monitor serial port data from the ZYNQ core board via a host computer and debug the ZYNQ chip by opening the JTAG device using the Vivado tool.

[0019] The UART module connects the PS's serial port to the peripheral hardware.

[0020] The JTAG module serves as the debugging interface for the entire FPGA, enabling debugging of the FPGA.

[0021] An apparatus based on the above-mentioned FPGA fault injection platform includes a DC power interface, a power self-locking switch, a level conversion unit, a Type-C USB interface, an RJ45 Ethernet interface, an SD card slot, and an LED control unit.

[0022] The power supply is connected to the device through a DC power interface. The power self-locking switch controls whether to supply power to the entire device. When the power self-locking switch is turned on, it will directly supply power to the cooling fan of the downstream stage, and after passing through the level conversion unit, it will supply power to the ZYNQ core board.

[0023] The Type-C USB interface allows you to insert a Type-C cable and connect to a host computer.

[0024] The RJ45 Ethernet interface allows the insertion of Ethernet cables;

[0025] The LED control unit receives GPIO signals from the ZYNQ core board and converts them into levels that can drive LEDs to control external LED indicators to display the current working status.

[0026] Insert an SD card containing the system firmware into the SD card slot to enable the ZYNQ chip to boot into a pre-designed Linux system.

[0027] This utility model has the following beneficial effects:

[0028] This invention proposes an ICAP multiplexing architecture that dynamically switches ICAP access control between SEM IP and HWICAP IP by introducing a multiplexer (MUX), thereby achieving resource sharing of the ICAP interface. This design has the following innovative advantages:

[0029] Resource conservation: In traditional architectures, SEM and HWICAP are often deployed independently and run mutually exclusively, resulting in resource waste. This invention avoids the repeated occupation of critical configuration port resources on the FPGA by using ICAP multiplexing;

[0030] Access conflict avoidance: ICAP access has atomicity requirements. This invention uses the AXI control logic on the PS side to allow only one module to access ICAP at a time, ensuring data consistency and system stability during injection operations.

[0031] Highly scalable: The MUX architecture allows for the addition of more modules that need to access ICAP in the future (such as the dynamic reconfiguration engine, configuration area monitoring module, etc.), improving the platform's functional compatibility and secondary development space.

[0032] This invention introduces a dual-path injection mechanism based on the ZYNQ platform to perform classified injection tests on two types of critical registers within the FPGA:

[0033] Configuration Register Injection Path (based on SEM IP): The SEM module's linear frame address mechanism is used to automatically traverse the FPGA configuration frame and perform SEU simulation injection on each configuration bit. This is suitable for evaluating the static fault tolerance and self-recovery mechanism of FPGA design.

[0034] User register injection path (based on HWICAP IP): The value of the user register is read through the HWICAP module, the value is bit-flipped and then written back, so as to achieve targeted perturbation of the user register in the DUT module.

[0035] This dual-path mechanism not only improves the injection granularity but also ensures comprehensive coverage, meeting the different testing needs of both system-level and module-level testing, and effectively overcoming the technical bottlenecks of low injection accuracy and uncontrollability in traditional platforms.

[0036] This utility model includes the development of a dedicated embedded testing device, integrating power management, debugging interface, communication link, status indication, and system startup functions, forming a complete hardware and software integrated platform. Its innovation lies in:

[0037] Flexible deployment: The equipment is small in size and compact in structure, supporting rapid deployment on test benches, ruggedized environments or unmanned systems, and adapting to various complex testing scenarios;

[0038] Operation visualization: The system's operating status, error status, and power-on status are reflected in real time through three-color LEDs, facilitating debugging and remote monitoring;

[0039] System Automation: Based on loading the Linux system and control program via Micro SD card, it supports automated system startup and unattended injection process, and has high engineering practicality.

[0040] Compared with traditional discrete injection test platforms based on development boards, this embedded device achieves significant improvements in structural integration, centralized communication, simplified operation, and remote friendliness. Attached Figure Description

[0041] Figure 1 A schematic diagram of the fault injection platform architecture of this utility model;

[0042] Figure 2 This is a schematic diagram of the embedded testing device of this utility model;

[0043] Figure 3 This is a schematic diagram of the fault injection process of this utility model. Detailed Implementation

[0044] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0045] Example 1:

[0046] This embodiment provides an FPGA fault injection platform based on ICAP multiplexing and dual-path injection, such as... Figure 1 As shown, the fault injection platform implements a platform architecture through the ZYNQ series core board. The PS terminal in the ZYNQ runs the core main control logic, communicates with the host computer through the RJ45 Ethernet interface, and controls multiple IP modules through AXI to achieve fault injection testing. The system architecture includes:

[0047] Host computer: Responsible for user interface, configuration distribution and result feedback;

[0048] ZYNQ PS: Internally based on a Linux system, it runs the core logic of the entire fault injection testing system and acts as the core processor to schedule the operation of the entire system. The PS receives instructions via Ethernet and controls various injection modules via the AXI bus;

[0049] The FT2232 module allows the FPGA to combine one UART serial port signal and one JTAG debug signal into a single USB signal for connection to a host computer. The host computer can then virtualize two independent devices, simplifying the communication links of the entire system.

[0050] UART module: This module connects the PS's serial port to the peripheral hardware.

[0051] JTAG module: Serves as the debugging interface for the entire FPGA, supporting debugging of the FPGA.

[0052] SEM IP Module: Based on linear frame addresses, this module performs continuous batch injection of configuration registers. It's an IP implemented in the FPGA PL section, converting control signals from AXI into operation signals for ICAP. It encapsulates the functionality that can be achieved using ICAP, making it easy for users to call. Its greatest value lies in the concept of "linear frame addresses" defined by the SEM IP manufacturer. These frame addresses map the addresses of all configuration registers on the entire FPGA into a contiguous address space. This eliminates the risk of invalid injection due to operating on illegal addresses, thus greatly simplifying fault injection operations.

[0053] HWICAP IP Module: Based on physical frame address operation, it performs single-point precise injection into user registers and can also reconfigure the PBlock region. This module is an IP implemented in the FPGA PL section. It also converts control signals from AXI into operating signals for ICAP. Unlike the SEM IP, it still uses the concept of physical frame address, but its advantage lies in providing flexible supporting software APIs, allowing users to use ICAP without directly operating the ICAP port, simplifying the interaction logic.

[0054] BRAM_CTRL Control Module: Provides clock / reset / excitation for the DUT module and acquires response output; this module, as a custom IP, implements control logic in the PL through BRAM, which allows the PS to provide clock, reset, and input signals to the DUT via the AXI bus, and allows the DUT's output signals to be checked at any time.

[0055] MUX Module: This module has two input ports that are basically the same as ICAP, which are connected to the output ports of the SEM IP module and the HWICAP IP module respectively; the MUX module also has a dedicated gating input port, which can freely select the signal output to the ICAP multiplexing module according to the signal of the gating input port.

[0056] ICAP Multiplexing Module: The MUX module enables dynamic switching between the SEM IP module and the HWICAP IP module on the output of the ICAP multiplexing module; this module is an interface in the FPGA used to implement dynamic reconfiguration, and there is only one ICAP interface in the entire FPGA.

[0057] DUT: User-defined logic under test. This part of the logic is implemented in a fixed area in the FPGA and is isolated from other modules to avoid conflicts between the logic under test and the logic of the system framework, thus ensuring the isolation of the test.

[0058] Reconfigurable region (PBlock): Used to deploy user-tested logic, supporting dynamic reconfiguration.

[0059] This platform employs a dual-path injection mechanism: the SEM path supports traversal and enumeration injection of configuration registers via linear frame addresses, while the HWICAP path supports precise positioning injection of user registers via physical frame addresses. This invention utilizes an ICAP reuse strategy to simultaneously implement two fault injection testing methods within a single fault injection platform, improving resource utilization and platform versatility. (An FPGA typically has only one ICAP interface, and both SEM and HWICAP rely on ICAP to function. Generally, a fault injection test platform can only use one of these two methods. However, this invention innovatively shares the ICAP between SEM and HWICAP through a single MUX, allowing a fault injection test platform to simultaneously support both testing methods.)

[0060] Example 2:

[0061] To facilitate the efficient operation of the aforementioned architecture, this invention also includes a dedicated embedded testing device, such as... Figure 2 As shown, the fault injection test equipment includes a round hole DC power interface (for power supply), a Type-C USB interface (connects to the FT2232HL chip, providing serial port (UART) and JTAG debugging interface), and an RJ45 Ethernet interface (directly connected to the ZYNQ PS-end network controller to realize command issuance and data upload), integrating all the interfaces required for the entire fault injection test equipment to interact with the outside world.

[0062] It also includes a power module, which receives an external DC voltage input and controls the main power supply via a self-locking switch; a voltage branch power supply for the fan and a level conversion module, the latter supplying power to the ZYNQ core board; and ZYNQ core board GPIO controls three LED indicators: power-on, running, and fault status indicators. A Micro SD card is used to store the Linux system and file system, supporting plug-and-play and flexible updates. The system automatically loads and boots from the SD card upon power-up, entering the running state. This test equipment is compact, has standard interfaces, is easy to deploy, supports unattended operation, possesses excellent integration and engineering adaptability, and provides a clear overview of all statuses, facilitating on-site debugging and remote monitoring.

[0063] The power supply is connected to the device through a DC power interface. The power supply self-locking switch controls whether the device is powered. When the power supply self-locking switch is turned on, it will directly power the cooling fan of the downstream stage, and after passing through the level conversion unit, it will power the ZYNQ core board and other electronic components on the circuit board (such as the FT2232HL related circuit, LED control unit related circuit, etc.).

[0064] The Type-C USB interface allows you to insert a Type-C cable and connect to a host computer.

[0065] The FT2232HL has the relevant firmware burned into it, which can virtualize a serial port device and a JTAG device in the host computer. This allows users to monitor serial port data from the ZYNQ core board through the host computer and debug the ZYNQ chip by opening the JTAG device through the Vivado tool.

[0066] The RJ45 Ethernet interface allows the insertion of an Ethernet cable and direct connection to a host computer or a switch on the same network segment as the host computer. After the host computer's network is configured, the device can be detected by scanning the PING command on the host computer and can be connected to and debugged by using the SSH command.

[0067] The LED control unit receives GPIO signals from the ZYNQ core board and converts them into levels that can drive LEDs, thereby controlling external LED indicators to display the current operating status.

[0068] An SD card containing the system firmware is inserted into the SD card slot to enable the ZYNQ chip to boot into a pre-designed Linux system, which contains applications related to the fault injection platform.

[0069] Example 3:

[0070] The system's workflow is as follows Figure 3 As shown, the steps for fault injection are as follows:

[0071] 1) The user first specifies the parameters and generates the relevant files required for the test in the accompanying software in the host computer, and sends them to the ZYNQ PS via Ethernet in the software, and at the same time transmits the task-related parameters to the ZYNQ PS via Ethernet.

[0072] 2) After receiving the file and task parameters, ZYNQ PS first extracts the typical values ​​for the current test, specifically including:

[0073] The processing system PS deploys the DUT to the PBlock area;

[0074] The processing system PS resets the DUT;

[0075] The processing system PS provides a clock for the DUT;

[0076] Processing system PS captures DUT output;

[0077] The processing system PS records typical output values ​​of the DUT.

[0078] 3) The ZYNQ PS iterates through all registers under test in the test list from the host computer and performs fault injection on each register individually. The general process of fault injection is as follows:

[0079] By reconfiguring the PBlock region using HWICAP, the bitstream information from the host computer file is configured into the PBlock, thereby achieving the effect of deploying the DUT to the PBlock.

[0080] The DUT is reset by the BRAM controller, allowing it to enter its initial state.

[0081] The clock is started by the BRAM controller, providing a clock for the DUT cycle by cycle.

[0082] Based on the current register type, activate the corresponding fault injection IP to perform fault injection on the register, specifically including:

[0083] The SEM module iterates through and enumerates the configuration registers using linear frame addresses;

[0084] The HWICAP module precisely locates and injects user registers using physical frame addresses;

[0085] 4) Capture the DUT output through the BRAM controller and compare it with the typical value. Record the data where the output value is inconsistent with the typical value to the log (mainly including the number of cycles of fault injection, the number of cycles when the fault occurred, and the output value after the fault).

[0086] 5) Once all user-specified registers have been tested, the system will set its status flag to "completed". After the host computer recognizes this status, it will actively download the test logs back to the host computer via the RJ45 interface for subsequent log analysis.

[0087] The following is an explanation of the technical terms involved in this utility model:

[0088] DUT: Design Under Test. It refers to the target under test for fault injection testing. It is generally an FPGA design written in RTL language. During testing, it needs to be implemented in a specific area of ​​the FPGA to bring it into a normal working state, and then faults are injected into it so that the working state of the FPGA design when a fault occurs can be observed.

[0089] PBlock: A concept in Xilinx Vivado tools, referring to a rectangular area that allows users to draw on an FPGA chip to implement specific logic. In this patent, a PBlock is drawn specifically to house the DUT (Device Under Test), while other logic in the platform (such as SEM IP, HWICAP IP, etc.) is placed outside this PBlock. This is done to prevent accidental fault injection into the platform logic during fault injection, which could lead to the collapse of the entire system.

[0090] Implementation: A concept in Xilinx Vivado tools, it refers to implementing the user's FPGA design (usually logic expressed in a design language) into the FPGA chip so that the logic written by the user can actually run.

[0091] Reconfiguration: A concept in FPGA chip operation, referring to the reprogramming of some logic into new logic during FPGA operation. In this patent, reconfiguration is used to reprogram the DUT in the PBlock area while the fault injection-related framework logic is still running. This allows the DUT, which may have an erroneous operating state, to be restored to a normal operating state after a fault injection test of a register is completed, so that the next register can be tested.

[0092] ZYNQ: ZYNQ chips are a type of FPGA chip with a built-in ARM processor. The ARM processor portion is called the PS (Processing System), and the FPGA logic portion is called the PL (Programmable Logic). Compared to traditional FPGAs that only contain programmable logic, the core advantage of ZYNQ is that it integrates the PS (general-purpose processor) and PL (programmable logic) on the same chip, supporting collaborative computing between the PS and PL using the high-bandwidth AXI bus.

[0093] Configuration Registers (Cnfg Reg): Configuration registers are register units used to control the FPGA hardware structure. They are primarily loaded during the FPGA configuration (bitstream programming) phase and remain static throughout the entire runtime. The values ​​of these registers determine the behavior of the following resources:

[0094] LUT (Lookup Table) configuration (LUT Cnfg): Defines the logical functions for each LUT;

[0095] Flip-flop / register connection configuration (CLB Cnfg): Determines the connection method between the LUT and the register;

[0096] Routing selection and interconnect control: Determines how signals are routed within the FPGA.

[0097] These configuration registers correspond to configuration frames within the FPGA, which are loaded during configuration by ICAP, JTAG, or the master control PS unit via a dedicated configuration interface. Once loaded, their values ​​remain unchanged under normal operating conditions and can only be modified through a reconfiguration operation. This static nature makes configuration registers a crucial target for fault injection, as their stability determines the correctness of the FPGA structure.

[0098] User registers are read-write registers defined by the designer at the RTL level. They typically take the form of sequential logic elements such as flip-flops, state machine registers, and counters, corresponding to FF (Flip-Flop) resources in the FPGA layout. The values ​​of these registers are clock-controlled during system operation and may change on every clock edge, reflecting the dynamic behavior of the user logic.

[0099] The contents of user registers, controlled by circuit inputs, status feedback, or combinational logic, are mapped to specific flip-flop resources in the FPGA during the design, synthesis, and implementation phases. The correctness of their values ​​directly affects the functional behavior of the DUT (Device Under Test), and therefore is an important observation point and analysis target during fault injection.

[0100] In summary, the above are merely preferred embodiments of this utility model and are not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. An FPGA fault injection platform, characterized in that, include: The ZYNQ core board is based on the Linux system, on which the core logic of the entire fault injection test system runs and acts as the core processor to schedule the operation of the entire system. The PS end of the core board receives instructions from the host computer via Ethernet and controls various injection modules via the AXI bus. SEM IP module: performs continuous batch injection of configuration registers based on linear frame addresses; HWICAP IP module: Based on physical frame address operation, it performs single-point injection into user registers and can also reconfigure the PBlock region through this module; The MUX module has two input ports identical to the ICAP multiplexing module, which are connected to the output ports of the SEM IP module and the HWICAP IP module respectively; and a strobe input port, which selects the signal output to the ICAP multiplexing module based on the signal of the strobe input port. The ICAP multiplexing module uses the MUX module to dynamically switch the outputs of the SEM IP module and the HWICAP IP module, connecting either the SEM IP module or the HWICAP IP module to the DUT under test. The BRAM control module provides DUT excitation and DUT response to injected faults. PBlock, a reconfigurable region, is used to deploy user-tested logic and supports dynamic reconfiguration.

2. The FPGA fault injection platform as described in claim 1, characterized in that, Also includes: The FT2232 module virtualizes a serial port device and a JTAG device, allowing users to monitor serial port data from the ZYNQ core board via a host computer and debug the ZYNQ chip by opening the JTAG device using the Vivado tool. The UART module connects the PS's serial port to the peripheral hardware. The JTAG module serves as the debugging interface for the entire FPGA, enabling debugging of the FPGA.

3. An apparatus based on the FPGA fault injection platform of claim 1 or 2, characterized in that, It includes a DC power interface, a power self-locking switch, a level conversion unit, a Type-C USB interface, an RJ45 Ethernet interface, an SD card slot, and an LED control unit; The power supply is connected to the device through a DC power interface. The power self-locking switch controls whether to supply power to the entire device. When the power self-locking switch is turned on, it will directly supply power to the cooling fan of the downstream stage, and after passing through the level conversion unit, it will supply power to the ZYNQ core board. The Type-C USB interface allows you to insert a Type-C cable and connect to a host computer. The RJ45 Ethernet interface allows the insertion of Ethernet cables; The LED control unit receives GPIO signals from the ZYNQ core board and converts them into levels that can drive LEDs to control external LED indicators to display the current working status. Insert an SD card containing the system firmware into the SD card slot to enable the ZYNQ chip to boot into a pre-designed Linux system.

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