Vacuum transistor, array substrate and electronic device

Abstract

Embodiments of the present disclosure provide a vacuum transistor, an array substrate and an electronic device, and relate to the technical field of vacuum electronics, and are used for improving the control of the gate on the vacuum tunneling current and improving the on-off ratio of the vacuum transistor. The vacuum transistor comprises a substrate, a first electrode, a gate, a second electrode and a via hole. The first electrode, the gate and the second electrode are sequentially stacked on the substrate along a first direction and a direction gradually away from the substrate, and the first direction is the thickness direction of the substrate. The first electrode and the gate, and the gate and the second electrode are both spaced apart along the first direction. The via hole penetrates the second electrode and the film layer between the second electrode and the first electrode along the first direction, and exposes the side surface of the first electrode away from the substrate. The orthogonal projection of the gate on the substrate and the orthogonal projection of the second electrode on the substrate overlap.

Description

Technical Field

[0001] This disclosure relates to the field of vacuum electronics technology, and in particular to a vacuum transistor, an array substrate, and an electronic device. Background Technology

[0002] Traditional vacuum electronic devices have long dominated fields such as communications and radar due to their high power, wide bandwidth, and high frequency characteristics. However, their complex machining, large size, and difficulty in integration have limited their application in modern electronic systems. For example, the cathode emission structure of a traditional vacuum tube requires precision mechanical assembly, and the device size is limited by the electron beam transmission path, resulting in a bulky system.

[0003] With breakthroughs in semiconductor technology, solid-state devices (such as transistors) have achieved high integration through micro- and nano-manufacturing processes, but they still have limitations in high-frequency performance, power capacity, and radiation resistance. The emergence of vacuum electronic transistors aims to combine the high-frequency advantages of vacuum devices with the integration potential of solid-state devices, breaking through the physical size limitations of traditional vacuum tubes.

[0004] However, after decades of development, solid-state semiconductor devices are gradually approaching their physical limits. Moore's Law has failed, and the manufacturing cost of these devices has increased significantly, while performance remains unimproved due to amplified electron transport losses within semiconductor materials. To address this issue, traditional vacuum electronics has re-emerged as a research focus. Nanoscale vacuum channel electronic transistors (NVETs), with their excellent electron transport characteristics, are considered a potential alternative to traditional semiconductor devices. Utility Model Content

[0005] The purpose of this disclosure is to provide a vacuum transistor, an array substrate, and an electronic device for improving the gate's control over vacuum tunneling current and increasing the switching ratio of the vacuum transistor.

[0006] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0007] On one hand, a vacuum transistor is provided. The vacuum transistor includes a substrate, a first electrode, a gate electrode, a second electrode, and a via: the first electrode, the gate electrode, and the second electrode are sequentially stacked on the substrate along a first direction that gradually moves away from the substrate, the first direction being the thickness direction of the substrate; there is a gap between the first electrode and the gate electrode, and between the gate electrode and the second electrode, along the first direction; the via penetrates the second electrode along the first direction, and through a film layer between the second electrode and the first electrode, exposing the side surface of the first electrode facing away from the substrate; wherein the orthographic projection of the gate electrode onto the substrate overlaps with the orthographic projection of the second electrode onto the substrate.

[0008] The above-mentioned configuration allows the orthogonal projection of the gate onto the substrate to overlap with the orthogonal projection of the second electrode onto the substrate 1. In other words, the orthogonal projection of the gate onto the substrate can be located within the orthogonal projection of the second electrode onto the substrate, or the orthogonal projection of the gate onto the substrate can be partially located within the orthogonal projection of the second electrode onto the substrate. That is, by adjusting the position of the gate, the control force of the gate on the electrons emitted by the first electrode can be changed, thereby improving the switching ratio of the vacuum transistor.

[0009] Since the first electrode, second electrode, and gate of a vacuum transistor are all disposed in different layers and spaced apart from each other, the first electrode, second electrode, and gate of the vacuum transistor can be fabricated in different film layers. This allows it to be manufactured using equipment for fabricating array substrates in large-area semiconductor processes (i.e., processes for manufacturing display panels), instead of requiring equipment for wafer-level semiconductor processes (i.e., processes for manufacturing chips) as in related technologies. This reduces the manufacturing cost and application range of vacuum transistors, improves the performance of display panels, and facilitates the integration of vacuum transistors into display panels.

[0010] In some embodiments, the device further includes: a dielectric layer disposed between the first electrode and the second electrode; the via penetrating the dielectric layer, at least a portion of the gate being embedded in the dielectric layer, and a portion of the dielectric layer being located between the first electrode and the gate, and another portion of the dielectric layer being located between the gate and the second electrode.

[0011] In some embodiments, the gate is disposed around the via.

[0012] In some embodiments, the surface of the gate facing the via is flush with the surface of the dielectric layer facing the via.

[0013] In some embodiments, the surface of the gate facing the via protrudes beyond the surface of the dielectric layer facing the via.

[0014] In some embodiments, the gate is wrapped by the dielectric layer, and there is a gap between the surface of the gate facing the via and the surface of the dielectric layer facing the via.

[0015] In some embodiments, the dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is located between the gate and the first electrode, and the second dielectric layer is located between the gate and the second electrode.

[0016] In some embodiments, the gate has a plurality of openings extending through itself along the first direction, at least one of the openings communicating with the via, and a portion of the gate is located within the via.

[0017] In some embodiments, the gate includes a first portion and a second portion; the first portion is disposed around the via; the second portion is located in the via and connected to the first portion to form the plurality of openings.

[0018] In some embodiments, the second portion of the gate covers the orthogonal projection onto the substrate, and the portion of the first electrode located within the via projects the orthogonal projection onto the substrate.

[0019] In some embodiments, the number of gates is multiple, and the multiple gates are spaced apart along the first direction.

[0020] In some embodiments, the plurality of gates includes a first gate and a second gate; the first gate has a plurality of openings extending through itself along the first direction, at least one of the openings communicating with the via, and a portion of the second gate is located within the via; the second gate is disposed around the via; the second gate is further away from the substrate than the first gate.

[0021] On the other hand, an array substrate is provided, comprising: a vacuum transistor as described in any of the above embodiments.

[0022] The array substrate described above has the same structure and beneficial technical effects as the vacuum transistors provided in some of the above embodiments, and will not be described again here.

[0023] In some embodiments, the vacuum transistor includes a first gate and a second gate spaced apart along the first direction, the second gate being further away from the substrate than the first gate; the array substrate further includes a first resistor and a second resistor, a first end of the first resistor being connected to the first gate, a first end of the second resistor being connected to the second gate, the resistance of the first resistor being greater than the resistance of the second resistor; the second ends of the first resistor and the second resistor are both configured to be connected to the same power supply.

[0024] In another aspect, an electronic device is provided, comprising: an array substrate as described in any of the above embodiments.

[0025] The above-described electronic device has the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be considered as schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of this disclosure.

[0027] Figure 1 This is a planar structural diagram of a vacuum transistor according to some embodiments of the present disclosure;

[0028] Figure 2 This is a cross-sectional structural diagram of a vacuum transistor according to some embodiments of the present disclosure;

[0029] Figure 3 This is another cross-sectional view of a vacuum transistor according to some embodiments of the present disclosure;

[0030] Figure 4 This is yet another cross-sectional view of a vacuum transistor according to some embodiments of the present disclosure;

[0031] Figure 5 This is another cross-sectional view of a vacuum transistor according to some embodiments of the present disclosure;

[0032] Figure 6 This is a planar structural diagram of the gate of a vacuum transistor according to some embodiments of the present disclosure;

[0033] Figure 7 This is yet another cross-sectional view of a vacuum transistor according to some embodiments of the present disclosure;

[0034] Figure 8 This is another cross-sectional view of a vacuum transistor according to some embodiments of the present disclosure;

[0035] Figure 9 This is yet another cross-sectional view of a vacuum transistor according to some embodiments of the present disclosure;

[0036] Figure 10 This is a flowchart of a method for fabricating a vacuum transistor according to some embodiments of the present disclosure;

[0037] Figure 11 This is another flowchart illustrating the steps of a method for fabricating a vacuum transistor according to some embodiments of the present disclosure;

[0038] Figure 12 This is a process structure diagram of a method for fabricating a vacuum transistor according to some embodiments of the present disclosure;

[0039] Figure 13 This is another process structure diagram of a method for fabricating a vacuum transistor according to some embodiments of the present disclosure;

[0040] Figure 14 This is another process structure diagram of a method for fabricating a vacuum transistor according to some embodiments of the present disclosure;

[0041] Figure 15 This is a structural diagram illustrating another process of fabricating a vacuum transistor according to some embodiments of the present disclosure.

[0042] Figure 16 This is another process structure diagram of a method for fabricating a vacuum transistor according to some embodiments of the present disclosure;

[0043] Figure 17 This is a plan view of an electronic device according to some embodiments of the present disclosure. Detailed Implementation

[0044] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0046] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0047] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0048] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", and includes the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0049] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0050] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when…” or “in the event of…” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrase “if determination…” or “if detection [the stated condition or event]” may optionally be interpreted as meaning “in the event of determination…” or “in response to determination…” or “in response to detection [the stated condition or event]” or “in response to detection [the stated condition or event].”

[0051] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0052] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0053] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0054] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0055] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0056] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0057] Some embodiments of this disclosure provide vacuum transistors, array substrates, and electronic devices that can be used to improve the gate's control over vacuum tunneling current and increase the on / off ratio of the vacuum transistor, i.e., the ratio of the current in the vacuum transistor in the on and off states.

[0058] For ease of description below, an XYZ coordinate system is established. The first direction Z is perpendicular to the substrate, i.e., the thickness direction in this application. The XY plane is perpendicular to the Z direction, and the second direction X intersects the third direction Y. For example, the second direction X and the third direction Y are perpendicular to each other.

[0059] It should be noted that, for example, 61 / 6 in the accompanying drawings of some embodiments of this disclosure indicates that component 61 belongs to component 6, and other similar reference numerals in the drawings also follow the above description.

[0060] The following sections will describe the vacuum transistor, array substrate, and electronic device provided in this disclosure.

[0061] Some embodiments of this disclosure provide a vacuum transistor 10, such as Figure 1 As shown, the vacuum transistor 10 includes a substrate 1, a first electrode 2, a gate 3, a second electrode 4, and a via 5. The first electrode 2, the gate 3, and the second electrode 4 are sequentially stacked on the substrate 1 along a first direction Z that gradually moves away from the substrate 1. The first direction Z is the thickness direction of the substrate 1. There is a gap between the first electrode 2 and the gate 3, and between the gate 3 and the second electrode 4, along the first direction Z. The via 5 penetrates the second electrode 5 along the first direction Z, as well as the film layer between the second electrode 5 and the first electrode 2, and exposes the side surface of the first electrode 2 facing away from the substrate 1. The orthographic projection of the gate 3 onto the substrate 1 overlaps with the orthographic projection of the second electrode 4 onto the substrate 1.

[0062] For example, such as Figure 1As shown, the substrate 1 can be made of a highly insulating material, such as glass, quartz, sapphire, or low-resistivity silicon. The first electrode 2 can be made of a metal or semiconductor material that readily generates field emission electrons, such as tungsten, molybdenum, gold, platinum, graphene, gallium nitride (GaN), gallium arsenide (GaAs), gallium oxide (GaO), silicon carbide (SiC), single-crystal silicon, or low-temperature polycrystalline silicon. The gate 3 and the second electrode 4 can be made of metallic materials, such as gold, copper, molybdenum, or aluminum.

[0063] Continue to refer to Figure 1 , Figure 1 The diagram shows at least three pads: a first pad S, a second pad D, and a third pad G. These pads are connected to the first electrode 2, the second electrode 4, and the gate 3 via leads. Exemplarily, the first electrode 2 is the emitter, and the second electrode 4 is the collector. By using a metal or semiconductor material that readily generates field emission electrons, the minimum potential barrier for electron escape from the first electrode 2 is lowered. After the third pad G applies a voltage to the gate 3, electrons in the first electrode 2 can escape more easily, and the escaped electrons quickly reach the second electrode 4 through the via 5.

[0064] It should be noted that metals that are more likely to generate field emission electrons refer to low work function metals with a work function less than or equal to the preset work function; semiconductor materials that are more likely to generate field emission electrons refer to semiconductor materials with a work function greater than or equal to the preset work function.

[0065] The above-mentioned configuration allows the orthogonal projection of the gate 3 onto the substrate 1 to overlap with the orthogonal projection of the second electrode 4 onto the substrate 1. In other words, the orthogonal projection of the gate 3 onto the substrate 1 can be located within the orthogonal projection of the second electrode 4 onto the substrate 1, or the orthogonal projection of the gate 3 onto the substrate 1 can be partially located within the orthogonal projection of the second electrode 4 onto the substrate 1. That is, by adjusting the position of the gate 3, the control force of the gate 3 on the electrons emitted by the first electrode 2 can be changed, thereby improving the switching ratio of the vacuum transistor.

[0066] Since the first electrode 2, the second electrode 4, and the gate 3 in the vacuum transistor are all disposed in different layers and spaced apart from each other, the first electrode 2, the second electrode 4, and the gate 3 in the vacuum transistor can be fabricated in different film layers. This allows them to be manufactured using equipment for fabricating array substrates in large-area semiconductor processes (i.e., processes for fabricating display panels), instead of using equipment for wafer-level semiconductor processes (i.e., processes for fabricating chips) as required in related technologies. This reduces the manufacturing cost and application range of vacuum transistors, improves the performance of display panels, and facilitates the integration of vacuum transistors into display panels.

[0067] In some embodiments, such as Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, it also includes: a dielectric layer 6 disposed between the first electrode 2 and the second electrode 4; a via 5 penetrating the dielectric layer 6; at least a portion of the gate 3 being embedded in the dielectric layer 6; a portion of the dielectric layer 6 being located between the first electrode 2 and the gate 3; and another portion of the dielectric layer 6 being located between the gate 3 and the second electrode 4.

[0068] For example, refer to Figure 2 , Figure 3 , Figure 4 and Figure 5 All gates 3 are embedded in the dielectric layer 6, and the embedding depth of the gates 3 in the dielectric layer 6 is different. That is, the orthogonal projection of the gate 3 on the substrate 1 can be located within the orthogonal projection of the second electrode 4 on the substrate 1, or the orthogonal projection of the gate 3 on the substrate 1 can be located within the orthogonal projection of the second electrode 4 on the substrate 1. That is, by adjusting the embedding depth of the gate 3 in the dielectric layer 6, the control force of the gate 3 on the electrons emitted by the first electrode 2 can be changed, thereby improving the switching ratio.

[0069] In some embodiments, such as Figure 2 , Figure 3 , Figure 4 The gate 3 is arranged around the through hole 5.

[0070] For example, such as Figure 2 , Figure 3 , Figure 4 The gate 3 in the vacuum transistor is ring-shaped, and the orthogonal projection of the gate 3 on the substrate 1 surrounds the orthogonal projection of the via 5 on the substrate 1. The orthogonal projection of the gate 3 on the substrate 1 is located within the orthogonal projection of the first electrode 2 on the substrate 1, thereby better controlling the transmission of electrons emitted by the first electrode 2 in the via 5, and thus improving the ability of the gate 3 to control electrons.

[0071] In some embodiments, such as Figure 2 As shown, the surface of the gate 3 facing the via 5 is flush with the surface of the dielectric layer 6 facing the via 5.

[0072] For example, refer to Figure 2 , Figure 2The gate 3 shown is arranged in a ring. The surface of the gate 3 facing the through hole 5 is flush with the surface of the dielectric layer 6 facing the through hole 5. That is, the surface of the gate 3 facing the through hole 5 coincides with the sidewall of the through hole 5, meaning there is no gap between the surface of the gate 3 facing the through hole 5 and the sidewall of the through hole 5. Since the through hole 5 penetrates the second electrode 5 along the first direction Z, that is, the surface of the second electrode 4 near the through hole 5 coincides with the sidewall of the through hole 5, the surface of the second electrode 4 facing the through hole 5 is flush with the surface of the dielectric layer 6 facing the through hole 5. With this arrangement, electrons emitted by the first electrode 2 can reach the second electrode 4 along the through hole 5. It is equivalent to the through hole 5 acting as an electron transport channel. The gate 3 is used to control the opening and closing of the vacuum transistor.

[0073] In some embodiments, such as Figure 3 As shown, the surface of the gate 3 facing the via 5 protrudes from the surface of the dielectric layer 6 facing the via 5.

[0074] For example, refer to Figure 3 The surface of the gate 3 facing the via 5 protrudes beyond the surface of the dielectric layer 6 facing the via 5. That is, part of the orthogonal projection of the gate 3 onto the substrate 1 lies within the orthogonal projection of the second electrode 4 onto the substrate 1, and the other part overlaps with the orthogonal projection of the via 5 onto the substrate 1. In other words, the gate 3 will cross the second electrode 4 and the dielectric layer 6 and approach the surface of the via 5. Part of the gate 3 is exposed in the via 5. With this configuration, the gate 3 captures electrons emitted by the first electrode 2, reducing the electron throughput to the second electrode 4 along the via 5. This enables improved control of the off-state current between the first electrode 2 and the second electrode 4 in the off-state, reducing the off-state leakage current, thereby improving the switching ratio of the vacuum transistor.

[0075] In some embodiments, such as Figure 4 As shown, the gate 3 is wrapped by the dielectric layer 6, and there is a gap between the surface of the gate 3 facing the via 5 and the surface of the dielectric layer 6 facing the via 5.

[0076] For example, refer to Figure 4 The gate 3 is encased in the dielectric layer 6, meaning that the gate 3 is buried in the dielectric layer 6. In other words, the orthogonal projection of the gate 3 onto the substrate 1 is located within the orthogonal projection of the second electrode 4 onto the substrate 1. That is, the gate 3 will not cross the surface of the second electrode 4 and the dielectric layer 6 near the via 5, and the gate 3 will not be exposed in the via 5. With this configuration, the gate 3 has less control over the electrons emitted by the first electrode 2, and the electrons can more easily reach the second electrode 4 along the via 5. This can improve the control of the off-state current between the first electrode 2 and the second electrode 4 in the on-state, thereby increasing the on-state current and reducing the on-state leakage current, thus improving the switching ratio of the vacuum transistor.

[0077] In some embodiments, such as Figure 2 , Figure 3, Figure 4 and Figure 5 The dielectric layer 6 includes a first dielectric layer 61 and a second dielectric layer 62. The first dielectric layer 61 is located between the gate 3 and the first electrode 2, and the second dielectric layer 62 is located between the gate 3 and the second electrode 4.

[0078] For example, such as Figure 2 , Figure 3 , Figure 4 and Figure 5 The dielectric layer 6 is made of organic or inorganic materials, including silicon oxide (SiO2), silicon nitride (SiNx), polyimide, etc. The first dielectric layer 61 serves as an insulating layer between the gate 3 and the first electrode 2. The first dielectric layer 61 must withstand the strong electric field generated by the gate bias voltage and prevent direct conduction between the gate 3 and the first electrode 2. The second dielectric layer 62 serves as an insulating layer between the gate 3 and the second electrode 4. The second dielectric layer 62 must isolate the high voltage potential difference between the gate and the second electrode 4 and reduce parasitic capacitance.

[0079] For example, the first dielectric layer 61 is made of a high dielectric constant material, such as hafnium oxide (HfO2), aluminum oxide (Al2O3), or silicon nitride (Si3N4), which can enhance the electric field modulation capability of the gate 3 while maintaining a high breakdown field strength. The second dielectric layer 62 can be made of a low dielectric loss material, such as silicon dioxide (SiO2) or magnesium fluoride (MgF2), which can reduce dielectric loss under high frequency signals and improve signal transmission efficiency.

[0080] In some embodiments, such as Figure 5 As shown in the figure, the gate 3 has a plurality of openings K that penetrate itself along the first direction Z, at least one opening K communicating with the through hole 5, and a portion of the gate 3 is located within the through hole 5.

[0081] For example, such as Figure 5 As shown, the multiple openings K of the gate 3 enhance the local modulation capability of the gate 3 on the surface electric field of the first electrode 2, reducing the driving voltage, for example, from 10V to below 5V. Simultaneously, it reduces leakage of the electric field in the non-emission region, enhancing electron emission from the first electrode 2 and improving energy efficiency. Furthermore, the via 5 is divided into multiple sub-regions by the gate 3 (separated by the multiple openings K of the gate 3), forming multiple sub-vacuum channels. After electrons are emitted from the first electrode 2, they must pass through the multiple openings K of the gate 3 into the vacuum channels and then be collected by the second electrode 4. This regional electron transport reduces energy loss due to electron collisions and improves electron collection efficiency. By controlling the electron beam cross-section (determined by the size of the openings K), the electron density within the via 5 can be limited, avoiding voltage drops caused by space charge accumulation, thereby maintaining stable output at high frequencies.

[0082] In some embodiments, such as Figure 6 As shown, the gate 3 includes a first part 31 and a second part 32; the first part 31 is disposed around the through hole 5; the second part 32 is located in the through hole 5 and is connected to the first part 31, forming a plurality of openings K.

[0083] For example, refer to Figure 6 The gate 3 includes a first portion 31 and a second portion 32 that are interconnected, wherein the first portion 31 is disposed around the second portion 32 and the first portion 31 is located away from the through hole 5 relative to the second portion 32. Figure 6 The second part 32 shown is cross-shaped and located within the through hole 5, dividing the through hole 5 into four fan-shaped holes. It should be noted that the shape of the second part 32 here is only illustrative; specifically, the shape of the second part 32 could also be star-shaped, dividing the area containing the through hole 5 into eight regions. Figure 5 After electrons are emitted from the first electrode 2, they can be transmitted to the second electrode 4 through eight channels. In other words, regional transmission can be achieved, avoiding voltage drop caused by space charge accumulation, and making the transmission process more uniform and stable.

[0084] In some embodiments, continue to refer to Figure 6 , combined Figure 5 The second portion 32 of the gate 3 covers the orthogonal projection of the substrate 1, and the portion of the first electrode 2 located in the through hole 5 is projected onto the center of the orthogonal projection of the substrate 1.

[0085] For example, continue to refer to Figure 6 , combined Figure 5 The center of the orthographic projection of the portion of the first electrode 2 located within the via 5 onto the substrate 1 is aligned with the center of the via 5. In other words, the center of the orthographic projection of the via 5 onto the substrate 1 coincides with the center of the orthographic projection of the portion of the first electrode 2 located within the via 5 onto the substrate 1. This configuration creates a "centrally symmetrical" electric field modulation structure, where the electric field lines generated by the gate voltage are uniformly distributed around the center of the first electrode 2 as the axis of symmetry, avoiding electric field tilting or edge effects caused by gate bias (such as electric field concentration at the electrode edge, leading to localized breakdown).

[0086] In some embodiments, such as Figure 7 , Figure 8 and Figure 9 As shown, there are multiple gates 3, and the multiple gates 3 are spaced apart along the first direction Z.

[0087] For example, multiple gates 3 are spaced apart along the Z-axis to form a "stepped" electric field distribution. Each gate can be independently biased with a voltage, enabling multi-level modulation of the electron beam. It should be noted that the electric field modulation range of traditional single-gate devices is limited by the gate voltage swing (e.g., ±5V), while multi-gate structures can extend the dynamic range to over ±15V through cascaded modulation, making them suitable for high-power applications. For instance, the gate 3 near the first electrode 2 can achieve potential control of the surface of the first electrode 2 with a smaller voltage (less than 10V), while the gate 3 near the second electrode 4 can control the direction of the electron beam with a larger voltage (greater than 20V), achieving precise collection of the electron beam.

[0088] In some embodiments, such as Figure 8 As shown, the plurality of gates 3 include a first gate 301 and a second gate 302; the first gate 301 has a plurality of openings K that penetrate itself along a first direction Z, at least one opening K communicating with a through hole, and a portion of the second gate 302 is located within the through hole 5; the second gate 302 is disposed around the through hole 5; the second gate 302 is further away from the substrate 1 than the first gate 301.

[0089] For example, the first gate 301 generates a strong electric field, drawing an electron beam from the first electrode 2, and the trajectory of the electron beam is finely adjusted by the second gate 302, allowing it to precisely bombard the second electrode 4. With this configuration, the first gate 301, due to its larger coverage area, can more effectively control the surface potential of the first electrode 2, making electron emission easier, while the annular structure of the second gate 302 can more effectively control the direction of the electron beam.

[0090] Some embodiments of this application also provide a method for fabricating a vacuum transistor 10, such as... Figure 10 As shown, the fabrication method of the vacuum transistor 10 includes the following steps S1 to S2:

[0091] S1. Reference Figure 2 A first electrode 2, a gate electrode 3, and a second electrode 4 are sequentially formed on the substrate 1 along the first direction Z, which is away from the substrate 1; the first direction Z is the thickness direction of the substrate 1; there is a gap between the first electrode 2 and the gate electrode 3, and between the gate electrode 3 and the second electrode 4 along the first direction Z.

[0092] S2, continue to refer to Figure 2 A through hole 5 is formed, which penetrates the second electrode 4 along the first direction Z and the film layer between the second electrode 4 and the first electrode 2, and exposes the side surface of the first electrode 2 facing away from the substrate 1.

[0093] Wherein, the orthogonal projection of the gate 3 onto the substrate 1 and the orthogonal projection of the second electrode 2 onto the substrate 1 at least partially overlap.

[0094] For example, the orthographic projection of the gate 3 on the substrate 1 and the orthographic projection of the second electrode 2 on the substrate 1 are configured to at least partially overlap. The specific beneficial effects are described in the foregoing section and will not be repeated here.

[0095] In some embodiments, such as Figure 11 As shown, combined with Figure 3 , Figure 4 , Figure 5 , Figure 13 , Figure 14 and Figure 15 On the substrate 1, a first electrode 2, a gate electrode 3, and a second electrode 4 are sequentially formed, including:

[0096] S11, Reference Figure 13 , Figure 14 and Figure 15 A first electrode 2, a first dielectric layer 61, and a gate layer 7 are sequentially formed on a substrate 1.

[0097] S12. Reference Figure 13 , Figure 14 and Figure 15 The gate layer 7 is etched to form the gate 3.

[0098] S13. Reference Figure 13 , Figure 14 and Figure 15 A second dielectric layer 62 is formed on the side of the gate 3 away from the substrate 1.

[0099] S14. Reference Figure 13 , Figure 14 and Figure 15 A second electrode layer 8 is formed on the side of the second dielectric layer 62 away from the substrate 1. The target area of ​​the second electrode layer 8 is etched to form the second electrode 4. The target area is a part of the area where the via 5 is formed.

[0100] S15. Reference Figure 13 , Figure 14 and Figure 15 Using the second electrode 4 as a mask, the first dielectric layer 61 and the second dielectric layer 62 are etched to form a through hole 5.

[0101] The following details the fabrication methods corresponding to different embodiments of vacuum transistors.

[0102] In some embodiments, refer to Figure 2 and Figure 12 , Figure 2 The method for fabricating the vacuum transistor shown specifically includes the following steps R1 to R8:

[0103] R1 provides substrate 1;

[0104] For example, the material of the substrate 1 can be a material with high insulation properties, such as glass, quartz, sapphire, low-resistivity silicon, etc.

[0105] R2, A first electrode 2 is formed on the substrate 1.

[0106] For example, an electron emission material is deposited on a substrate 1 by means of sputtering or chemical vapor deposition to form a first electrode 2. The thickness of the first electrode 2 is 10 nm to 500 nm, and the material of the first electrode 2 is tungsten, molybdenum, gold, zirconium, tantalum, platinum, or graphene, etc.

[0107] R3, A first dielectric layer 61 is formed on the first electrode 2.

[0108] For example, a first dielectric layer 61 is prepared on the first electrode 2 by chemical vapor deposition. The material of the first dielectric layer 61 can be silicon oxide (SiO2) or silicon nitride (SiNx), and the thickness of the first dielectric layer 61 is 50 nm to 200 nm.

[0109] R4. A gate layer 7 is formed on the first dielectric layer 61.

[0110] For example, a conductive material is deposited on the first dielectric layer 61 by a sputtering process. The material of the gate layer 7 is, for example, tungsten or aluminum, and the thickness of the gate layer 7 is 50 nm to 200 nm.

[0111] R5. A second dielectric layer 62 is formed on the gate layer 7.

[0112] It should be noted that the material and preparation process of the second dielectric layer 62 are the same as those described for forming the first dielectric layer 61, and will not be repeated here.

[0113] R6. A second electrode layer 8 is formed on the second dielectric layer 62.

[0114] For example, metallic materials such as copper, gold, and platinum are deposited on the second dielectric layer 62 by sputtering.

[0115] R7. Etch the second electrode layer 8 to form the second electrode 4.

[0116] For example, the second electrode layer 8 is patterned and etched to form the second electrode 4, the thickness of the second electrode 4 being 200 nm to 500 nm.

[0117] R8, forming through hole 5.

[0118] It should be noted that the second electrode 4 can be used as a hard mask to form the via 5. The first dielectric layer 61, the second dielectric layer, and the gate layer 7 are etched by dry etching to form the via.

[0119] For example, the diameter of the through hole 5 is 5μm to 20μm.

[0120] In some embodiments, refer to Figure 4 and Figure 13 , Figure 13 The method for fabricating the vacuum transistor shown specifically includes the following steps P1 to P7:

[0121] P1, Provide substrate 1;

[0122] For example, the material of the substrate 1 is described in the aforementioned partial step R1, and will not be repeated here.

[0123] P2. A first electrode 2 is formed on the substrate 1.

[0124] For example, an electron emission material is deposited on a substrate 1 by a sputtering process to form a first electrode 2. The thickness of the first electrode 2 is 100 nm, and the material of the first electrode 2 is, for example, tungsten.

[0125] P3. A first dielectric layer 61 is formed on the first electrode 2.

[0126] For example, a first dielectric layer 61 is prepared on the first electrode 2 by chemical vapor deposition. The material of the first dielectric layer 61 can be silicon nitride (SiNx), and the thickness of the first dielectric layer 61 is 100 nm.

[0127] P4. Form a gate layer 7 on the first dielectric layer 61, and etch the gate layer 7 to form a gate 3.

[0128] For example, a conductive material is deposited on the first dielectric layer 61 by a sputtering process, and the material of the gate layer 7 is, for example, copper, and the thickness of the gate layer 7 is 100 nm.

[0129] For example, the etching process of the gate layer 7 can be photolithography or wet etching to form the gate 3. The outer diameter of the gate 3 can be 10 μm and the inner diameter can be 6 μm.

[0130] P5. A second dielectric layer 62 is formed on the gate layer 7.

[0131] It should be noted that the material, thickness, and fabrication process of the second dielectric layer 62 are described in the same way as those for the formation of the first dielectric layer 61, and will not be repeated here.

[0132] P6. Form a second electrode layer 8 on the second dielectric layer 62, and etch the second electrode layer 8 to form a second electrode 4.

[0133] For example, aluminum with a thickness of 300 nm is deposited on the second dielectric layer 62 by sputtering, and a hole with a diameter of, for example, 4 μm is formed by photolithography or wet etching to form the second electrode 4.

[0134] P7, forming through hole 5.

[0135] It should be noted that the second electrode 4 can be used as a hard mask to form the via 5. The first dielectric layer 61 and the second dielectric layer are etched by dry etching, such as by an inductively coupled plasma (ICP) etching machine, to form the via 5 with a diameter of 4 μm.

[0136] In some embodiments, refer to Figure 3 and Figure 14 , Figure 14 The method for fabricating the vacuum transistor shown specifically includes the following steps Q1 to Q7:

[0137] Q1. Provide substrate 1;

[0138] For example, the material of the substrate 1 is described in the aforementioned partial step R1, and will not be repeated here.

[0139] Q2. Form a first electrode 2 on the substrate 1.

[0140] For example, an electron emission material is deposited on a substrate 1 by a sputtering process to form a first electrode 2. The thickness of the first electrode 2 is 50 nm, and the material of the first electrode 2 is, for example, molybdenum.

[0141] Q3. A first dielectric layer 61 is formed on the first electrode 2.

[0142] For example, a first dielectric layer 61 is prepared on the first electrode 2 by chemical vapor deposition. The material of the first dielectric layer 61 can be silicon oxide (SiO2), and the thickness of the first dielectric layer 61 is 150 nm.

[0143] Q4. Form a gate layer 7 on the first dielectric layer 61, and etch the gate layer 7 to form a gate 3.

[0144] For example, a conductive material is deposited on the first dielectric layer 61 by a sputtering process, and the material of the gate layer 7 is, for example, aluminum, and the thickness of the gate layer 7 is 150 nm.

[0145] For example, the etching process of the gate layer 7 can be photolithography or chlorine-based dry etching to form the gate 3. The outer diameter of the gate 3 can be 10 μm and the inner diameter can be 4 μm.

[0146] Q5. A second dielectric layer 62 is formed on the gate layer 7.

[0147] It should be noted that the material, thickness, and fabrication process of the second dielectric layer 62 are described in the same way as those for the formation of the first dielectric layer 61, and will not be repeated here.

[0148] Q6. Form a second electrode layer 8 on the second dielectric layer 62, and etch the second electrode layer 8 to form a second electrode 4.

[0149] For example, gold (Au) with a thickness of 300 nm is deposited on the second dielectric layer 62 by sputtering, and a hole with a diameter of, for example, 6 μm is formed by photolithography or wet etching to form the second electrode 4.

[0150] Q7, Form through hole 5.

[0151] It should be noted that the second electrode 4 can be used as a hard mask to form the via 5. The first dielectric layer 61 and the second dielectric layer are etched by dry etching, such as by an inductively coupled plasma (ICP) etching machine, to form the via 5 with a diameter of 4 μm.

[0152] In some embodiments, refer to Figure 5 and Figure 15 , Figure 15 The method for fabricating the vacuum transistor shown specifically includes the following steps T1 to T7:

[0153] T1, Provide substrate 1;

[0154] For example, the material of the substrate 1 is described in the aforementioned partial step R1, and will not be repeated here.

[0155] T2. A first electrode 2 is formed on the substrate 1.

[0156] For example, an electron emission material is deposited on a substrate 1 by a sputtering process to form a first electrode 2. The thickness of the first electrode 2 is 50 nm, and the material of the first electrode 2 is, for example, molybdenum.

[0157] T3. A first dielectric layer 61 is formed on the first electrode 2.

[0158] For example, a first dielectric layer 61 is prepared on the first electrode 2 by chemical vapor deposition. The material of the first dielectric layer 61 can be silicon nitride (SiNx), and the thickness of the first dielectric layer 61 is 100 nm.

[0159] T4. Form a gate layer 7 on the first dielectric layer 61, and etch the gate layer 7 to form a gate 3.

[0160] For example, a conductive material is deposited on the first dielectric layer 61 by a sputtering process, and the material of the gate layer 7 is, for example, aluminum, and the thickness of the gate layer 7 is 70 nm.

[0161] For example, the etching process of the gate layer 7 can be photolithography or chlorine-based dry etching to form the gate 3.

[0162] T5. A second dielectric layer 62 is formed on the gate layer 7.

[0163] It should be noted that the material, thickness, and fabrication process of the second dielectric layer 62 are described in the same way as those for the formation of the first dielectric layer 61, and will not be repeated here.

[0164] T6. Form a second electrode layer 8 on the second dielectric layer 62, and etch the second electrode layer 8 to form a second electrode 4.

[0165] For example, gold (Au) with a thickness of 300 nm is deposited on the second dielectric layer 62 by sputtering, and a hole with a diameter of, for example, 6 μm is formed by photolithography or wet etching to form the second electrode 4.

[0166] T7, forming through hole 5.

[0167] It should be noted that the second electrode 4 can be used as a hard mask to form the via 5. The first dielectric layer 61 and the second dielectric layer are etched by dry etching, such as by an inductively coupled plasma (ICP) etching machine, to form the via 5 with a diameter of 4 μm.

[0168] It should be noted that, referring to Figures 7-9 When the gate 3 includes a first gate 301 and a second gate 302, the specific fabrication process is as described above and will not be repeated here. It is understood that when the gate 3 includes a first electrode 301 and a second electrode 302, the dielectric layer 6 may include three dielectric layers, respectively located between the first electrode 2 and the first gate 301, between the first gate 301 and the second gate 302, and between the second gate 302 and the second electrode 4.

[0169] In some embodiments, refer to Figure 16 , Figure 16 The method for fabricating the vacuum transistor shown specifically includes the following steps F1 to T5:

[0170] F1. Provide substrate 1;

[0171] For example, the substrate 1 is made of glass.

[0172] F2. A first electrode 2 is formed on the substrate 1.

[0173] For example, an electron emission material gold (Au) is deposited on a substrate 1 by a sputtering process to form a first electrode 2. The thickness of the first electrode 2 is 300 nm, and the material of the first electrode 2 is, for example, molybdenum.

[0174] F3. The first electrode 2 is hot-pressed using a hot-pressing process.

[0175] For example, sapphire or mica can be used to hot press the first electrode 2 in the hot pressing process. The hot pressing time is, for example, 30 minutes, the temperature is 250°C, and the pressure is 10 MPa.

[0176] It should be noted that, referring to Figure 16 , Figure 16 The glass substrate shown is rougher than other semiconductor substrates, and the bumps on the surface can easily cause the vacuum transistor to break down, especially the gate 3 near the first electrode 2. Therefore, the first electrode 2 is treated by hot pressing to reduce the probability of the vacuum transistor breaking down.

[0177] F4. An isolation layer 9 is formed on the first electrode 2.

[0178] It should be noted that the insulation layer 9 is mainly used for heat insulation.

[0179] F5, Remove isolation layer 9.

[0180] It should be noted that after removing the isolation layer 9, the subsequent process steps for fabricating the gate and the second electrode are as described above, and will not be repeated here.

[0181] Some embodiments of this application also provide an array substrate 100, see reference Figure 1 The array substrate 100 includes a plurality of vacuum transistors 10 as described in any of the above embodiments.

[0182] For example, the array substrate 100 includes the vacuum transistor 10 provided in the above embodiments, and has all the beneficial effects of the vacuum transistor 10, which will not be described in detail here.

[0183] The array substrate mentioned above can be an array substrate in display panels such as liquid crystal display (LCD), organic light-emitting diode (OLED), quantum dot light-emitting diode (QLED), and micro light-emitting diode (Micro LED), and this utility model does not specifically limit it.

[0184] In some embodiments, such as Figure 9As shown, the vacuum transistor 10 includes a first gate 301 and a second gate 302 spaced apart along a first direction Z. The second gate 302 is further away from the substrate 1 than the first gate 301. The array substrate 100 also includes a first resistor W1 and a second resistor W2. The first end of the first resistor W1 is connected to the first gate 301, and the first end of the second resistor W2 is connected to the second gate 302. The resistance of the first resistor W1 is greater than the resistance of the second resistor W2. The second ends of the first resistor W1 and the second ends of the second resistor W2 are both configured to be connected to the same power supply.

[0185] For example, refer to Figure 9 The first gate 301 and the second gate 302 are connected in parallel to the same voltage source. By using a resistor divider, the first resistor W1 is connected in series with the first gate 301, and the second resistor W2 is connected in series with the second gate 302. This configuration simplifies the power supply system and reduces costs by adjusting the resistance values, and allows for precise control of the voltage ratio between G1 and G2, making it suitable for integrated circuit applications. The adjustment of the resistors ensures that the voltage of the first gate 301 is less than the voltage of the second electrode 302. The first gate 301 can control the surface potential of the first electrode 2, and the second electrode 302 can control the direction of the electron beam, achieving precise collection of the electron beam.

[0186] Furthermore, some embodiments of this disclosure also provide an electronic device 1000, such as... Figure 17 As shown, the electronic device 1000 includes an array substrate 100 as provided in any of the above embodiments and a circuit board 200 connected to the array substrate 100.

[0187] For example, the electronic device 1000 includes the array substrate 100 provided in the above embodiments and has all the beneficial effects of the array substrate 100, which will not be described in detail here.

[0188] Exemplary examples show that the aforementioned electronic device 1000 may be a millimeter-wave radar, a detector, a high-speed modulator, a sensor, and any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, television (TV) products, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 17 The following example uses a mobile phone product as an illustration.

[0189] In terms of its form, the electronic device 1000 can be a planar electronic device, a curved electronic device, or a foldable electronic device, etc. In terms of its shape, the electronic device 1000 can be rectangular or circular, etc. This disclosure does not impose any limitations in this regard, and adaptive designs can be made according to actual needs.

[0190] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0191] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A vacuum transistor, characterized in that, include: Substrate; A first electrode, a gate electrode, and a second electrode are sequentially stacked on the substrate along a first direction that gradually moves away from the substrate. The first direction is the thickness direction of the substrate. There is a gap between the first electrode and the gate electrode, and between the gate electrode and the second electrode, along the first direction. A via, the via penetrating the second electrode along the first direction and the film layer between the second electrode and the first electrode, and exposing the side surface of the first electrode facing away from the substrate; Wherein, the orthographic projection of the gate on the substrate overlaps with the orthographic projection of the second electrode on the substrate.

2. The vacuum transistor according to claim 1, characterized in that, Also includes: A dielectric layer is disposed between the first electrode and the second electrode; The via penetrates the dielectric layer, at least a portion of the gate is embedded in the dielectric layer, and a portion of the dielectric layer is located between the first electrode and the gate, while another portion of the dielectric layer is located between the gate and the second electrode.

3. The vacuum transistor according to claim 2, characterized in that, The gate is disposed around the through hole.

4. The vacuum transistor according to claim 3, characterized in that, The surface of the gate facing the via is flush with the surface of the dielectric layer facing the via.

5. The vacuum transistor according to claim 3, characterized in that, The surface of the gate facing the via protrudes beyond the surface of the dielectric layer facing the via.

6. The vacuum transistor according to claim 3, characterized in that, The gate is enclosed by the dielectric layer, and there is a gap between the surface of the gate facing the via and the surface of the dielectric layer facing the via.

7. The vacuum transistor according to claim 2, characterized in that, The dielectric layer includes: A first dielectric layer and a second dielectric layer, wherein the first dielectric layer is located between the gate and the first electrode, and the second dielectric layer is located between the gate and the second electrode.

8. The vacuum transistor according to claim 1, characterized in that, The gate has a plurality of openings extending through itself along the first direction, at least one of the openings communicating with the through hole, and a portion of the gate is located within the through hole.

9. The vacuum transistor according to claim 8, characterized in that, The gate includes a first portion and a second portion; The first portion is disposed around the through hole; the second portion is located in the through hole and connected to the first portion, forming the plurality of openings.

10. The vacuum transistor according to claim 9, characterized in that, The second portion of the gate is projected onto the substrate, and the portion of the first electrode located within the via is projected onto the center of the substrate.

11. The vacuum transistor according to any one of claims 1 to 10, characterized in that, The number of gates is multiple, and the multiple gates are spaced apart along the first direction.

12. The vacuum transistor according to claim 10, characterized in that, The plurality of gates includes a first gate and a second gate; The first gate has a plurality of openings extending through itself along the first direction, at least one of the openings communicating with the through hole, and a portion of the second gate is located within the through hole; the second gate is disposed around the through hole; The second gate is further away from the substrate than the first gate.

13. An array substrate, characterized in that, It includes a plurality of vacuum transistors as described in any one of claims 1-12 arranged in an array.

14. The array substrate according to claim 13, characterized in that, The vacuum transistor includes a first gate and a second gate that are spaced apart along the first direction, wherein the second gate is further away from the substrate than the first gate. The array substrate further includes: a first resistor and a second resistor, wherein a first end of the first resistor is connected to the first gate, a first end of the second resistor is connected to the second gate, and the resistance value of the first resistor is greater than the resistance value of the second resistor. The second terminals of the first resistor and the second resistor are both configured to be connected to the same power supply.

15. An electronic device, characterized in that, include: The array substrate as described in claim 13 or 14.

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