Solar cell and solar cell module
By setting passivated contact areas and electrode layers on the back of solar cells, selectively removing polycrystalline silicon layers, and optimizing the layout to form a grid structure, the parasitic absorption of light by polycrystalline silicon layers is solved, improving the photocurrent density and cell conversion efficiency, and achieving more efficient photoelectric conversion.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- DAS SOLAR CO LTD
- Filing Date
- 2025-08-29
- Publication Date
- 2026-06-26
Smart Images
Figure CN224419199U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of photovoltaic power generation technology, and in particular to a solar cell and a solar cell module. Background Technology
[0002] In the traditional TOPCon battery structure, a silicon dioxide oxide layer with a thickness of 1-3 nm is first grown on the back side as a tunneling layer, which allows carriers to be transported through the quantum tunneling effect. Subsequently, a polycrystalline silicon layer with a thickness of 120-160 nm is deposited outside the oxide layer, and an n+ type polycrystalline silicon passivation layer is formed by heavy phosphorus ion doping to achieve good surface passivation and carrier collection.
[0003] However, this structure has a significant drawback: the thicker polycrystalline silicon layer on the back has a strong parasitic absorption effect on incident light, which causes some photons to be unable to be effectively utilized by the cell, thereby reducing the short-circuit current density of the solar cell. Utility Model Content
[0004] In view of this, this application provides a solar cell and a solar cell module, with the aim of solving one of the technical problems in the prior art.
[0005] To achieve the above objectives, the technical solution adopted in this application is as follows:
[0006] In a first aspect, this application provides a solar cell, comprising:
[0007] Base silicon;
[0008] A passivated contact region is disposed on the back side of the substrate silicon;
[0009] An electrode layer is disposed in the passivation contact region, and in the direction away from the substrate silicon, the projection pattern of the passivation contact region is the same as the projection pattern of the electrode layer.
[0010] In an optional embodiment, the electrode layer includes multiple transverse gate lines and multiple longitudinal gate lines;
[0011] The passivated contact area includes multiple lateral sub-regions and multiple longitudinal sub-regions, with the lateral grid lines disposed in the lateral sub-regions and the longitudinal grid lines disposed in the longitudinal sub-regions;
[0012] The width of the horizontal sub-region and the vertical sub-region is 200-600 μm.
[0013] In an optional embodiment, the passivated contact region further includes a spacer sub-region, which is disposed between two adjacent lateral sub-regions, or the spacer sub-region is disposed between two adjacent lateral sub-regions.
[0014] In the spacer sub-region, the substrate silicon surface is exposed.
[0015] In an optional embodiment, a groove is formed on the substrate silicon surface in the spacer sub-region, the groove having a depth of 0.5-2 μm.
[0016] In an optional embodiment, the groove wall on the side facing the spacer sub-region has a velvety structure.
[0017] In an optional embodiment, in the direction away from the back side of the substrate silicon, the passivation contact region includes a tunneling layer, a polysilicon layer and a passivation layer stacked sequentially, and the electrode layer is disposed on the passivation layer and electrically connected to the polysilicon layer.
[0018] In an optional implementation, the passivation layer also completely covers the walls of the groove.
[0019] In an optional embodiment, the thickness of the tunneling layer is 1.5-2.5 nm.
[0020] In an optional embodiment, the thickness of the polycrystalline silicon layer is 120-160 nm.
[0021] Secondly, this application provides a solar cell module, including the solar cell described in any of the foregoing embodiments.
[0022] Compared to existing technologies, the advantages of this application are as follows: This application proposes a solar cell comprising a silicon substrate, a passivation contact region, and an electrode layer. The passivation contact region is disposed on the back side of the silicon substrate, and the electrode layer is disposed on the passivation contact region. In the direction away from the silicon substrate, the projected pattern of the passivation contact region is the same as the projected pattern of the electrode layer. Compared to related technologies that lay a large area of the passivation contact region on the back side of the silicon substrate, by removing the polycrystalline silicon layer in the non-slurry contact region while retaining its functional role in the metal electrode contact region, the parasitic absorption of light by the polycrystalline silicon layer is reduced, allowing more photons to enter the silicon substrate and generate electron-hole pairs, thereby increasing the photocurrent density and improving the cell conversion efficiency. Attached Figure Description
[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 The present application shows schematic diagrams of the structure of solar cells in some embodiments;
[0025] Figure 2 A schematic diagram of the cross-sectional structure of a solar cell in some embodiments of this application is shown.
[0026] Key component symbols: 100 - Solar cell; 110 - Substrate silicon; 120 - Passivation contact area; 130 - Electrode layer; 131 - Lateral grid line; 132 - Vertical grid line; 125 - Lateral sub-region; 126 - Vertical sub-region; 124 - Spacer sub-region; 1241 - Groove; 12411 - Fleece structure; 121 - Tunneling layer; 122 - Polycrystalline silicon layer; 123 - Passivation layer. Detailed Implementation
[0027] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0028] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0030] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0031] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0032] like Figure 1 and Figure 2 As shown, an embodiment of this application provides a solar cell 100, which is mainly used to reduce parasitic light loss and increase cell current by removing the polycrystalline silicon layer in the non-slurry contact area, thereby improving efficiency. The solar cell 100 includes a substrate silicon 110, a passivated contact area 120, and an electrode layer 130.
[0033] The substrate silicon 110 is either N-type or P-type.
[0034] A passivation contact region 120 is disposed on the back side of the substrate silicon 110, and an electrode layer 130 is disposed on the passivation contact region 120. In the direction away from the substrate silicon 110, the projected pattern of the passivation contact region 120 is the same as the projected pattern of the electrode layer 130. Compared with the related technology that lays a large area of the passivation contact region 120 on the back side of the substrate silicon 110, this application selectively removes the polycrystalline silicon layer 122 in the non-slurry contact area, retaining its functional role in the metal electrode contact area. This reduces the parasitic absorption of light by the polycrystalline silicon layer 122, allowing more photons to enter the silicon substrate and generate electron-hole pairs, increasing the photogenerated current density, and ultimately improving the cell conversion efficiency.
[0035] The solar cell in this application is a TOPCon cell, an HJT cell, or a PERC cell.
[0036] In some embodiments, such as Figure 1 As shown, the electrode layer 130 includes multiple horizontal grid lines 131 and multiple vertical grid lines 132. The horizontal grid lines 131 and the vertical grid lines 132 form a grid structure and are uniformly distributed on the surface of the battery.
[0037] Correspondingly, the passivated contact area 120 includes multiple lateral sub-regions 125 and multiple longitudinal sub-regions 126. The lateral sub-regions 125 and longitudinal sub-regions 126 are interwoven to form a grid-like layout, which makes the current collection more uniform and reduces resistance loss.
[0038] Horizontal grid lines 131 are disposed in horizontal sub-region 125, and vertical grid lines 132 are disposed in vertical sub-region 126. By optimizing the layout of the passivated contact region 120, the current transmission path is shortened, and resistance loss is reduced. This structure also facilitates compatibility with existing battery manufacturing processes without requiring significant modifications to production line equipment.
[0039] In some embodiments, such as Figure 1 As shown, the widths of the horizontal sub-region 125 and the vertical sub-region 126 are 200-600 μm.
[0040] It is understandable that, in order to increase the connection stability between the electrode layer 130 and the polysilicon layer 122, the width of the vertical sub-region 126 or the horizontal sub-region 125 should be increased accordingly in the areas where the vertical gate line 132 and the horizontal gate line 131 are thicker. The specific width of each horizontal sub-region 125 and the vertical sub-region 126 are set according to requirements.
[0041] Specifically, the width of the horizontal sub-region 125 is 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm, etc., and is not limited to the width in the example.
[0042] Specifically, the width of the vertical sub-region 126 is 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm, etc., and is not limited to the width in the example.
[0043] It is understood that in electrode layer 130, there are gaps between adjacent transverse gate lines 131 and between adjacent longitudinal gate lines 132. The passivation contact region 120 and the electrode layer 130 have the same projected pattern.
[0044] Accordingly, in this embodiment, the passivated contact region 120 also has a spacer sub-region 124, which is disposed between two adjacent lateral sub-regions 125, or the spacer sub-region 124 is disposed between two adjacent lateral sub-regions 125.
[0045] In some embodiments, such as Figure 2 As shown, in the spacer sub-region 124, the surface of the substrate silicon 110 is exposed, reducing the unnecessary polycrystalline silicon layer 122, reducing parasitic light absorption and resistance loss, and improving the photoelectric conversion efficiency of the cell.
[0046] The polysilicon layer 122 is either P-type or N-type. The P-type polysilicon layer 122 is obtained by boron doping of the polysilicon layer 122, and the N-type polysilicon layer 122 is obtained by phosphorus diffusion of the polysilicon layer 122.
[0047] It is understandable that in the phosphorus diffusion process, a certain amount of phosphorus atoms diffuse through the polycrystalline silicon layer 122 and enter the substrate silicon 110. The penetration depth is usually 0.2μm, forming a recombination center to reduce the on-state voltage of the solar cell 100.
[0048] To address the above problems, in some embodiments, such as Figure 2 As shown, in the spacer region 124, a groove 1241 is formed on the surface of the substrate silicon 110, and the depth of the groove 1241 is 0.5-2 μm. The portion of the substrate silicon 110 containing phosphorus atoms that has penetrated into the substrate silicon 110 is removed, thereby reducing Auger recombination within the substrate silicon 110 and improving the on-state voltage of the solar cell 100.
[0049] Specifically, the depth of the groove 1241 is 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, etc., and is not limited to the depth of the example.
[0050] It should be noted that there are multiple grooves 1241, and there is no limitation on the cross-sectional shape of each groove 1241.
[0051] In some embodiments, such as Figure 2 As shown, the groove 1241 has a velvety structure 12411 on one side of the groove facing the spacer region 124, which improves the light absorption rate of the back side of the solar cell and improves the bifaciality of the cell.
[0052] In some embodiments, such as Figure 2 As shown, in the direction away from the back of the substrate silicon 110, the passivation contact region 120 includes a tunneling layer 121, a polysilicon layer 122 and a passivation layer 123 stacked sequentially, and an electrode layer 130 is disposed on the passivation layer 123 and electrically connected to the polysilicon layer 122.
[0053] The polysilicon layer 122 is either P-type or N-type.
[0054] In one embodiment, such as Figure 2 As shown, the electrode layer 130 passes through the passivation layer 123 and is embedded in the polysilicon layer 122.
[0055] In some embodiments, such as Figure 2 As shown, the passivation layer 123 also completely covers the wall of the groove 1241.
[0056] In some embodiments, the thickness of the tunneling layer 121 is 1.5-2.5 nm.
[0057] In one embodiment, the tunneling layer 121 is a silicon oxide thin film layer.
[0058] Specifically, the thickness of the tunneling layer 121 is 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, 2nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, etc., and is not limited to the thickness in the example.
[0059] In some embodiments, the thickness of the polysilicon layer 122 is 120-160 nm.
[0060] Specifically, the thickness of the polysilicon layer 122 is 120nm, 130nm, 140nm, 150nm, 125nm, 135nm, 145nm, 155nm, 160nm, etc., and is not limited to the thickness in the example.
[0061] Taking TOPCon batteries as an example, the method for manufacturing the solar cells in this application is as follows:
[0062] Step S1: Double-sided texturing of the N-type silicon wafer ensures the reflectivity of the texturized surface is between 9.5% (9%-10%). The selected solution is 15L (10-20L) NaOH, 4.0L (3-6L) texturing additive, 465L (450-500L) water, and the temperature is 77℃ (75-85℃). The texturing additive consists of 2-3% surfactant, 1-3% defoamer, 1-1.5% nucleating agent, 0.5-1% sodium citrate, 4-6% sodium benzoate, and 80-85% water. The concentration of the concentrated NaOH is 40%. The defoamer can be oxypropylene glycerol ether or not. The nucleating agent is sodium citrate.
[0063] Step S2: Diffusion is performed on the texturized silicon wafer. The silicon wafer is heated to 830℃ (830-870℃), BCL3 flow rate is 180sccm / min (180-220), oxygen is 700sccm / min (700-900), pressure is 150mbar (120-180), nitrogen is 2000sccm / min (1500-3000), and time is 10min (10-15). The silicon wafer is then heated to 1045℃ (1030-1050), oxygen is 18000sccm / min (15000-20000), time is 60min (50-80min), and pressure is 800mbar (700-950).
[0064] Step S3: Perform alkaline polishing on the silicon wafer from Step S2 to remove the backside BSG using 550L (500-600) of chain HF and 50L (50-100) of water, followed by alkaline polishing using 20L (19-26L) of NaOH at 75℃ (70-80℃), 4L (3-6) of additives, and 470L (450-500) of water. The additives consist of: 2-3% surfactant, 2-3% defoamer, 2-4% antifoaming agent, 2-3% glucose, 2-3% sodium polystyrene sulfonate, and 80-85% water. The defoamer can be oxypropylene glycerol ether or oxypropylene glycerol ether; the antifoaming agent is polydimethylsiloxane.
[0065] Step S4: First, a 2.0nm (1.5-2.5nm) silicon oxide thin film layer is grown on the back side as the tunneling oxide layer of the TOPCon core structure. The tunneling oxide layer serves as an insulating layer. However, in the subsequent phosphorus diffusion process, phosphorus atoms will leave voids after penetrating the oxide layer, becoming pinholes, which serve as dedicated channels for electron movement, greatly improving the efficiency of the solar cell.
[0066] Outside the tunneling oxide layer, a 140 nm (120-160 nm) thick polycrystalline silicon layer 122 is grown to serve as a passivation layer 123 and form an ohmic contact with the slurry.
[0067] Step S5: Perform phosphorus diffusion with phosphorus oxychloride flow rate of 1700 sccm / min (1400-1800), oxygen flow rate of 600 sccm / min (500-700), pressure of 170 mbar (150-200), time of 20 min (14-20 min), and temperature of 800℃ (785-805); then heat the silicon wafer to 888℃ (870-890) and advance it for 30 min (25-35 min), with a phosphorus atom surface concentration of 7.2E20 / cm3; the PSG (phosphorus atom and silicon dioxide complex) thickness is 40 nm (30-50 nm).
[0068] Step S6: Print the mask layer. The printing width of the mask layer is 400um (200-600um), and the height is 20um (10-30um). The printing area is consistent with the position of the paste grid lines. The mask layer is insoluble in HF and protects the phosphorus diffusion PSG.
[0069] The mask layer is soluble in NaOH solution; the main components are 83% (80-90%) cyclized polyisoprene resin; 6% (5-10%) diazid crosslinking agent; 5% (2%-8%) maleic anhydride copolymer; 2% (1%-2%) benzophenone; and 4% (2%-10%) propylene glycol methyl ether acetate.
[0070] Step S7: Immerse the silicon wafer in a chain machine for HF etching, controlling the HF concentration at 6% (5-10%) for removal. The chain machine length is 3.6 meters and the belt speed is 3.5 m / s. PSG in the mask layer protected area is not removed; PSG in the non-mask layer area is removed.
[0071] The silicon wafer is subjected to alkaline etching to remove the polysilicon layer 122 in the non-mask area and to etch the silicon substrate under the polysilicon layer 122 to a depth of 1µm (0.5-2µm); the mask layer dissolves in the alkaline solution during this process and is simultaneously cleaned.
[0072] Alkaline etching: Set up 16L (16-24%) NaOH, 450L (400-500%) water, 4.0L (3-7L) additives, temperature 81℃ (70-85℃), time 280S (250-300S); where the additive composition is: surfactant 1.5% (1-2%), defoamer 2.5% (2-3%), antifoamer 3% (1-3%), glucose 4% (2-4%), sodium dodecyl sulfonate 2% (1-3%), water 87% (80-90%); the defoamer can be oxypropylene glycerol ether or oxypropylene glycerol ether; the antifoamer is octylphenol polyoxyethylene ether.
[0073] Step S8: Continue HF cleaning with an HF concentration of 30% (25-40%) and a cleaning time of 120 seconds (100-150 seconds) to remove PSG from under the mask layer.
[0074] Step S9: Perform subsequent ALD on the silicon wafer (3.5nm (2.5-5nm), front silicon nitride (76nm (70-84nm)), back silicon nitride (80nm (75-90nm)), printing and sintering (sintering temperature 810℃ (780-840℃), time 50S (40-70S)).
[0075] This application also provides a solar cell module, including the solar cell 100 in any of the above embodiments, and therefore has all the beneficial effects of the solar cell 100 in any of the above embodiments, which will not be described in detail here.
[0076] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0077] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A solar cell, characterized in that, include: Base silicon; A passivated contact region is disposed on the back side of the substrate silicon; An electrode layer is disposed in the passivation contact region, and in the direction away from the substrate silicon, the projection pattern of the passivation contact region is the same as the projection pattern of the electrode layer.
2. The solar cell according to claim 1, characterized in that, The electrode layer includes multiple horizontal grid lines and multiple vertical grid lines; The passivated contact area includes multiple lateral sub-regions and multiple longitudinal sub-regions, with the lateral grid lines disposed in the lateral sub-regions and the longitudinal grid lines disposed in the longitudinal sub-regions; The width of the horizontal sub-region and the vertical sub-region is 200-600 μm.
3. The solar cell according to claim 2, characterized in that, The passivated contact area also has a spacer sub-region, which is located between two adjacent transverse sub-regions, or the spacer sub-region is located between two adjacent transverse sub-regions. In the spacer sub-region, the substrate silicon surface is exposed.
4. The solar cell according to claim 3, characterized in that, In the spacer sub-region, a groove is formed on the substrate silicon surface, the groove having a depth of 0.5-2 μm.
5. The solar cell according to claim 4, characterized in that, The groove wall on the side facing the spacer sub-region has a velvety structure.
6. The solar cell according to claim 4, characterized in that, In the direction away from the back of the substrate silicon, the passivation contact region includes a tunneling layer, a polysilicon layer and a passivation layer stacked sequentially, and the electrode layer is disposed on the passivation layer and electrically connected to the polysilicon layer.
7. The solar cell according to claim 6, characterized in that, The passivation layer also completely covers the walls of the groove.
8. The solar cell according to claim 6, characterized in that, The thickness of the tunneling layer is 1.5-2.5 nm.
9. The solar cell according to claim 6, characterized in that, The thickness of the polycrystalline silicon layer is 120-160 nm.
10. A solar cell module, characterized in that, Includes the solar cell as described in any one of claims 1 to 8.