Display device and electronic device

Abstract

A display device and an electronic device are provided. The display device includes a bank surrounding an emission region, first electrodes and second electrodes spaced apart from each other in the emission region, and light emitting elements disposed between the first electrodes and the second electrodes, and, in a case where a diameter of each of the light emitting elements is α, a maximum distance between the light emitting elements in a first direction is 25α or less, and a maximum distance between a light emitting element closest to the bank among the light emitting elements in the first direction and the bank is 12.5α or less.

Description

Technical Field

[0001] The embodiments relate to display devices and electronic devices. Background Technology

[0002] In recent years, with increasing attention to information display, research and development of display devices has been ongoing. Utility Model Content

[0003] The embodiments provide a display device with improved reliability.

[0004] The scope of this disclosure is not limited to the objects described above, and other technical objects not mentioned will be clearly understood by those skilled in the art from the following description.

[0005] According to an embodiment, the display device may include: a dam surrounding an emitting region; a first electrode and a second electrode spaced apart from each other in the emitting region; and a light-emitting element disposed between the first electrode and the second electrode. When the diameter of each of the light-emitting elements is α, the maximum distance between the light-emitting elements in a first direction may be 25α or less, and the maximum distance between the light-emitting element closest to the dam in the first direction and the dam may be 12.5α or less.

[0006] α can be 0.5 μm or smaller.

[0007] The maximum distance between light-emitting elements in the first direction can be 4 μm or greater.

[0008] The embankment may extend in a second direction intersecting the first direction, and may include a first extension and a second extension spaced apart from each other in the first direction.

[0009] The maximum distance between the light-emitting element closest to the first extension and the first extension in the first direction can be 12.5α or less.

[0010] The maximum distance between the light-emitting element closest to the second extension in the first direction and the second extension can be 12.5α or less.

[0011] The first electrode and the second electrode can be spaced apart from each other in a second direction that intersects with the first direction.

[0012] The first end of the light-emitting element can face the first electrode, and the second end of the light-emitting element can face the second electrode.

[0013] The display device may also include a first connecting electrode and a second connecting electrode disposed on the light-emitting element.

[0014] The first connecting electrode can be electrically connected to the first end of the light-emitting element, and the second connecting electrode can be electrically connected to the second end of the light-emitting element.

[0015] To achieve the above objectives, the display device according to an embodiment may include: a dam surrounding an emitting region; a first electrode and a second electrode spaced apart from each other in the emitting region; and a light-emitting element disposed between the first electrode and the second electrode. The maximum number of light-emitting elements disposed in the emitting region can satisfy the following formula 1.

[0016] 2γ+nα+(n-1)β=δ

[0017] Here, α can be the diameter of each of the light-emitting elements, β can be the maximum distance between the light-emitting elements in the first direction, γ can be the maximum distance between the light-emitting element closest to the embankment in the first direction and the embankment, n can be the maximum number of light-emitting elements set in the emission region, and δ can be the maximum length of the emission region in the first direction.

[0018] β can be 25α or smaller.

[0019] γ can be 12.5α or smaller.

[0020] α can be 0.5 μm or smaller.

[0021] β can be 4 μm or larger.

[0022] The first electrode and the second electrode can be spaced apart from each other in a second direction that intersects with the first direction.

[0023] The first end of the light-emitting element can face the first electrode, and the second end of the light-emitting element can face the second electrode.

[0024] The display device may also include a first connecting electrode and a second connecting electrode disposed on the light-emitting element.

[0025] The display device may also include an insulating pattern disposed between the light-emitting element and the first connecting electrode and / or the second connecting electrode.

[0026] The first connecting electrode can be electrically connected to the first end of the light-emitting element exposed by the insulating pattern, and the second connecting electrode can be electrically connected to the second end of the light-emitting element exposed by the insulating pattern.

[0027] According to an embodiment, the electronic device may include: a processor for providing input image data; and a display device for displaying an image based on the input image data, the display device defining a sub-pixel region, wherein the display device includes a dam surrounding an emission region, a first electrode and a second electrode spaced apart from each other in the emission region, and light-emitting elements disposed between the first electrode and the second electrode. When the diameter of each of the light-emitting elements is α, the maximum distance between the light-emitting elements in a first direction may be 25α or less, and the maximum distance between the light-emitting element closest to the dam in the first direction and the dam may be 12.5α or less.

[0028] Specific details of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0029] The accompanying drawings illustrate embodiments of the present application and, together with the specification, serve to explain the principles of the present application. The drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this specification.

[0030] Figure 1 This is a schematic perspective view showing a light-emitting element according to an embodiment.

[0031] Figure 2 This is a schematic cross-sectional view showing a light-emitting element according to an embodiment.

[0032] Figure 3 This is a schematic plan view illustrating a display device according to an embodiment.

[0033] Figure 4 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0034] Figure 5 and Figure 6 This is a schematic plan view showing pixels according to an embodiment.

[0035] Figure 7 This is a schematic plan view used to explain the arrangement of the light-emitting elements according to the embodiments.

[0036] Figure 8 It is along Figure 5 A schematic cross-sectional view taken by line A-A' in the diagram.

[0037] Figure 9 It is along Figure 5 A schematic cross-sectional view taken by line B-B' in the diagram.

[0038] Figure 10 It is along Figure 6 A schematic cross-sectional view taken by line C-C' in the figure.

[0039] Figure 11 It is along Figure 6 A schematic cross-sectional view taken by line D-D' in the diagram.

[0040] Figure 12 This is a schematic cross-sectional view showing the first to third pixels according to an embodiment.

[0041] Figure 13 This is a schematic cross-sectional view of pixels according to an embodiment.

[0042] Figure 14 This is a schematic block diagram illustrating an electronic device including a display device according to an embodiment.

[0043] Figure 15 It is shown Figure 14 The diagram illustrates an example of an electronic device, such as a smartphone.

[0044] Figure 16 It is shown Figure 14 The electronic device is a schematic diagram of an example of a tablet computer. Detailed Implementation

[0045] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clearer from the embodiments described below in conjunction with the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. These embodiments are provided merely to improve this disclosure and to fully inform those skilled in the art of the scope of this disclosure. This disclosure is limited only by the scope of the appended claims.

[0046] The terminology used in this disclosure is for the purpose of describing embodiments and is not intended to be limiting. In this disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used in this disclosure, the terms “comprising” and / or “including” do not exclude the presence or addition of one or more other components, steps, operations, and / or elements in addition to those mentioned.

[0047] In addition, the term "connection" can include not only electrical connections but also physical connections, and can include direct connections as well as indirect connections through other components, or can include integral connections or non-integral connections.

[0048] The phrase "an element or layer disposed on another element or another layer" can mean that the element or layer can be directly disposed on another element or layer, and / or that the element or layer can be indirectly disposed on another element or layer through yet another element or another layer. Throughout the specification, the same reference numerals generally refer to similar elements.

[0049] Although the terms “first,” “second,” etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. Therefore, in the technical spirit of this disclosure, the first component discussed below may be the second component.

[0050] In the following description, embodiments will be described in more detail with reference to the accompanying drawings.

[0051] Figure 1 This is a schematic perspective view showing a light-emitting element according to an embodiment. Figure 2 This is a schematic cross-sectional view showing a light-emitting element according to an embodiment. Figure 1 and Figure 2 The illustration shows a light-emitting element (LD) with a columnar or columnar shape, but the type and / or shape of the light-emitting element (LD) is not limited to this.

[0052] refer to Figure 1 and Figure 2 The light-emitting element (LD) may include a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and / or an electrode layer 14.

[0053] The light-emitting element (LD) can be formed into a column shape extending in one direction. The LD can have a first end EP1 and a second end EP2. One of a first semiconductor layer 11 and a second semiconductor layer 13 can be disposed at the first end EP1 of the LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 can be disposed at the second end EP2 of the LD. For example, the first semiconductor layer 11 can be disposed at the first end EP1 of the LD, and the second semiconductor layer 13 can be disposed at the second end EP2 of the LD.

[0054] According to embodiments, the light-emitting element (LD) can be a light-emitting element manufactured into a columnar shape by etching methods or similar means. In this disclosure, the columnar shape can include a rod-shaped or strip-shaped shape with an aspect ratio greater than 1, such as a cylinder or a polygonal cylinder, and the shape of the cross-section is not limited.

[0055] Light-emitting elements (LDs) can have dimensions ranging from nanometers to micrometers. LDs can have a diameter (or width) and / or length (L) in the nanometer to micrometer range. For example, the diameter D of a LD can be 0.5 μm or less. The length L of a LD can be 10 μm or less. The length L of a LD can be 5 μm or less. However, the dimensions of a LD are not limited to these. The dimensions of a LD can vary depending on the design conditions of various devices (e.g., display devices) that use LDs as light sources.

[0056] The first semiconductor layer 11 may be a semiconductor layer of a first conductivity type. For example, the first semiconductor layer 11 may include a p-type semiconductor layer. For example, the first semiconductor layer 11 may include a p-type semiconductor layer containing at least one of InAlGaN, GaN, AlGaN, InGaN, and AlN and doped with a first conductivity type dopant such as Mg. However, the materials constituting (or forming) the first semiconductor layer 11 are not limited to these, and various other materials may constitute (or form) the first semiconductor layer 11.

[0057] An active layer 12 may be disposed between a first semiconductor layer 11 and a second semiconductor layer 13. The active layer 12 may include any of the following structures: a single-well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but the embodiments are not limited thereto. The active layer 12 may include GaN, InGaN, InAlGaN, AlGaN, AlN, or the like, and various other materials may constitute (or form) the active layer 12. When a voltage higher than a threshold voltage is applied to the ends (e.g., opposite ends) of the light-emitting element LD, electron-hole pairs can recombine in the active layer 12, and the light-emitting element LD can emit light. By controlling the light emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source for various light-emitting devices, including pixels of display devices.

[0058] The second semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. The second semiconductor layer 13 may include an n-type semiconductor layer. For example, the second semiconductor layer 13 may include an n-type semiconductor layer containing any one of InAlGaN, GaN, AlGaN, InGaN, and AlN and doped with a second conductivity type dopant such as Si, Ge, or Sn. However, the materials constituting (or forming) the second semiconductor layer 13 are not limited to these, and various other materials may constitute (or form) the second semiconductor layer 13.

[0059] Electrode layer 14 can be disposed on the first end EP1 and / or the second end EP2 of the light-emitting element LD. Figure 2 The example shown illustrates the formation of electrode layer 14 on the first semiconductor layer 11, but the embodiment is not limited to this. For example, a separate electrode layer may also be formed on the second semiconductor layer 13.

[0060] Electrode layer 14 may comprise a transparent metal or a transparent metal oxide. For example, electrode layer 14 may comprise at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc tin oxide (ZTO), but the embodiments are not limited thereto. When electrode layer 14 is made of a transparent metal or a transparent metal oxide, light generated in the active layer 12 of the light-emitting element LD can pass through electrode layer 14 and can be emitted to the outside of the light-emitting element LD.

[0061] An insulating film INF can be disposed on the surface of the light-emitting element LD. The insulating film INF can be disposed (e.g., directly disposed) on the surface of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the electrode layer 14. The insulating film INF can expose the first end EP1 and the second end EP2 of the light-emitting element LD, which have different polarities.

[0062] The insulating film INF prevents electrical short circuits that can occur when the active layer 12 comes into contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film INF can improve the lifespan and luminous efficiency of the light-emitting element (LD) by minimizing surface defects.

[0063] The insulating film INF may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) and titanium oxide (TiO) x At least one of the following. For example, the insulating film INF can be composed of a double layer, and the layers constituting (or forming) the double layer can include different materials. For example, the insulating film INF can be made of aluminum oxide (AlO2). x ) and silicon oxide (SiO) x The structure is a double layer made of [material name], but the embodiments are not limited to this. In another example, the insulating film INF can be omitted.

[0064] Light-emitting devices including the aforementioned light-emitting element (LD) can be used in various types of devices (including display devices) that require a light source. For example, a light-emitting element (LD) can be provided in each pixel of a display panel, and the LD can be used as the light source for each pixel. However, the application areas of the LD are not limited to the examples described above. For example, the LD can also be used in other types of devices that require a light source (such as lighting devices).

[0065] Figure 3 This is a schematic plan view illustrating a display device according to an embodiment.

[0066] Figure 3 Showing the use Figure 1 and Figure 2 The embodiments described herein are examples of electronic devices with light-emitting elements (LD) as light sources, and display devices, such as display panels (PNL) included in the display devices, are shown.

[0067] For ease of description, Figure 3 The structure of the display panel PNL is briefly shown with the display area DA as the center. However, according to an embodiment, at least one drive circuit unit (e.g., at least one of a scan driver and a data driver), lines, and / or pads may also be provided on the display panel PNL.

[0068] refer to Figure 3 The display panel PNL and the base layer BSL used to form the display panel PNL may include a display area DA for displaying images and a non-display area NDA, which is the area other than the display area DA. The display area DA may constitute (or form) a screen on which the image is displayed, and the non-display area NDA may be the remaining area other than the display area DA.

[0069] Pixel units PXU can be set in the display area DA. Pixel units PXU may include a first pixel PXL1, a second pixel PXL2, and / or a third pixel PXL3. Hereinafter, when at least one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is mentioned arbitrarily, or when two or more types of pixels are mentioned collectively, they may be referred to as "pixel PXL" or "multiple pixels PXL".

[0070] Pixel PXL can be based on things like stripes or The arrangement of pixels PXL is regular and follows a specific structure. However, the arrangement of pixels PXL is not limited to this, and pixels PXL can be arranged in the display area DA in various structures and / or methods.

[0071] According to an embodiment, two or more pixels PXL that emit light of different colors can be provided in the display area DA. For example, a first pixel PXL1 that emits light of a first color, a second pixel PXL2 that emits light of a second color, and a third pixel PXL3 that emits light of a third color can be arranged in the display area DA. At least one first pixel PXL1, second pixel PXL2, and third pixel PXL3 arranged adjacent to each other can form a pixel unit (e.g., a single pixel unit) PXU capable of emitting light of various colors. For example, each of the first pixel PXL1, second pixel PXL2, and third pixel PXL3 can be a pixel that emits light of a selected color. According to an embodiment, the first pixel PXL1 can be a red pixel that emits red light, the second pixel PXL2 can be a green pixel that emits green light, and the third pixel PXL3 can be a blue pixel that emits blue light, but the embodiment is not limited to this.

[0072] In one embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include light-emitting elements that emit light of the same color. For example, color conversion layers and / or color filter layers of different colors may be disposed on the light-emitting elements, so that light of the first, second, and third colors can be emitted respectively. In another embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include light-emitting elements of the first, second, and third colors as light sources, so that light of the first, second, and third colors can be emitted respectively. However, the color, type, and / or number of pixels PXL constituting (or forming) the pixel unit PXU are not limited. The color of the light emitted by each pixel PXL can be changed in various ways.

[0073] Pixel PXL may include at least one light source driven by selected control signals (e.g., scan signals and data signals) and / or selected power supplies (e.g., a first power supply and a second power supply). In embodiments, the light source may include, according to... Figure 1 and Figure 2 At least one light-emitting element (LD) in any of the embodiments, for example, an ultra-small columnar light-emitting element LD with a size as small as nanometers to micrometers. However, the embodiments are not limited to this, and various types of light-emitting elements (LDs) can be used as the light source for the pixel PXL.

[0074] In this embodiment, each pixel PXL may be composed of an active pixel. However, the type, structure, and / or driving method of the pixel PXL suitable for the display device are not limited. For example, each pixel PXL may constitute (or form) a pixel of a passive or active light-emitting display device having various structures and / or driving methods.

[0075] Figure 4This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0076] Figure 4 The pixel PXL shown in the image can be Figure 3 The display panel PNL includes any one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have substantially the same or similar structures.

[0077] refer to Figure 4 The pixel PXL may also include an emissive unit EMU for generating light with brightness corresponding to the data signal and a pixel circuit PXC for driving the emissive unit EMU.

[0078] The pixel circuit PXC can be connected between the first power supply VDD and the transmitter unit EMU. The pixel circuit PXC can be connected to the scan line SL and data line DL of the corresponding pixel PXL, and can control the operation of the transmitter unit EMU in response to the scan signals and data signals provided from the scan line SL and data line DL. The pixel circuit PXC can also be selectively connected to the sensing signal line SSL and the sensing line SENL.

[0079] A pixel circuit (PXC) may include at least one transistor and a capacitor. For example, a pixel circuit (PXC) may include a first transistor M1, a second transistor M2, a third transistor M3, and a storage capacitor Cst.

[0080] The first transistor M1 can be connected between the first power supply VDD and the first connection electrode ELT1. The gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the drive current supplied to the transmitter unit EMU in response to the voltage of the first node N1. The first transistor M1 can be a drive transistor that controls the drive current of the pixel PXL.

[0081] In an embodiment, the first transistor M1 may optionally include a lower conductive layer BML (also referred to as a "lower electrode," "back gate electrode," or "lower light-blocking layer"). The gate electrode of the first transistor M1 and the lower conductive layer BML may overlap each other, and an insulating layer is interposed between the gate electrode and the lower conductive layer BML. In an embodiment, the lower conductive layer BML may be connected to an electrode of the first transistor M1, such as a source electrode or a drain electrode.

[0082] When the first transistor M1 includes a lower conductive layer BML, a back-biasing technique (or synchronization technique) can be applied to shift the threshold voltage of the first transistor M1 in the negative or positive direction by applying a back-bias voltage to the lower conductive layer BML. For example, the threshold voltage of the first transistor M1 can be shifted in the negative or positive direction by applying a source-sink technique in which the lower conductive layer BML is connected to the source electrode of the first transistor M1. When the lower conductive layer BML is disposed below the semiconductor pattern that forms (or constitutes) the channel of the first transistor M1, the lower conductive layer BML can act as a light-blocking pattern and can stabilize the operating characteristics of the first transistor M1. However, the function and / or usage of the lower conductive layer BML are not limited to this.

[0083] The second transistor M2 can be connected between the data line DL and the first node N1. For example, the gate electrode of the second transistor M2 can be connected to the scan line SL. When a scan signal with a turn-on voltage (e.g., a high-level voltage) is provided from the scan line SL, the second transistor M2 can be turned on to connect the data line DL and the first node N1.

[0084] For each frame period, the data signal of the corresponding frame can be provided to the data line DL. With a scan signal providing a conduction voltage, the data signal can be transmitted to the first node N1 via the conducting second transistor M2. The second transistor M2 can be a switching transistor used to transmit each data signal to the inside of pixel PXL.

[0085] One electrode of the storage capacitor Cst can be connected to the first node N1, and the other electrode of the storage capacitor Cst can be connected to the second electrode of the first transistor M1. The storage capacitor Cst can be charged during each frame period using the voltage corresponding to the data signal provided to the first node N1.

[0086] A third transistor M3 can be connected between the first connection electrode ELT1 (or the second electrode of the first transistor M1) and the sensing line SENL. The gate electrode of the third transistor M3 can be connected to the sensing signal line SSL. The third transistor M3 can transmit the voltage value applied to the first connection electrode ELT1 to the sensing line SENL according to the sensing signal provided to the sensing signal line SSL. The voltage value transmitted through the sensing line SENL can be transmitted to external circuitry (e.g., a timing controller). The external circuitry can extract characteristic information (e.g., the threshold voltage of the first transistor M1, etc.) of each pixel PXL based on the provided voltage value. The extracted characteristic information can be used to transform image data so that characteristic deviations between pixels PXL can be compensated.

[0087] exist Figure 4In this embodiment, all transistors included in the pixel circuit PXC are shown as n-type transistors, but the embodiment is not limited to this. For example, at least one of the first transistor M1, the second transistor M2, and the third transistor M3 can be modified to be a p-type transistor.

[0088] The structure and driving method of the pixel PXL can be changed in various ways. For example, besides Figure 4 In addition to the embodiments shown, the pixel circuit PXC can be composed of pixel circuits having various structures and / or driving methods.

[0089] For example, the pixel circuit PXC may not include the third transistor M3. The pixel circuit PXC may also include other circuit elements, such as a compensation transistor for compensating the threshold voltage of the first transistor M1, an initialization transistor for initializing the voltage of the first node N1 and / or the first connection electrode ELT1, an emitter control transistor for controlling the period during which drive current is supplied to the emitter unit EMU, and / or a boost capacitor for increasing the voltage of the first node N1.

[0090] The transmitting unit (EMU) may include at least one light-emitting element (LD), for example, a light-emitting element (LD) connected between a first power supply (VDD) and a second power supply (VSS).

[0091] For example, the EMU may include a first connection electrode ELT1 connected to a first power supply VDD via a pixel circuit PXC and a first power line PL1, a fifth connection electrode ELT5 connected to a second power supply VSS via a second power line PL2, and a light-emitting element LD connected between the first connection electrode ELT1 and the fifth connection electrode ELT5.

[0092] The first power supply VDD and the second power supply VSS can have different potentials, allowing the light-emitting element (LD) to emit light. For example, the first power supply VDD can be set to a high potential, and the second power supply VSS can be set to a low potential.

[0093] In an embodiment, the emitting unit (EMU) may include at least one series stage. Each series stage may include a pair of electrodes (e.g., two electrodes) and at least one light-emitting element (LD) connected between the pair of electrodes in a forward bias direction. For example, the number of series stages constituting (or forming) the emitting unit (EMU) and the number of light-emitting elements (LDs) constituting (or forming) each series stage are not limited. For example, the number of light-emitting elements (LDs) constituting (or forming) each series stage may be the same or different, and the number of light-emitting elements (LDs) is not limited.

[0094] For example, the transmitting unit (EMU) may include a first series stage containing at least one first light-emitting element (LD1), a second series stage containing at least one second light-emitting element (LD2), a third series stage containing at least one third light-emitting element (LD3), and a fourth series stage containing at least one fourth light-emitting element (LD4).

[0095] The first series stage may include a first connecting electrode ELT1, a second connecting electrode ELT2, and at least one first light-emitting element LD1 connected between the first connecting electrode ELT1 and the second connecting electrode ELT2. The first light-emitting element LD1 may be connected between the first connecting electrode ELT1 and the second connecting electrode ELT2 in a forward bias direction. For example, a first end EP1 of the first light-emitting element LD1 may be connected to the first connecting electrode ELT1, and a second end EP2 of the first light-emitting element LD1 may be connected to the second connecting electrode ELT2.

[0096] The second series stage may include a second connecting electrode ELT2, a third connecting electrode ELT3, and at least one second light-emitting element LD2 connected between the second connecting electrode ELT2 and the third connecting electrode ELT3. The second light-emitting element LD2 may be connected between the second connecting electrode ELT2 and the third connecting electrode ELT3 in a forward bias direction. For example, a first end EP1 of the second light-emitting element LD2 may be connected to the second connecting electrode ELT2, and a second end EP2 of the second light-emitting element LD2 may be connected to the third connecting electrode ELT3.

[0097] The third series stage may include a third connecting electrode ELT3, a fourth connecting electrode ELT4, and at least one third light-emitting element LD3 connected between the third connecting electrode ELT3 and the fourth connecting electrode ELT4. The third light-emitting element LD3 may be connected between the third connecting electrode ELT3 and the fourth connecting electrode ELT4 in a forward bias direction. For example, a first end EP1 of the third light-emitting element LD3 may be connected to the third connecting electrode ELT3, and a second end EP2 of the third light-emitting element LD3 may be connected to the fourth connecting electrode ELT4.

[0098] The fourth series stage may include a fourth connecting electrode ELT4, a fifth connecting electrode ELT5, and at least one fourth light-emitting element LD4 connected between the fourth connecting electrode ELT4 and the fifth connecting electrode ELT5. The fourth light-emitting element LD4 may be connected between the fourth connecting electrode ELT4 and the fifth connecting electrode ELT5 in a forward bias direction. For example, a first end EP1 of the fourth light-emitting element LD4 may be connected to the fourth connecting electrode ELT4, and a second end EP2 of the fourth light-emitting element LD4 may be connected to the fifth connecting electrode ELT5.

[0099] The first electrode of the transmitting unit EMU (e.g., the first connecting electrode ELT1) can be the anode of the transmitting unit EMU. The last electrode of the transmitting unit EMU (e.g., the fifth connecting electrode ELT5) can be the cathode of the transmitting unit EMU.

[0100] The remaining electrodes of the transmitting unit (EMU) (e.g., the second connecting electrode ELT2, the third connecting electrode ELT3, and / or the fourth connecting electrode ELT4) can constitute (or form) intermediate electrodes. For example, the second connecting electrode ELT2 can constitute (or form) the first intermediate electrode IET1, the third connecting electrode ELT3 can constitute (or form) the second intermediate electrode IET2, and the fourth connecting electrode ELT4 can constitute (or form) the third intermediate electrode IET3.

[0101] When light-emitting elements (LDs) are connected in a series / parallel configuration, power efficiency can be improved compared to when the same number of LDs are connected only in parallel. In a pixel PXL with LDs connected in a series / parallel configuration, even if a short-circuit defect occurs in some of the series stages, a certain brightness can still be characterized by the remaining LDs in the series stages. Therefore, the possibility of dark spot defects in the pixel PXL can be reduced. However, the embodiments are not limited to this, and the emission unit EMU can be formed by connecting only the LDs in series, or the emission unit EMU can be formed by connecting only the LDs in parallel.

[0102] Each of the light-emitting elements (LDs) may include a first end EP1 (e.g., a p-type end) connected to a first power supply VDD via at least one electrode (e.g., a first connecting electrode ELT1), a pixel circuit PXC, and / or a first power line PL1, and a second end EP2 (e.g., an n-type end) connected to a second power supply VSS via at least one other electrode (e.g., a fifth connecting electrode ELT5) and a second power line PL2. The LDs may be connected in a forward bias direction between the first power supply VDD and the second power supply VSS. LDs connected in a forward bias direction can constitute (or form) an effective light source for an emission unit (EMU).

[0103] When a drive current is provided through the corresponding pixel circuit (PXC), the light-emitting element (LD) can emit light with a brightness corresponding to the drive current. For example, during each frame period, the pixel circuit (PXC) can provide a drive current to the emission unit (EMU) corresponding to the grayscale value to be represented in the frame. Therefore, when the light-emitting element (LD) emits light with a brightness corresponding to the drive current, the emission unit (EMU) can represent the brightness corresponding to the drive current.

[0104] Figure 5 and Figure 6This is a schematic plan view showing pixels according to an embodiment. Figure 7 This is a schematic plan view used to explain the arrangement of the light-emitting elements according to the embodiments. Figure 8 It is along Figure 5 A schematic cross-sectional view taken by line A-A' in the diagram. Figure 9 It is along Figure 5 The sectional view taken by line B-B' in the figure. Figure 10 It is along Figure 6 A schematic cross-sectional view taken by line C-C' in the figure. Figure 11 It is along Figure 6 A schematic cross-sectional view taken by line D-D' in the diagram.

[0105] For example, Figure 5 and Figure 6 Showing the composition (or formation) Figure 3 The pixel unit PXU is one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have substantially the same or similar structures. Figure 5 and Figure 6 Each pixel PXL includes, as shown Figure 4 The embodiment shown depicts light-emitting elements (LDs) arranged in four cascade stages. However, the number of cascade stages for each pixel PXL can vary depending on the embodiment.

[0106] Hereinafter, when referring to one or more of the first light-emitting element LD1, the second light-emitting element LD2, the third light-emitting element LD3, and the fourth light-emitting element LD4, or when referring generally to two or more types of light-emitting elements, they may be referred to as "light-emitting element LD" or "multiple light-emitting elements LD". When referring to at least one of the electrodes including the first electrode ALE1, the second electrode ALE2, and the third electrode ALE3, they may be referred to as "electrode ALE" or "multiple electrodes ALE". When referring to at least one of the electrodes including the first connecting electrode ELT1, the second connecting electrode ELT2, the third connecting electrode ELT3, the fourth connecting electrode ELT4, and the fifth connecting electrode ELT5, they may be referred to as "connecting electrode ELT" or "multiple connecting electrodes ELT".

[0107] refer to Figure 5 and Figure 6Pixel PXL may include an emitting region EA and a non-emitting region NEA. The emitting region EA may include a light-emitting element LD and may be a region capable of emitting light. The non-emitting region NEA may be configured to surround the emitting region EA. The non-emitting region NEA may be a region in which a first embankment BNK1 is configured to surround the emitting region EA. The first embankment BNK1 may be configured in the non-emitting region NEA and to at least partially surround the emitting region EA.

[0108] The first dam BNK1 may include an opening that overlaps with the emission region EA. The opening of the first dam BNK1 can provide space for providing (or setting) the light-emitting element LD in the step (or process) of providing the light-emitting element LD to the pixel PXL. For example, light-emitting element ink of a desired type and / or amount can be provided to the space defined by the opening of the first dam BNK1.

[0109] The first layer BNK1 may include organic materials such as acrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, polyester resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). However, the embodiments are not limited thereto, and the first layer BNK1 may include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0110] According to an embodiment, the first dam BNK1 may include at least one light-blocking material and / or a reflective material. Therefore, light leakage between adjacent pixels PXL can be prevented. For example, the first dam BNK1 may include at least one black pigment.

[0111] The second dam BNK2 may include an opening that overlaps with the emission region EA. This opening in the second dam BNK2 may provide space for a color conversion layer, which will be described later. For example, a color conversion layer of the desired type and / or amount may be provided in the space defined by the opening in the second dam BNK2.

[0112] The second layer BNK2 may include organic materials such as acrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, polyester resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). However, the embodiments are not limited thereto, and the second layer BNK2 may include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0113] According to an embodiment, the second dam BNK2 may include at least one light-blocking and / or reflective material. Therefore, light leakage between adjacent pixels PXL can be prevented. For example, the second dam BNK2 may include at least one black pigment.

[0114] Pixel PXL may include wall (or partition wall) WL, electrode ALE, light-emitting element LD and / or connecting electrode ELT.

[0115] Walls WL may overlap with emission regions EA and may be spaced apart from each other. Walls WL may be arranged at least partially in non-emission regions NEA. Walls WL may extend in a second direction (e.g., the Y-axis direction) and may be spaced apart from each other in a first direction (e.g., the X-axis direction).

[0116] Each of the wall walls (WL) can partially overlap with at least one electrode (ALE) in the emission region (EA). For example, the wall wall (WL) can be positioned below the electrode (ALE). Since the wall wall (WL) is positioned below a portion of the electrode (ALE), the portion of the electrode (ALE) can protrude towards the top of the pixel (PXL) in the region forming the wall wall (WL), for example, in a third direction (e.g., the Z-axis direction). If the wall wall (WL) and / or the electrode (ALE) include a reflective material, a reflective wall structure can be formed around the light-emitting element (LD). Therefore, light emitted from the light-emitting element (LD) can be emitted towards the top of the pixel (PXL) (e.g., in the forward direction of the display panel PNL, encompassing a selected viewing angle range). This can improve the light output efficiency of the display panel PNL.

[0117] Electrodes ALE may be disposed at least in the emission region EA. Electrodes ALE may extend in a second direction (e.g., the Y-axis direction) and may be spaced apart from each other in a first direction (e.g., the X-axis direction).

[0118] The first electrode ALE1, the second electrode ALE2, and the third electrode ALE3 may extend in a second direction (e.g., the Y-axis direction) and may be arranged sequentially and spaced apart from each other in a first direction (e.g., the X-axis direction). Some of the electrodes ALEs may be connected to the pixel circuit PXC (Pixel Pixel Array) via contact holes. Figure 4 (as shown in the diagram) and / or selected power lines. For example, the first electrode ALE1 can be connected to the pixel circuit PXC and / or the first power line PL1 through a contact hole, and the second electrode ALE2 can be connected to the second power line PL2 through a contact hole.

[0119] According to an embodiment, some of the electrodes ALE can be electrically connected to some of the connecting electrodes ELT through contact holes. For example, the first electrode ALE1 can be electrically connected to the first connecting electrode ELT1 through contact holes, and the second electrode ALE2 can be electrically connected to the fifth connecting electrode ELT5 through contact holes.

[0120] A pair of adjacent electrodes ALE can receive different signals during the alignment step (or process) of the light-emitting element LD. For example, when the first electrode ALE1, the second electrode ALE2, and the third electrode ALE3 are arranged sequentially in a first direction (e.g., the X-axis direction), the first electrode ALE1 and the second electrode ALE2 can receive different alignment signals, and the second electrode ALE2 and the third electrode ALE3 can receive different alignment signals.

[0121] Each of the light-emitting elements (LDs) can be aligned between a pair of electrodes ALE in the emission region EA. Each of the light-emitting elements (LDs) can be electrically connected between a pair of connecting electrodes ELT.

[0122] The first light-emitting element LD1 can be aligned between the first electrode ALE1 and the second electrode ALE2. The first light-emitting element LD1 can be electrically connected between the first connecting electrode ELT1 and the second connecting electrode ELT2. For example, the first light-emitting element LD1 can be aligned in a first region (e.g., the upper region) of the first electrode ALE1 and the second electrode ALE2, the first end EP1 of the first light-emitting element LD1 can be electrically connected to the first connecting electrode ELT1, and the second end EP2 of the first light-emitting element LD1 can be electrically connected to the second connecting electrode ELT2.

[0123] The second light-emitting element LD2 can be aligned between the first electrode ALE1 and the second electrode ALE2. The second light-emitting element LD2 can be electrically connected between the second connecting electrode ELT2 and the third connecting electrode ELT3. For example, the second light-emitting element LD2 can be aligned in the second region (e.g., the lower region) of the first electrode ALE1 and the second electrode ALE2, the first end EP1 of the second light-emitting element LD2 can be electrically connected to the second connecting electrode ELT2, and the second end EP2 of the second light-emitting element LD2 can be electrically connected to the third connecting electrode ELT3.

[0124] The third light-emitting element LD3 can be aligned between the second electrode ALE2 and the third electrode ALE3. The third light-emitting element LD3 can be electrically connected between the third connecting electrode ELT3 and the fourth connecting electrode ELT4. For example, the third light-emitting element LD3 can be aligned in the second region (e.g., the lower region) of the second electrode ALE2 and the third electrode ALE3, the first end EP1 of the third light-emitting element LD3 can be electrically connected to the third connecting electrode ELT3, and the second end EP2 of the third light-emitting element LD3 can be electrically connected to the fourth connecting electrode ELT4.

[0125] The fourth light-emitting element LD4 can be aligned between the second electrode ALE2 and the third electrode ALE3. The fourth light-emitting element LD4 can be electrically connected between the fourth connecting electrode ELT4 and the fifth connecting electrode ELT5. For example, the fourth light-emitting element LD4 can be aligned in a first region (e.g., the upper region) of the second electrode ALE2 and the third electrode ALE3, the first end EP1 of the fourth light-emitting element LD4 can be electrically connected to the fourth connecting electrode ELT4, and the second end EP2 of the fourth light-emitting element LD4 can be electrically connected to the fifth connecting electrode ELT5.

[0126] For example, the first light-emitting element LD1 can be positioned or disposed in the upper left region of the emission region EA, and the second light-emitting element LD2 can be positioned or disposed in the lower left region of the emission region EA. The third light-emitting element LD3 can be positioned or disposed in the lower right region of the emission region EA, and the fourth light-emitting element LD4 can be positioned or disposed in the upper right region of the emission region EA. However, the arrangement and / or connection structure of the light-emitting elements LD can vary depending on the structure of the emission unit EMU and / or the number of series stages.

[0127] Each of the connecting electrodes ELTs can be disposed in the emission region EA and can be configured to overlap with at least one electrode ALE and / or light-emitting element LD. For example, the connecting electrode ELT can be formed on the electrode ALE and / or light-emitting element LD to overlap with the electrode ALE and / or light-emitting element LD, and can be electrically connected to the light-emitting element LD.

[0128] The first connecting electrode ELT1 can be disposed on the portion of the first electrode ALE1 corresponding to the first region (e.g., the upper region) and on the first end EP1 of the first light-emitting element LD1, and is electrically connected to the first end EP1 of the first light-emitting element LD1.

[0129] The second connecting electrode ELT2 can be disposed on the portion of the second electrode ALE2 corresponding to the first region (e.g., the upper region) and on the second end EP2 of the first light-emitting element LD1, and electrically connected to the second end EP2 of the first light-emitting element LD1. The second connecting electrode ELT2 can also be disposed on the portion of the first electrode ALE1 corresponding to the second region (e.g., the lower region) and on the first end EP1 of the second light-emitting element LD2, and electrically connected to the first end EP1 of the second light-emitting element LD2. For example, the second connecting electrode ELT2 can electrically connect the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2 in the emission region EA. For example, the second connecting electrode ELT2 can have a curved shape. For example, the second connecting electrode ELT2 can have a structure that is bent or twisted at the boundary between the region where at least one first light-emitting element LD1 is disposed and the region where at least one second light-emitting element LD2 is disposed.

[0130] The third connecting electrode ELT3 can be disposed on the portion of the second electrode ALE2 corresponding to the second region (e.g., the lower region) and on the second end EP2 of the second light-emitting element LD2, and electrically connected to the second end EP2 of the second light-emitting element LD2. The third connecting electrode ELT3 can also be disposed on the portion of the third electrode ALE3 corresponding to the second region (e.g., the lower region) and on the first end EP1 of the third light-emitting element LD3, and electrically connected to the first end EP1 of the third light-emitting element LD3. For example, the third connecting electrode ELT3 can electrically connect the second end EP2 of the second light-emitting element LD2 and the first end EP1 of the third light-emitting element LD3 in the emission region EA. For example, the third connecting electrode ELT3 can have a curved shape. For example, the third connecting electrode ELT3 can have a structure that is bent or twisted at the boundary between the region where at least one second light-emitting element LD2 is arranged and the region where at least one third light-emitting element LD3 is arranged.

[0131] The fourth connecting electrode ELT4 can be disposed on the portion of the second electrode ALE2 corresponding to the second region (e.g., the lower region) and on the second end EP2 of the third light-emitting element LD3, and is electrically connected to the second end EP2 of the third light-emitting element LD3. The fourth connecting electrode ELT4 can also be disposed on the portion of the third electrode ALE3 corresponding to the first region (e.g., the upper region) and on the first end EP1 of the fourth light-emitting element LD4, and is electrically connected to the first end EP1 of the fourth light-emitting element LD4. For example, the fourth connecting electrode ELT4 can electrically connect the second end EP2 of the third light-emitting element LD3 and the first end EP1 of the fourth light-emitting element LD4 in the emission region EA. For example, the fourth connecting electrode ELT4 can have a curved shape. For example, the fourth connecting electrode ELT4 can have a structure that is bent or folded at the boundary between the region where at least one third light-emitting element LD3 is arranged and the region where at least one fourth light-emitting element LD4 is arranged.

[0132] The fifth connecting electrode ELT5 can be disposed on the portion of the second electrode ALE2 corresponding to the first region (e.g., the upper region) and on the second end EP2 of the fourth light-emitting element LD4, and is electrically connected to the second end EP2 of the fourth light-emitting element LD4.

[0133] The first connecting electrode ELT1, the third connecting electrode ELT3, and / or the fifth connecting electrode ELT5 can be made of the same conductive layer. The second connecting electrode ELT2 and the fourth connecting electrode ELT4 can also be made of the same conductive layer. For example, as... Figure 9 As shown, the connecting electrodes ELT can be composed of a conductive layer. The first connecting electrode ELT1, the third connecting electrode ELT3, and / or the fifth connecting electrode ELT5 can be made of the first conductive layer, and the second connecting electrode ELT2 and the fourth connecting electrode ELT4 can be made of a second conductive layer different from the first conductive layer. In another example, as... Figure 10 As shown, the first connecting electrode ELT1, the second connecting electrode ELT2, the third connecting electrode ELT3, the fourth connecting electrode ELT4, and the fifth connecting electrode ELT5 can be made of the same conductive layer.

[0134] As described above, the connecting electrode ELT can be used to connect the light-emitting elements LD aligned between the electrodes ALE in a desired manner. For example, the connecting electrode ELT can be used to connect the first light-emitting element LD1, the second light-emitting element LD2, the third light-emitting element LD3, and the fourth light-emitting element LD4 in series sequentially.

[0135] refer to Figure 7 In the diameter D of the light-emitting element LD ( Figure 1When α is shown, the maximum distance B between the light-emitting elements LD in the second direction (e.g., the Y-axis direction) can be 25α or less. When the maximum distance B between the light-emitting elements LD in the second direction (e.g., the Y-axis direction) exceeds 25α, brightness dispersion may occur within each pixel PXL and between the first pixel PXL1, the second pixel PXL2, and / or the third pixel PXL3. For example, when the diameter D of the light-emitting element LD is approximately 0.5 μm, the maximum distance B between the light-emitting elements LD in the second direction (e.g., the Y-axis direction) can be 12.5 μm or less. In an embodiment, the maximum distance B between the light-emitting elements LD in the second direction (e.g., the Y-axis direction) can be 4 μm or greater. When the maximum distance B between the light-emitting elements LD in the second direction (e.g., the Y-axis direction) is less than 4 μm, the light-emitting elements LD may cluster together.

[0136] In the second direction (e.g., the Y-axis direction), the maximum distance between the light-emitting element LD closest to the first dam BNK1 and the first dam BNK1 can be 12.5α or less. In an embodiment, the first dam BNK1 may include a first extension E1 and a second extension E2. The first extension E1 and the second extension E2 may extend in the first direction (e.g., the X-axis direction) and may be spaced apart from each other in the second direction (e.g., the Y-axis direction).

[0137] In the second direction (e.g., the Y-axis direction), the maximum distance A between the light-emitting element LD closest to the first extension E1 and the first extension E1 can be 12.5α or less. If the maximum distance A between the light-emitting element LD closest to the first extension E1 and the first extension E1 in the second direction (e.g., the Y-axis direction) exceeds 12.5α, brightness dispersion may occur within each pixel PXL and between the first pixel PXL1, the second pixel PXL2, and / or the third pixel PXL3. For example, when the diameter D of the light-emitting element LD is approximately 0.5 μm, the maximum distance A between the light-emitting element LD closest to the first extension E1 and the first extension E1 in the second direction (e.g., the Y-axis direction) can be 6.3 μm or less.

[0138] In the second direction (e.g., the Y-axis direction), the maximum distance C between the light-emitting element LD closest to the second extension E2 and the second extension E2 can be the same as the maximum distance A between the light-emitting element LD closest to the first extension E1 and the first extension E1 in the second direction (e.g., the Y-axis direction). For example, the maximum distance C between the light-emitting element LD closest to the second extension E2 and the second extension E2 in the second direction (e.g., the Y-axis direction) can be 12.5α or less. When the maximum distance C between the light-emitting element LD closest to the second extension E2 and the second extension E2 in the second direction (e.g., the Y-axis direction) exceeds 12.5α, brightness dispersion may occur within each pixel PXL and between the first pixel PXL1, the second pixel PXL2, and / or the third pixel PXL3. When the diameter D of the light-emitting element LD is about 0.5 μm, the maximum distance C between the light-emitting element LD closest to the second extension E2 in the second direction (e.g., the Y-axis direction) and the second extension E2 can be 6.3 μm or less.

[0139] The maximum number of light-emitting elements (LDs) set in the emission region EA can satisfy the following formula 1.

[0140] 2γ+nα+(n-1)β=δ

[0141] Wherein, α can be the diameter D of the light-emitting element LD, β can be the maximum distance B between the light-emitting elements LD in the second direction (e.g., the Y-axis direction), γ can be the maximum distance between the light-emitting element LD closest to the first dam BNK1 and the first dam BNK1 in the second direction (e.g., the Y-axis direction), n can be the maximum number of light-emitting elements LD disposed in the emission region EA, and δ can be the length E of the emission region EA in the second direction (e.g., the Y-axis direction).

[0142] As described above, α can be 0.5 μm or smaller, and β can be 25α or smaller. When β exceeds 25α, as described above, brightness dispersion may occur within each pixel PXL and between the first pixel PXL1, the second pixel PXL2, and / or the third pixel PXL3. γ can be 12.5α or smaller. When γ exceeds 12.5α, as described above, brightness dispersion may occur within each pixel PXL and between the first pixel PXL1, the second pixel PXL2, and / or the third pixel PXL3. δ can be determined based on the resolution of the display device.

[0143] According to the above embodiments, by deriving the maximum distance B between light-emitting elements (LDs) that can minimize the brightness dispersion of pixel PXL and the maximum number of light-emitting elements (LDs), the display quality and reliability of the display device can be improved.

[0144] The following will refer to Figures 8 to 11 Describe the cross-sectional structure of pixel PXL in detail. Figures 8 to 11 This illustrates the PXC (pixel circuit) that constitutes (or forms) the pixel circuit. Figure 4 The first transistor M1 is shown among the various circuit elements (as illustrated). Unless it is necessary to separately identify the first transistor M1, the second transistor M2, and the third transistor M3, they will be collectively referred to as "transistor M". For example, the structure and / or location of each layer of transistor M are not limited to... Figure 8 and Figure 10 The embodiments shown are examples, and variations may be made based on these embodiments.

[0145] According to an embodiment, the pixel PXL may include circuit elements including a transistor M disposed on the base layer BSL and various wiring connected thereto. Electrodes ALE, light-emitting elements LD, connecting electrodes ELT, first dam BNK1 and / or second dam BNK2 constituting (or forming) the emitting unit EMU may be disposed on the circuit elements.

[0146] The base layer (BSL) can constitute (or form) a base component and can be a rigid or flexible substrate or a rigid or flexible film. For example, the base layer (BSL) can be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal, or at least one insulating layer. The material and / or physical properties of the base layer (BSL) are not limited. In embodiments, the base layer (BSL) can be substantially transparent. For example, the term "substantially transparent" may mean that light can be transmitted at a higher transmittance than selected. In other embodiments, the base layer (BSL) can be translucent or opaque. According to embodiments, the base layer (BSL) may include a reflective material.

[0147] The lower conductive layer BML and the first power conductive layer PL2a can be disposed on the base layer BSL. The lower conductive layer BML and the first power conductive layer PL2a can be disposed on the same layer. For example, the lower conductive layer BML and the first power conductive layer PL2a can be formed simultaneously in the same process, or can be formed from the same material, but the embodiments are not limited thereto. The first power conductive layer PL2a can constitute (or form) a reference layer. Figure 4 The second power supply line PL2 is described in the following description.

[0148] Each of the lower conductive layer BML and the first power conductive layer PL2a may consist of a single layer or multiple layers made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and their oxides or alloys.

[0149] A buffer layer BFL can be disposed on the lower conductive layer BML and the first power conductive layer PL2a. The buffer layer BFL can prevent impurities from diffusing (or penetrating) into the circuit elements. The buffer layer BFL can be composed of a single layer, or it can be composed of multiple layers (double or more layers). When the buffer layer BFL is formed of multiple layers, each layer can be formed of the same material, or it can be formed of different materials.

[0150] A semiconductor pattern SCP can be formed on the buffer layer BFL. For example, the semiconductor pattern SCP may include a first region in contact with a first transistor electrode TE1, a second region in contact with a second transistor electrode TE2, and a channel region positioned or disposed between the first and second regions. According to an embodiment, one of the first and second regions may be a source region, and the other of the first and second regions may be a drain region.

[0151] According to an embodiment, the semiconductor pattern SCP can be made of polycrystalline silicon, amorphous silicon, oxide semiconductor, or the like. The channel region of the semiconductor pattern SCP can be an undoped semiconductor pattern and can be an intrinsic semiconductor. The first and second regions of the semiconductor pattern SCP can be semiconductors doped with selected impurities.

[0152] A gate insulating layer GI can be disposed on the buffer layer BFL and the semiconductor pattern SCP. For example, the gate insulating layer GI can be disposed between the semiconductor pattern SCP and the gate electrode GE. The gate insulating layer GI can be disposed between the buffer layer BFL and the second power supply conductive layer PL2b. The gate insulating layer GI can be composed of a single layer or multiple layers and can include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0153] The gate electrode GE and the second power conductive layer PL2b of transistor M can be disposed on the gate insulating layer GI. The gate electrode GE and the second power conductive layer PL2b can be disposed on the same layer. For example, the gate electrode GE and the second power conductive layer PL2b can be formed simultaneously in the same process, or they can be formed from the same material, but the embodiments are not limited thereto. The gate electrode GE can overlap with the semiconductor pattern SCP in a third direction (e.g., the Z-axis direction) on the gate insulating layer GI. The second power conductive layer PL2b can overlap with the first power conductive layer PL2a in a third direction (e.g., the Z-axis direction) on the gate insulating layer GI. The second power conductive layer PL2b and the first power conductive layer PL2a can together form a reference. Figure 4 The second power supply line PL2 as described above.

[0154] Each of the gate electrode GE and the second power conductive layer PL2b can consist of a single layer or multiple layers made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), their oxides or alloys. For example, each of the gate electrode GE and the second power conductive layer PL2b can consist of multiple layers of titanium (Ti), copper (Cu), and / or indium tin oxide (ITO) stacked sequentially or repeatedly.

[0155] An interlayer insulating layer (ILD) can be disposed on the gate electrode GE and the second power conductive layer PL2b. For example, the ILD can be disposed between the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2. The ILD can also be disposed between the second power conductive layer PL2b and the third power conductive layer PL2c.

[0156] Interlayer insulating layers (ILDs) can consist of a single layer or multiple layers and can include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0157] The first transistor electrode TE1, the second transistor electrode TE2, and the third power conductive layer PL2c of transistor M can be disposed on the interlayer insulating layer (ILD). The first transistor electrode TE1, the second transistor electrode TE2, and the third power conductive layer PL2c can be disposed on the same layer. For example, the first transistor electrode TE1, the second transistor electrode TE2, and the third power conductive layer PL2c can be formed simultaneously in the same process, or can be formed from the same material, but the embodiments are not limited thereto.

[0158] The first transistor electrode TE1 and the second transistor electrode TE2 may overlap with the semiconductor pattern SCP in a third direction (e.g., the Z-axis direction). The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to the semiconductor pattern SCP. For example, the first transistor electrode TE1 may be electrically connected to a first region of the semiconductor pattern SCP through a contact hole penetrating the interlayer insulating layer (ILD). The first transistor electrode TE1 may also be electrically connected to the lower conductive layer (BML) through a contact hole penetrating the ILD and the buffer layer (BFL). The second transistor electrode TE2 may be electrically connected to a second region of the semiconductor pattern SCP through a contact hole penetrating the ILD. According to an embodiment, one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0159] The third power conductive layer PL2c may overlap with the first power conductive layer PL2a and / or the second power conductive layer PL2b in a third direction (e.g., the Z-axis direction). The third power conductive layer PL2c may be electrically connected to the first power conductive layer PL2a and / or the second power conductive layer PL2b. For example, the third power conductive layer PL2c may be electrically connected to the first power conductive layer PL2a through contact holes penetrating the interlayer insulating layer (ILD) and the buffer layer (BFL). The third power conductive layer PL2c may be electrically connected to the second power conductive layer PL2b through contact holes penetrating the interlayer insulating layer (ILD). The third power conductive layer PL2c may form a reference together with the first power conductive layer PL2a and / or the second power conductive layer PL2b. Figure 4 The second power supply line PL2 is described in the following description.

[0160] The first transistor electrode TE1, the second transistor electrode TE2, and the third power conductive layer PL2c can be composed of a single layer or multiple layers of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), their oxides or alloys.

[0161] A passivation layer PSV can be disposed on the first transistor electrode TE1, the second transistor electrode TE2, and the third power conductive layer PL2c. The passivation layer PSV can consist of a single layer or multiple layers and can include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0162] A via layer (VIA) can be formed on the passivation layer PSV. The via layer VIA can be made of an organic material to flatten the step difference beneath it. For example, the via layer VIA can include organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiments are not limited thereto, and the via layer VIA can include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0163] Walls (WLs) can be set on the via layer (VIA). The wall (WL) can form a selected step difference, allowing the light-emitting element (LD) to be easily aligned in the emission region (EA).

[0164] The wall WL can have various shapes depending on the embodiment. In one embodiment, the wall WL can have a shape that protrudes from the base layer BSL in a third direction (e.g., the Z-axis direction). The wall WL can be formed with an inclined surface that is tilted relative to the base layer BSL at a selected angle. However, the embodiment is not limited to this, and the wall WL can have curved side surfaces or stepped side surfaces. For example, the wall WL can have a semi-circular or semi-elliptical cross-section.

[0165] The wall WL may comprise at least one organic and / or inorganic material. For example, the wall WL may comprise organic materials such as acrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, polyester resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). However, the embodiments are not limited thereto, and the wall WL may comprise various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0166] Electrode ALE can be disposed on the via layer VIA and wall WL. Electrode ALE can at least partially cover the side surface and / or top surface of wall WL. Electrode ALE disposed on wall WL can have a shape corresponding to wall WL. For example, electrode ALE disposed on wall WL can include an inclined or curved surface having a shape corresponding to the shape of wall WL. For example, wall WL and electrode ALE can be reflective members that reflect light emitted from light-emitting element LD and guide light forward toward pixel PXL in a third direction (e.g., Z-axis direction). Therefore, the light output efficiency of display panel PNL can be improved.

[0167] Electrodes ALEs may be spaced apart from each other. Electrodes ALEs may be disposed on the same layer. For example, electrodes ALEs may be formed simultaneously in the same process, or may be formed from the same material, but the embodiments are not limited thereto.

[0168] Electrodes ALE can receive alignment signals during the step (or process) of aligning the light-emitting elements LD. Therefore, an electric field can be formed between electrodes ALE, enabling the light-emitting elements LD included in each pixel PXL to be aligned between electrodes ALE.

[0169] Electrode ALE may include at least one conductive material. For example, electrode ALE may include at least one of the following: various metallic materials, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), or alloys thereof; conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), or gallium tin oxide (GTO); and conductive polymers, such as poly(PEDOT), but the embodiments are not limited thereto.

[0170] The first electrode ALE1 can be electrically connected to the first transistor electrode TE1 of transistor M through contact holes penetrating the via layer VIA and the passivation layer PSV. The second electrode ALE2 can be electrically connected to the third power conductive layer PL2c through contact holes penetrating the via layer VIA and the passivation layer PSV.

[0171] A first insulating layer INS1 can be formed on the electrode ALE. The first insulating layer INS1 can be composed of a single layer or multiple layers, and can include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0172] A first dam BNK1 may be disposed on a first insulating layer INS1. The first dam BNK1 may include an opening overlapping the emitting region EA. The opening of the first dam BNK1 may provide space for forming the light-emitting element LD in the step (or process) of providing the light-emitting element LD to each pixel PXL. For example, light-emitting element ink of a desired type and / or amount may be provided to the space defined by the opening of the first dam BNK1.

[0173] The first layer BNK1 may include organic materials such as acrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, polyester resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). However, the embodiments are not limited thereto, and the first layer BNK1 may include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO)x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0174] The light-emitting element LD can be disposed between the electrodes ALE. The light-emitting element LD can be biased and aligned between the electrodes ALE. For example, the light-emitting element LD can be biased and aligned such that the first end EP1 (or the first semiconductor layer 11) can face or overlap with the first electrode ALE1, and the second end EP2 (or the second semiconductor layer 13) can face or overlap with the second electrode ALE2.

[0175] The light-emitting element (LD) can be disposed in the opening of the first dike BNK1 and between the walls WL. The LD can be prepared (or provided) in a dispersed form in a light-emitting element ink and provided to each pixel PXL by inkjet printing or a similar method. For example, the LD can be dispersed in a volatile solvent and provided to each pixel PXL. Subsequently, when an alignment signal is provided to the electrodes ALE, an electric field can be formed between the electrodes ALE, allowing the LD to be aligned between them. After the LD is aligned, the LD can be stably disposed between the electrodes ALE by evaporating the solvent or otherwise removing it.

[0176] A second insulating layer INS2 can be provided on the light-emitting element LD. For example, the second insulating layer INS2 can be partially provided on the light-emitting element LD, and the first end EP1 and the second end EP2 of the light-emitting element LD can be exposed. When the second insulating layer INS2 is formed on the light-emitting element LD after the alignment of the light-emitting element LD is completed, the light-emitting element LD can be prevented from separating from the aligned position.

[0177] The second insulating layer INS2 can be composed of a single layer or multiple layers, and can include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0178] The connecting electrode ELT can be disposed on the first end EP1 and the second end EP2 of the light-emitting element LD that are exposed by the second insulating layer INS2. The first connecting electrode ELT1 can be disposed (e.g., directly disposed) on the first end EP1 of the first light-emitting element LD1 and can be in contact with the first end EP1 (or the first semiconductor layer 11) of the first light-emitting element LD1.

[0179] The second connection electrode ELT2 can be disposed (e.g., directly disposed) on the second end EP2 (or the second semiconductor layer 13) of the first light-emitting element LD1, and can be in contact with the second end EP2 (or the second semiconductor layer 13) of the first light-emitting element LD1. The second connection electrode ELT2 can also be disposed (e.g., directly disposed) on the first end EP1 (or the first semiconductor layer 11) of the second light-emitting element LD2, and can be in contact with the first end EP1 (or the first semiconductor layer 11) of the second light-emitting element LD2. The second connection electrode ELT2 can electrically connect the second end EP2 (or the second semiconductor layer 13) of the first light-emitting element LD1 and the first end EP1 (or the first semiconductor layer 11) of the second light-emitting element LD2.

[0180] For example, the third connecting electrode ELT3 can be disposed (e.g., directly disposed) on the second end EP2 (or the second semiconductor layer 13) of the second light-emitting element LD2, and can be in contact with the second end EP2 (or the second semiconductor layer 13) of the second light-emitting element LD2. The third connecting electrode ELT3 can be disposed (e.g., directly disposed) on the first end EP1 (or the first semiconductor layer 11) of the third light-emitting element LD3, and can be in contact with the first end EP1 (or the first semiconductor layer 11) of the third light-emitting element LD3. The third connecting electrode ELT3 can electrically connect the second end EP2 (or the second semiconductor layer 13) of the second light-emitting element LD2 and the first end EP1 (or the first semiconductor layer 11) of the third light-emitting element LD3.

[0181] For example, the fourth connecting electrode ELT4 can be disposed (e.g., directly disposed) on the second end EP2 (or the second semiconductor layer 13) of the third light-emitting element LD3, and can be in contact with the second end EP2 (or the second semiconductor layer 13) of the third light-emitting element LD3. The fourth connecting electrode ELT4 can also be disposed (e.g., directly disposed) on the first end EP1 (or the first semiconductor layer 11) of the fourth light-emitting element LD4, and can be in contact with the first end EP1 (or the first semiconductor layer 11) of the fourth light-emitting element LD4. The fourth connecting electrode ELT4 can electrically connect the second end EP2 (or the second semiconductor layer 13) of the third light-emitting element LD3 and the first end EP1 (or the first semiconductor layer 11) of the fourth light-emitting element LD4.

[0182] For example, the fifth connecting electrode ELT5 can be disposed (e.g., directly disposed) on the second end EP2 (or the second semiconductor layer 13) of the fourth light-emitting element LD4, and can be in contact with the second end EP2 (or the second semiconductor layer 13) of the fourth light-emitting element LD4.

[0183] The first connecting electrode ELT1 can be electrically connected to the first electrode ALE1 through a contact hole penetrating the first insulating layer INS1. The fifth connecting electrode ELT5 can be electrically connected to the second electrode ALE2 through a contact hole penetrating the first insulating layer INS1.

[0184] In an embodiment, the connecting electrode ELT may be composed of a conductive layer. For example, such as Figure 8 and Figure 9 As shown, the first connecting electrode ELT1, the third connecting electrode ELT3, and the fifth connecting electrode ELT5 can be disposed on the same layer. The second connecting electrode ELT2 and the fourth connecting electrode ELT4 can be disposed on the same layer. The first connecting electrode ELT1, the third connecting electrode ELT3, and the fifth connecting electrode ELT5 can be disposed on the second insulating layer INS2. The third insulating layer INS3 can be disposed on the first connecting electrode ELT1, the third connecting electrode ELT3, and the fifth connecting electrode ELT5. The second connecting electrode ELT2 and the fourth connecting electrode ELT4 can be disposed on the third insulating layer INS3.

[0185] When the third insulating layer INS3 is disposed between the connecting electrodes ELT made of different conductive layers, the connecting electrodes ELT can be stably separated by the third insulating layer INS3. Therefore, the electrical stability between the first end EP1 and the second end EP2 of the light-emitting element LD can be ensured.

[0186] The third insulating layer INS3 can consist of a single layer or multiple layers, and can include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0187] In another embodiment, the connection electrode ELT can be constructed from the same conductive layer. For example, as... Figure 10 and Figure 11As shown, the first connecting electrode ELT1, the second connecting electrode ELT2, the third connecting electrode ELT3, the fourth connecting electrode ELT4, and the fifth connecting electrode ELT5 can be disposed on the same layer. For example, the first connecting electrode ELT1, the second connecting electrode ELT2, the third connecting electrode ELT3, the fourth connecting electrode ELT4, and the fifth connecting electrode ELT5 can be formed simultaneously in the same process, or they can be formed from the same material. When the connecting electrodes ELT are formed simultaneously, the number of masks can be reduced, and the manufacturing process can be simplified.

[0188] The connecting electrode ELT can be made of various transparent conductive materials. For example, the connecting electrode ELT may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), zinc tin oxide (ZTO), or gallium tin oxide (GTO), and can be implemented as substantially transparent or translucent to meet a selected light transmittance. Therefore, light emitted from the first end EP1 and the second end EP2 of the light-emitting element LD can pass through the connecting electrode ELT and can be emitted to the outside of the display panel PNL.

[0189] The second dike, BNK2, can be installed on top of the first dike, BNK1. The second dike, BNK2, can also be installed in the non-launch area (NEA).

[0190] The second dam BNK2 may include an opening that overlaps with the emission region EA. The opening in the second dam BNK2 may provide space in which a color conversion layer, as described later, is provided. For example, a color conversion layer of a desired type and / or amount may be provided into the space defined by the opening in the second dam BNK2.

[0191] The second layer BNK2 may include organic materials such as acrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, polyester resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). However, the embodiments are not limited thereto, and the second layer BNK2 may include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0192] Figure 12This is a schematic cross-sectional view showing the first to third pixels according to an embodiment. Figure 13 This is a schematic cross-sectional view of pixels according to an embodiment.

[0193] Figure 12 The color conversion layer CCL, optical layer OPL, and / or color filter layer CFL are shown. Figure 12 For ease of description, the following will be omitted. Figures 8 to 11 The components other than the base layer BSL and the second embankment BNK2. Figure 12 The stacking structure of pixel PXL is shown in detail for the color conversion layer CCL, optical layer OPL and / or color filter layer CFL.

[0194] refer to Figure 12 and Figure 13 The second dam BNK2 can be disposed between or at the boundaries of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, and can include an opening that overlaps with each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The openings of the second dam BNK2 can provide space for forming the color conversion layer CCL.

[0195] The color conversion layer CCL can be disposed on the light-emitting element LD in the opening of the second embankment BNK2. The color conversion layer CCL may include a first color conversion layer CCL1 disposed in the first pixel PXL1, a second color conversion layer CCL2 disposed in the second pixel PXL2, and a scattering layer LSL disposed in the third pixel PXL3.

[0196] In an embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be included in... Figure 1 and Figure 2 The embodiments described herein include light-emitting elements (LDs). For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include light-emitting elements (LDs) that emit light of the same color (e.g., a third color (or blue)). A full-color image can be displayed by providing a color conversion layer (CCL) comprising color conversion particles on each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0197] The first color conversion layer CCL1 may include first color conversion particles that convert third-color light emitted from the light-emitting element LD into first-color light. For example, the first color conversion layer CCL1 may include first quantum dots QD1 dispersed in a selected matrix material (such as a base resin).

[0198] In an embodiment, when the light-emitting element LD is a blue light-emitting element that emits blue light and the first pixel PXL1 is a red pixel, the first color conversion layer CCL1 may include a first quantum dot QD1 that converts blue light emitted from the blue light-emitting element into red light. The first quantum dot QD1 may absorb blue light and emit red light by shifting the wavelength according to energy conversion. When the first pixel PXL1 is a pixel of a different color, the first color conversion layer CCL1 may include a first quantum dot QD1 corresponding to the color of the first pixel PXL1.

[0199] The second color conversion layer CCL2 may include second color conversion particles that convert light of a third color emitted from the light-emitting element LD into light of a second color. For example, the second color conversion layer CCL2 may include second quantum dots QD2 dispersed in a selected matrix material (such as a base resin).

[0200] In an embodiment, when the light-emitting element LD is a blue light-emitting element that emits blue light and the second pixel PXL2 is a green pixel, the second color conversion layer CCL2 may include a second quantum dot QD2 that converts the blue light emitted by the blue light-emitting element into green light. The second quantum dot QD2 may absorb blue light and emit green light by shifting the wavelength according to energy conversion. If the second pixel PXL2 is a pixel of a different color, the second color conversion layer CCL2 may include a second quantum dot QD2 corresponding to the color of the second pixel PXL2.

[0201] In this embodiment, since blue light with a relatively short wavelength in the visible light region is incident on the first quantum dot QD1 and the second quantum dot QD2, the absorption coefficients of the first quantum dot QD1 and the second quantum dot QD2 can be increased. Accordingly, the efficiency of the light ultimately emitted from the first pixel PXL1 and the second pixel PXL2 can be improved, and excellent color reproduction can be ensured or guaranteed. By configuring the emission units (EMUs) of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 using light-emitting elements (LDs) of the same color (e.g., blue light-emitting elements), the manufacturing efficiency of the display device can be improved.

[0202] A scattering layer LSL can be provided to effectively utilize a third color (or blue) light emitted from a light-emitting element (LD). For example, in the case where the LD is a blue light-emitting element that emits blue light and the third pixel PXL3 is a blue pixel, the scattering layer LSL can include at least one type of scatterer SCT to effectively utilize the light emitted from the LD. For example, the scatterer SCT of the scattering layer LSL can include at least one of barium sulfate (BaSO4), calcium carbonate (CaCO3), titanium dioxide (TiO2), silicon dioxide (SiO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), and zinc oxide (ZnO). For example, the scatterer SCT can be disposed not only in the third pixel PXL3, but can also be selectively included in the first color conversion layer CCL1 or the second color conversion layer CCL2. In another example, the scatterer SCT can be omitted, and the scattering layer LSL can be formed of a transparent polymer.

[0203] A first capping layer CPL1 can be set on the color conversion layer CCL. The first capping layer CPL1 can be set across the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The first capping layer CPL1 can cover the color conversion layer CCL. The first capping layer CPL1 can prevent foreign objects such as moisture or air from penetrating from the outside and damaging or contaminating the color conversion layer CCL.

[0204] The first capping layer CPL1 can be an inorganic layer and can include silicon nitride (SiN). x ), aluminum nitride (AlN) x ), titanium nitride (TiN) x ), silicon oxide (SiO) x ), aluminum oxide (AlO) x ), titanium oxide (TiO) x ), silicon oxide carbide (SiO) x C y ), silicon oxynitride (SiO) x N y (or similar items)

[0205] An optical layer OPL can be disposed on the first capping layer CPL1. The optical layer OPL can function to improve light extraction efficiency by recycling light provided from the color conversion layer CCL via total internal reflection. For example, the optical layer OPL can have a relatively low refractive index compared to the color conversion layer CCL. For example, the refractive index of the color conversion layer CCL can be in the range of 1.6 to 2.0, and the refractive index of the optical layer OPL can be in the range of 1.1 to 1.3.

[0206] A second capping layer CPL2 can be set on the optical layer OPL. The second capping layer CPL2 can be set across the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The second capping layer CPL2 can cover the optical layer OPL. The second capping layer CPL2 can prevent foreign objects such as moisture or air from seeping in from the outside and damaging or contaminating the optical layer OPL.

[0207] The second capping layer CPL2 can be an inorganic layer and may include silicon nitride (SiN). x ), aluminum nitride (AlN) x ), titanium nitride (TiN) x ), silicon oxide (SiO) x ), aluminum oxide (AlO) x ), titanium oxide (TiO) x ), silicon oxide carbide (SiO) x C y ), silicon oxynitride (SiO) x N y (or similar items)

[0208] A planarization layer PLL can be set on the second capping layer CPL2. The planarization layer PLL can be set across the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0209] The planarization layer PLL may comprise organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiments are not limited thereto, and the planarization layer PLL may comprise various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0210] A color filter layer (CFL) can be set on the planarization layer (PLL). The color filter layer (CFL) can include color filters CF1, CF2, and CF3 that match the colors of pixels PXL. By setting color filters CF1, CF2, and CF3 that match the colors of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, a full-color image can be displayed.

[0211] The color filter layer CFL may include a first color filter CF1 disposed in a first pixel PXL1 and selectively transmitting light emitted from the first pixel PXL1, a second color filter CF2 disposed in a second pixel PXL2 and selectively transmitting light emitted from the second pixel PXL2, and a third color filter CF3 disposed in a third pixel PXL3 and selectively transmitting light emitted from the third pixel PXL3.

[0212] In the embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can be a red color filter, a green color filter, and a blue color filter, respectively, but the embodiments are not limited thereto. Hereinafter, when referring to any of the first color filter CF1, the second color filter CF2, and the third color filter CF3, or when referring to two or more types of color filters in general, they may be referred to as "color filter CF" or "multiple color filters CF".

[0213] The first color filter CF1 may overlap with the first color conversion layer CCL1 in a third direction (e.g., the Z-axis direction). The first color filter CF1 may include a color filter material that selectively transmits light of a first color (or red). For example, if the first pixel PXL1 is a red pixel, the first color filter CF1 may include a red color filter material.

[0214] The second color filter CF2 may overlap with the second color conversion layer CCL2 in a third direction (e.g., the Z-axis direction). The second color filter CF2 may include a color filter material that selectively transmits light of a second color (or green). For example, if the second pixel PXL2 is a green pixel, the second color filter CF2 may include a green color filter material.

[0215] The third color filter CF3 may overlap with the scattering layer LSL in a third direction (e.g., the Z-axis direction). The third color filter CF3 may include a filter material that selectively transmits a third color (or blue) of light. For example, if the third pixel PXL3 is a blue pixel, the third color filter CF3 may include a blue filter material.

[0216] According to an embodiment, a light-blocking layer BM can be further disposed between the first color filter C1, the second color filter C2, and the third color filter CF3. With the light-blocking layer BM formed between the first color filter C1, the second color filter C2, and the third color filter CF3, color mixing defects that may be visible from the front or side surface of the display device can be prevented. The material of the light-blocking layer BM is not limited, and various light-blocking materials can be used. For example, the light-blocking layer BM can be implemented by stacking the first color filter C1, the second color filter C2, and the third color filter CF3.

[0217] An outer coating OC can be applied to the color filter layer CFL. The outer coating OC can be applied to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The outer coating OC can cover the lower components, including the color filter layer CFL. The outer coating OC prevents moisture or air from penetrating into the lower components. The outer coating OC protects the lower components from foreign matter such as dust.

[0218] The outer coating OC may include organic materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, polyester resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). However, the embodiments are not limited thereto, and the outer coating OC may include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) or titanium oxide (TiO) x ).

[0219] Figure 14 This is a schematic block diagram illustrating an electronic device 1000 including a display device according to an embodiment. Figure 15 It is shown Figure 14 The electronic device 1000 is a schematic diagram of an example of a smartphone. Figure 16 It is shown Figure 14 The electronic device 1000 is a schematic diagram of an example of a tablet computer.

[0220] refer to Figures 14 to 16 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 3 The display device. The electronic device 1000 may also include various ports for communicating with a graphics card, sound card, memory card, USB device, or other systems. In embodiments, such as... Figure 15 As shown, the electronic device 1000 can be a smartphone. In an embodiment, as... Figure 16As shown, electronic device 1000 may be a tablet computer. However, the above examples are merely illustrative, and electronic device 1000 is not necessarily limited to the examples described above. For example, electronic device 1000 may be a cellular phone, video phone, smart tablet, smartwatch, navigation device for a vehicle, computer display, laptop computer, head-mounted display device, or the like.

[0221] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may include a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, a controller, and at least one of the like. Processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. In embodiments, processor 1010 may be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus. In embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display an image based on the input image data provided from processor 1010.

[0222] The memory device 1020 can store data required for performing operations of the electronic device 1000. The memory device 1020 can be used as working memory and / or buffer memory of the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0223] Storage device 1030 can store data in response to control signals or data from processor 1010. Storage device 1030 may include one or more non-volatile memories to retain data even when electronic device 1000 is powered off. In some embodiments, storage device 1030 may include solid-state drive (SSD), hard disk drive (HDD), CD-ROM, or the like.

[0224] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. In an embodiment, display device 1060 may be integrated with I / O device 1040.

[0225] Power supply 1050 can supply the power required to operate electronic device 1000. For example, power supply 1050 may include a power management integrated circuit (PMIC). In an embodiment, power supply 1050 can supply power to display device 1060.

[0226] The display device 1060 can display an image in response to image data signals and / or control signals from the processor 1010. The display device 1060 can be connected to other components via a bus or other communication link.

[0227] According to the embodiments, by deriving the maximum distance between light-emitting elements and the maximum number of light-emitting elements that minimize pixel brightness dispersion, the display quality and reliability of the display device can be improved.

[0228] The effects of the embodiments are not limited to the above description, and this specification includes many other effects.

[0229] Those skilled in the art to which the presented embodiments pertain will understand that this disclosure can be implemented in modified forms without departing from the basic features described above. Therefore, the methods described above should be considered illustratively rather than restrictively. The scope of this disclosure is indicated in the claims rather than in the foregoing description, and all differences within the equivalent scope should be construed as included in this disclosure.

Claims

1. A display device, characterized in that, include: A dike surrounds the launch area; The first electrode and the second electrode are spaced apart from each other in the emission region; as well as A light-emitting element is disposed between the first electrode and the second electrode. Wherein, when the diameter of each of the light-emitting elements is α, the maximum distance between the light-emitting elements in the first direction is 25α or less, and the maximum distance between the light-emitting element closest to the dike in the first direction and the dike is 12.5α or less.

2. The display device according to claim 1, characterized in that, The α is 0.5 μm or smaller.

3. The display device according to claim 1, characterized in that, The maximum distance between the light-emitting elements in the first direction is 4 μm or greater.

4. The display device according to claim 1, characterized in that, The embankment extends in a second direction intersecting the first direction and includes a first extension and a second extension spaced apart from each other in the first direction.

5. The display device according to claim 4, characterized in that, The maximum distance between the light-emitting element closest to the first extension and the first extension in the first direction is 12.5α or less.

6. The display device according to claim 5, characterized in that, The maximum distance between the light-emitting element closest to the second extension in the first direction and the second extension is 12.5α or less.

7. The display device according to claim 1, characterized in that, The first electrode and the second electrode are spaced apart from each other in a second direction that intersects with the first direction.

8. The display device according to claim 1, characterized in that, The first end of the light-emitting element faces the first electrode, and The second end of the light-emitting element faces the second electrode.

9. The display device according to claim 8, characterized in that, Also includes: The first connecting electrode and the second connecting electrode are disposed on the light-emitting element.

10. An electronic device, characterized in that, include: A processor used to provide input image data; as well as A display device for displaying an image based on the input image, the display device defining sub-pixel regions. The display device includes: A dike surrounds the launch area; The first electrode and the second electrode are spaced apart from each other in the emission region; and A light-emitting element is disposed between the first electrode and the second electrode. Wherein, when the diameter of each of the light-emitting elements is α, the maximum distance between the light-emitting elements in the first direction is 25α or less, and the maximum distance between the light-emitting element closest to the dike in the first direction and the dike is 12.5α or less.

Images