Low-voltage multiplier circuits and electronic equipment

Abstract

This utility model discloses a low-voltage multiplier circuit and electronic device. The low-voltage multiplier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first MOSFET. The base and collector of the first transistor, the base and collector of the second transistor, and the collector of the second transistor are used to receive a first current. The emitters of the first transistor and the fourth transistor are used to receive a second current. The emitters of the second transistor and the third transistor, the gate and drain of the first MOSFET are interconnected. The source of the first MOSFET is grounded. The collector of the third transistor is used to output a third current. The bases of the third transistor and the base and collector of the fourth transistor are used to receive a fourth current. This utility model solves the problems of small linear input range, large nonlinear error, and high distortion in low-voltage multipliers.

Description

Technical Field

[0001] This utility model relates to the field of multipliers, and more particularly to a low-voltage multiplier circuit and electronic device. Background Technology

[0002] Multipliers, as fundamental modules in integrated circuits, are widely used in many signal processing fields such as artificial neural networks, adaptive filtering, modulation and demodulation, and frequency conversion. Currently, many design techniques and circuit structures are focused on optimizing the performance of multipliers, such as high speed, low power consumption, low supply voltage, and high bandwidth. For example, in power factor correction (PFC) applications, most PFC control chips require multipliers to implement their functions.

[0003] There are many ways to design a multiplier: some utilize the square law relationship between the voltage and current of a MOSFET, some utilize the volt-ampere characteristic of a MOSFET in the linear region, and some utilize Gilbert cells. These methods have drawbacks in low-voltage multipliers, such as a small linear input range, large nonlinear error, and high distortion, and the circuit complexity is also relatively high. Utility Model Content

[0004] In view of the shortcomings of the prior art, the purpose of this utility model is to provide a low-voltage multiplier circuit and electronic device to solve the problems of small linear input range, large nonlinear error and large distortion of low-voltage multipliers.

[0005] The technical solution of this utility model is as follows:

[0006] A low-voltage multiplier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first MOSFET;

[0007] The base, collector, base, and collector of the first transistor, the second transistor, and the second transistor are used to connect to a first current. The emitter of the first transistor and the emitter of the fourth transistor are used to connect to a second current. The emitter of the second transistor, the emitter of the third transistor, the gate of the first MOSFET, and the drain of the first MOSFET are interconnected. The source of the first MOSFET is grounded. The collector of the third transistor is used to output a third current. The base, base, and collector of the third transistor and the fourth transistor are used to connect to a fourth current.

[0008] Optionally, the low-voltage multiplier circuit further includes a second MOSFET and a third MOSFET;

[0009] The gate, drain, and gate of the second MOS transistor are used to receive a first current. The source of the second MOS transistor is connected to the collector of the first transistor. The drain of the third MOS transistor is used to receive a second current. The source of the third MOS transistor is connected to the collector of the third transistor.

[0010] Optionally, the first transistor, the second transistor, the third transistor, and the fourth transistor are of the same size.

[0011] Optionally, the low-voltage multiplier circuit further includes:

[0012] The input circuit has a power supply terminal for connecting to a power source, a first output terminal for outputting a first current, a second output terminal for outputting a second current, and a third output terminal for outputting a fourth current. The input circuit also has a first input terminal for receiving a first input current, a second input terminal for receiving a second input current, and a third input terminal for receiving a third input current. The input circuit is used to add the first and second input currents to output the first current, add the first and fourth input currents to output the second current, and convert the third input current to output the fourth current.

[0013] Optionally, the input circuit includes a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, and a fifth current mirror. The input terminal of the first current mirror is used to receive a first input current, the output terminal of the second current mirror is used to output a second current, the input terminal of the third current mirror is connected to the output terminal of the first current mirror, and the output terminal of the third current mirror is used to output the first current. The fourth current mirror is connected to the third current mirror, and the input terminal of the fourth current mirror is used to receive the second input current. The fifth current mirror is connected to the second current mirror, and the output terminal of the fifth current mirror is used to output the fourth current.

[0014] Optionally, the first current mirror includes a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; the second current mirror includes a seventh MOSFET and an eighth MOSFET; the third current mirror includes a ninth MOSFET and a tenth MOSFET; the fourth current mirror includes an eleventh MOSFET and a twelfth MOSFET; and the fifth current mirror includes a thirteenth MOSFET, a fourteenth MOSFET, and a fifteenth MOSFET.

[0015] The gate, drain, fifth, and sixth MOSFETs are used to receive a first input current. The sources of the fourth, fifth, sixth, seventh, and eighth MOSFETs are grounded. The drains of the sixth and seventh MOSFETs are used to output a second current. The gates of the seventh, eighth, and eighth MOSFETs are interconnected with the drain of the thirteenth MOSFET. The drains of the fifth, ninth, and tenth MOSFETs are interconnected. The drains of the tenth and eleventh MOS transistors are used to output a first current. The gates of the eleventh, twelfth, and fifteenth MOS transistors are used to connect a second input current. The gates of the thirteenth, fourteenth, and fifteenth MOS transistors are interconnected. The drain of the fourteenth MOS transistor is used to output a fourth current. The sources of the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth MOS transistors are used to connect to a power supply.

[0016] Optionally, the fourth, fifth, and sixth MOS transistors are of the same size; the seventh and eighth MOS transistors are of the same size; the ninth and tenth MOS transistors are of the same size; the eleventh and twelfth MOS transistors are of the same size; and the thirteenth, fourteenth, and fifteenth MOS transistors are of the same size.

[0017] This invention also proposes an electronic device comprising multiple low-voltage multiplier circuits as described above, wherein the multiple low-voltage multiplier circuits are cascaded.

[0018] Optionally, the electronic device further includes:

[0019] Multiple current mirrors are provided, with their input terminals connected one-to-one to the output terminals of the multiple low-voltage multiplier circuits. The current mirrors are used to convert the current signals output by the low-voltage multiplier circuits into current sources and then output them.

[0020] Optionally, the electronic device further includes:

[0021] The processor has its input terminal connected to the output terminals of the plurality of current mirrors. The processor is used to receive current sources output by the plurality of current mirrors and to perform conversion processing on the current sources.

[0022] Through the connection relationship described above, this utility model enables the low-voltage multiplier circuit to operate without additional operational amplifiers, resulting in a simple circuit structure. The operating voltage only requires Vthn + VBE + Vos, where Vthn is the threshold voltage of the NMOS transistor (typically 0.4V), VBE is the base-emitter voltage drop of the transistor (typically approximately 0.6V), and Vos is the saturation voltage drop of the MOS transistor (typically 0.2V), meeting the requirements for low-voltage applications up to 1.8V. Furthermore, the matching between the transistors gives this structure the advantages of high linearity, low error, and low distortion. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the low-voltage multiplier circuit of this utility model.

[0025] Figure 2 This is a schematic diagram of the circuit structure of another embodiment of the low-voltage multiplier circuit of this utility model.

[0026] Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the input circuit in the low-voltage multiplier circuit of this utility model.

[0027] Explanation of reference numerals in the attached diagram: Q1, first transistor; Q2, second transistor; Q3, third transistor; Q4, fourth transistor; MN1, first MOSFET; MN2, second MOSFET; MN3, third MOSFET; N1, fourth MOSFET; N2, fifth MOSFET; N3, sixth MOSFET; N4, seventh MOSFET; N5, eighth MOSFET; P1, ninth MOSFET; P2, tenth MOSFET; P3, eleventh MOSFET; P4, twelfth MOSFET; P5, thirteenth MOSFET; P6, fourteenth MOSFET; P7, fifteenth MOSFET; I12, first current; I14, second current; I1, first input current; I2, second input current; I3, third current; I4, fourth current; I7, third input current; VCC, power supply. Detailed Implementation

[0028] To make the objectives, technical solutions, and effects of this utility model clearer and more explicit, the present utility model will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0029] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of this utility model involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0030] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0031] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0032] Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0033] Multipliers, as fundamental modules in integrated circuits, are widely used in many signal processing fields such as artificial neural networks, adaptive filtering, modulation and demodulation, and frequency conversion. Currently, many design techniques and circuit structures are focused on optimizing the performance of multipliers, such as high speed, low power consumption, low supply voltage, and high bandwidth. For example, in power factor correction (PFC) applications, most PFC control chips require multipliers to implement their functions.

[0034] There are many ways to design a multiplier: some utilize the square law relationship between the voltage and current of a MOSFET, some utilize the volt-ampere characteristic of a MOSFET in the linear region, and some utilize Gilbert cells. These methods have drawbacks in low-voltage multipliers, such as a small linear input range, large nonlinear error, and high distortion, and the circuit complexity is also relatively high.

[0035] To solve the above problems, this utility model proposes a low-voltage multiplier circuit.

[0036] Reference Figure 1 In one embodiment, the low-voltage multiplier circuit includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, and a first MOSFET MN1;

[0037] The base, collector, base, and collector of the first transistor Q1, the second transistor Q2, and the second transistor Q4 are used to connect to a first current I12. The emitter of the first transistor Q1 and the emitter of the fourth transistor Q4 are used to connect to a second current I14. The emitter of the second transistor Q2, the emitter of the third transistor Q3, the gate of the first MOSFET MN1, and the drain of the first MOSFET MN1 are interconnected. The source of the first MOSFET MN1 is grounded. The collector of the third transistor Q3 is used to output a third current I3. The base of the third transistor Q3, the base of the fourth transistor Q4, and the collector of the fourth transistor Q4 are used to connect to a fourth current I4.

[0038] Furthermore, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are of the same size.

[0039] In this embodiment, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 can be NPN transistors, the first MOSFET MN1 can be an NMOS transistor, and the low-voltage multiplier circuit utilizes the logarithmic relationship between the transistor voltage and current. By adding or subtracting the transistor voltage, the multiplication and division of the current can be achieved.

[0040] right Figure 1The circuit structure is analyzed as follows:

[0041] Because the transistor operates in the amplification region, its collector current I c With base-emitter voltage drop V BE The relationship is:

[0042]

[0043] Where I S V is a constant used to describe the transfer characteristics of a transistor in the forward amplification region. T This is the thermal voltage, approximately 26mV at room temperature. When the transistor's amplification factor is sufficient, the base current is negligible relative to the collector current. For the fourth transistor Q4, its collector current is I4, the magnitude of which is the same as the fourth current I4. The collector current of the third transistor Q3 is I3, the magnitude of which is the same as the third current I3. Let the collector current of the first transistor Q1 be I1, and the collector current of the second transistor Q2 be I2, according to... Figure 1 The circuit connection relationships are as follows:

[0044]

[0045] I 12 =I1+I2;

[0046] I 14 =I1+I4;

[0047] Among them, I 12 The magnitude is the same as the magnitude of the first current I12, I 14 The magnitude is the same as that of the second current I14, V BE1 V is the base-emitter voltage drop of the first transistor Q1. BE2 V is the base-emitter voltage drop of the second transistor Q2. BE3 V is the base-emitter voltage drop of the third transistor Q3. BE4 This is the base-emitter voltage drop of the fourth transistor Q4; because the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 use perfectly matched transistors of the same size, their Ig... S Similarly, dividing I1 / I2 and I4 / I3 respectively yields:

[0048]

[0049] Depend on Figure 1 The connection relationship, the V of the first transistor Q1 BE1 Subtract V from the second transistor Q2 BE2 Equal to the V of the fourth transistor Q4 BE4 Subtract V from the third transistor Q3 BE3 ,Right now:

[0050] V BE1 =V BE2 =V BE4 -V BE3 ;

[0051] so:

[0052]

[0053] Furthermore, we can obtain:

[0054]

[0055] From the above analysis, it can be seen that the current I... 12 Let I be the sum of currents I1 and I2, and let I be the current I. 14 As the sum of currents I1 and I4, this invention ensures that the output current I3 has a fixed multiplication and division relationship with I1, I2, and I4. If current I1 is set as a fixed current, the product of output current I3 and I2 and I4 is a set ratio; if current I2 (or I4) is set as a fixed current, the value of output current I3 divided by I4 (or I2) is a set ratio, resulting in extremely small linear error. Furthermore, all of the above multiplication and division relationships are unaffected by the transistor V. BE V T V A and I S The influence of parameters such as process and temperature is reduced. In summary, the circuit structure of this invention does not require an additional operational amplifier, resulting in a simple circuit structure. Furthermore, the operating voltage only requires Vthn + VBE + Vos, where Vthn is the threshold voltage of the NMOS transistor (typically approximately 0.4V), VBE is the base-emitter voltage drop of the transistor (typically approximately 0.6V), and Vos is the saturation voltage drop of the MOS transistor (typically approximately 0.2V), meeting the requirements for low-voltage applications up to 1.8V. Additionally, the matching between the transistors gives this structure advantages such as high linearity, low error, and low distortion.

[0056] Alternatively, multipliers can use transistors with a logarithmic voltage-current relationship to achieve multiplication, but this does not take into account the Erlich effect of the transistors. The collector-emitter voltage drops of transistors that achieve a logarithmic relationship are different, which will introduce linearity errors.

[0057] Therefore, refer to Figure 3 In one embodiment, the low-voltage multiplier circuit further includes a second MOS transistor MN2 and a third MOS transistor MN3;

[0058] The gate of the second MOS transistor MN2, the drain of the second MOS transistor MN2, and the gate of the third MOS transistor MN3 are used to connect to the first current I12. The source of the second MOS transistor MN2 is connected to the collector of the first transistor Q1. The drain of the third MOS transistor MN3 is used to connect to the second current I14. The source of the third MOS transistor MN3 is connected to the collector of the third transistor Q3.

[0059] In this embodiment, to further improve the linearity of the low-voltage multiplier, the Erlich effect of the transistor is considered, and a corrected transistor collector current I is obtained. C as follows:

[0060]

[0061] Where I S V is a constant used to describe the transfer characteristics of a transistor in the forward amplification region, typically ranging from approximately 10exp(-14)A to 10exp(-16)A; CE V is the collector-emitter voltage drop of the transistor; A This is the Urlie voltage, typically ranging from approximately 10V to 100V; V T This is the thermal voltage, approximately 26mV at room temperature. It can be seen that if the V1 of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4... CE If the voltages are the same, the effect of the Erlich voltage can be eliminated, and the calculation can be performed according to the formula mentioned earlier. The voltages V1 of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are... CE The difference between them and the Earlier voltage V A Compared to being two orders of magnitude smaller, then V A The effect is negligible, that is, the V between different transistors CE The difference is within several hundred mV, the Earlier voltage V A The impact is relatively small, therefore a reasonable approximation is made. The first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are the same transistor, and their V values ​​can be approximated as... BE Since the second MOSFET MN2 and the third MOSFET MN3 are matched, their gate-source voltages are approximately considered to be equal. GS2 =V GS3 V GS2 V is the gate-source voltage of the second MOSFET MN2. GS3 The gate-source voltage of the third MOSFET MN3 is determined by... Figure 3 From the circuit connection relationship, we can obtain:

[0062] V CE1 =V BE1 =V BE ;

[0063] V CE2 =V BE2 =V BE ;

[0064] V CE3 =V BE1 +V GS2 -V GS3 =V BE ;

[0065] V CE4 =V BE4 =V BE ;

[0066] Therefore, we can conclude that:

[0067] V CE1 =V CE2 =V CE3 =V CE4 =V BE ;

[0068] Therefore, refer to Figure 3 The low-voltage multiplier circuit of this invention can eliminate the influence of the Erlie effect and has high linearity.

[0069] In one embodiment, the low-voltage multiplier circuit further includes:

[0070] The input circuit has a power supply terminal for connecting to a power source, a first output terminal for outputting a first current I12, a second output terminal for outputting a second current I14, and a third output terminal for outputting a fourth current I4. The input circuit also has a first input terminal for receiving a first input current I1, a second input terminal for receiving a second input current I2, and a third input terminal for receiving a third input current I7. The input circuit is used to add the first input current I1 and the second input current I2 to output the first current I12. It is also used to add the first input current I1 and the fourth current I4 to output the second current I14. Furthermore, the input circuit is used to convert the third input current I7 to output the fourth current I4.

[0071] Furthermore, the input circuit includes a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, and a fifth current mirror. The input terminal of the first current mirror is used to receive a first input current I1, the output terminal of the second current mirror is used to output a second current I14, the input terminal of the third current mirror is connected to the output terminal of the first current mirror, and the output terminal of the third current mirror is used to output a first current I12. The fourth current mirror is connected to the third current mirror, and the input terminal of the fourth current mirror is used to receive the second input current I2. The fifth current mirror is connected to the second current mirror, and the output terminal of the fifth current mirror is used to output a fourth current I4.

[0072] Furthermore, referring to Figure 3 In one embodiment, the first current mirror includes a fourth MOSFET N1, a fifth MOSFET N2, and a sixth MOSFET N3; the second current mirror includes a seventh MOSFET N4 and an eighth MOSFET N5; the third current mirror includes a ninth MOSFET P1 and a tenth MOSFET P2; the fourth current mirror includes an eleventh MOSFET P3 and a twelfth MOSFET P4; and the fifth current mirror includes a thirteenth MOSFET P5, a fourteenth MOSFET P6, and a fifteenth MOSFET P7.

[0073] The gate, drain, fifth MOSFET N2, and sixth MOSFET N3 are used to connect to the first input current I1. The sources of the fourth MOSFET N1, fifth MOSFET N2, sixth MOSFET N3, seventh MOSFET N4, and eighth MOSFET N5 are grounded. The drains of the sixth MOSFET N3 and seventh MOSFET N4 are used to output the second current I14. The gates of the seventh MOSFET N4, eighth MOSFET N5, and eighth MOSFET N5 are interconnected with the drain of the thirteenth MOSFET P5. The drains of the fifth MOSFET N2, ninth MOSFET P1, and tenth MOSFET P2 are interconnected. The drains of the tenth MOSFET P2 and the eleventh MOSFET P3 are used to output the first current I12. The gates of the eleventh MOSFET P3, the gates of the twelfth MOSFET P4, and the drains of the twelfth MOSFET P4 are used to connect the second input current I2. The gates of the thirteenth MOSFET P5, the fourteenth MOSFET P6, the fifteenth MOSFET P7, and the drains of the fifteenth MOSFET P7 are interconnected. The drain of the fourteenth MOSFET P6 is used to output the fourth current. The sources of the ninth MOSFET P1, the tenth MOSFET P2, the eleventh MOSFET P3, the twelfth MOSFET P4, the thirteenth MOSFET P5, the fourteenth MOSFET P6, and the fifteenth MOSFET P7 are connected to the power supply VCC.

[0074] Furthermore, the fourth MOSFET N1, the fifth MOSFET N2, and the sixth MOSFET N3 have the same dimensions; the seventh MOSFET N4 and the eighth MOSFET N5 have the same dimensions; the ninth MOSFET P1 and the tenth MOSFET P2 have the same dimensions; the eleventh MOSFET P3 and the twelfth MOSFET P4 have the same dimensions; and the thirteenth MOSFET P5, the fourteenth MOSFET P6, and the fifteenth MOSFET P7 have the same dimensions.

[0075] In this embodiment, the fourth MOSFET N1, the fifth MOSFET N2, the sixth MOSFET N3, the seventh MOSFET N4, and the eighth MOSFET N5 are NMOS transistors, and the ninth MOSFET P1, the tenth MOSFET P2, the eleventh MOSFET P3, the twelfth MOSFET P4, the thirteenth MOSFET P5, the fourteenth MOSFET P6, and the fifteenth MOSFET P7 are PMOS transistors. This is the current addition circuit of the multiplier circuit of this utility model. From Figure 1 and Figure 2 From the circuit analysis, the current I 12Let I be the sum of currents I1 and I2, and let I be the current I. 14 The sum of currents I1 and I4 is easily achieved through current addition, as shown below. Figure 2 As shown, a current adding circuit is provided for input current. It should be noted that the magnitude of the first current I12 is related to the current I... 12 The first current I12 is the same as the sum of the currents of the first transistor Q1 and the second transistor Q2; the magnitude of the second current I14 is the same as the current I. 14 Similarly, the magnitude of the third current I3 is the same as that of the current I3, and the magnitude of the fourth current I4 is the same as that of the current I4. Figure 2 The third input current I7 is copied and converted by the fifth current mirror to output a fourth current I4, and the magnitude of the fourth current I4 is the same as that of the third input current I7.

[0076] from Figure 2 The connection relationship shows that the fourth MOSFET N1, the fifth MOSFET N2, and the sixth MOSFET N3 form the first current mirror. Given the same dimensions, their currents are equal, that is:

[0077] I1=I N1 =I N2 =I N3 ;

[0078] The seventh MOSFET N4 and the eighth MOSFET N5 form a second current mirror. Given the same dimensions, their currents are equal, i.e.:

[0079] I P5 =I N5 =I N4 ;

[0080] The ninth MOSFET P1 and the tenth MOSFET P2 form a third current mirror. Given the same dimensions, their currents are equal, that is:

[0081] I N2 =I P1 =I P2 ;

[0082] The eleventh MOSFET P3 and the twelfth MOSFET P4 form the fourth current mirror. Given the same dimensions, their currents are equal, that is:

[0083] I2=I P4 =I P3 ;

[0084] The thirteenth MOSFET P5, the fourteenth MOSFET P6, and the fifteenth MOSFET P7 form the fifth current mirror. Given the same dimensions, their currents are equal, that is:

[0085] I7 = I4 = I P5 ;

[0086] in,

[0087] I 12 =I P2 +I P3 =I1+I2;

[0088] I 14 =I N3 +I N4 =I1+I4;

[0089] In this way, the currents are added together. Furthermore, the ratio of the current mirror can be adjusted to achieve current addition at different ratios. It should be noted that by inputting the current addition signals—the first current I12 and the second current I14—to the transistor in the low-voltage multiplier circuit, a linear combination of the input signals can be ensured, allowing the low-voltage multiplier to maintain linear characteristics within a certain range. Moreover, in low-voltage environments, signal strength is often weak and easily affected by noise and other interference. By adding multiple input current signals, the overall signal amplitude can be increased, thereby enhancing the circuit's signal processing capabilities.

[0090] This utility model also proposes an electronic device.

[0091] In one embodiment, the electronic device includes a plurality of low-voltage multiplier circuits as described above, wherein the plurality of low-voltage multiplier circuits are cascaded.

[0092] In this embodiment, it is understood that since the aforementioned low-voltage multiplier circuit is used in the electronic device of this utility model, the embodiments of the electronic device of this utility model include all the technical solutions of all embodiments of the aforementioned low-voltage multiplier circuit, and the achieved technical effects are exactly the same, which will not be repeated here. In order to achieve more current multiplication and division, multiple low-voltage multiplier circuits can be cascaded, for example, two low-voltage multiplier circuits can be connected, and the third current output by one low-voltage multiplier circuit can be used as the input current of another low-voltage multiplier circuit.

[0093] In one embodiment, the electronic device further includes:

[0094] Multiple current mirrors are provided, with their input terminals connected one-to-one to the output terminals of the multiple low-voltage multiplier circuits. The current mirrors are used to convert the current signals output by the low-voltage multiplier circuits into current sources and then output them.

[0095] In this embodiment, the current signal output by the low-voltage multiplier circuit refers to the magnitude of the current of I3. I3 is a current drain, which can be converted into a current source output to the subsequent circuit for processing through a current mirror.

[0096] In one embodiment, the electronic device further includes:

[0097] The processor has its input terminal connected to the output terminals of the plurality of current mirrors. The processor is used to receive current sources output by the plurality of current mirrors and to perform conversion processing on the current sources.

[0098] In this embodiment, the processor can be a digital signal processor (DSP), a programmable logic device (PLD), a microprocessor, an MCU, or other electronic components. The processor can convert the current sources output from multiple current mirrors, i.e., analog signals, into digital signals for subsequent data processing.

[0099] It should be understood that the application of this utility model is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A low-voltage multiplier circuit, characterized in that, It includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first MOSFET; The base, collector, base, and collector of the first transistor, the second transistor, and the second transistor are used to connect to a first current. The emitter of the first transistor and the emitter of the fourth transistor are used to connect to a second current. The emitter of the second transistor, the emitter of the third transistor, the gate of the first MOSFET, and the drain of the first MOSFET are interconnected. The source of the first MOSFET is grounded. The collector of the third transistor is used to output a third current. The base, base, and collector of the third transistor and the fourth transistor are used to connect to a fourth current.

2. The low-voltage multiplier circuit as described in claim 1, characterized in that, The low-voltage multiplier circuit also includes a second MOSFET and a third MOSFET; The gate, drain, and gate of the second MOS transistor are used to receive a first current. The source of the second MOS transistor is connected to the collector of the first transistor. The drain of the third MOS transistor is used to receive a second current. The source of the third MOS transistor is connected to the collector of the third transistor.

3. The low-voltage multiplier circuit as described in claim 1, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are all the same size.

4. The low-voltage multiplier circuit as described in claim 1, characterized in that, The low-voltage multiplier circuit also includes: The input circuit has a power supply terminal for connecting to a power source, a first output terminal for outputting a first current, a second output terminal for outputting a second current, and a third output terminal for outputting a fourth current. The input circuit also has a first input terminal for receiving a first input current, a second input terminal for receiving a second input current, and a third input terminal for receiving a third input current. The input circuit is used to add the first and second input currents to output the first current, add the first and fourth input currents to output the second current, and convert the third input current to output the fourth current.

5. The low-voltage multiplier circuit as described in claim 4, characterized in that, The input circuit includes a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, and a fifth current mirror. The input terminal of the first current mirror is used to receive a first input current, the output terminal of the second current mirror is used to output a second current, the input terminal of the third current mirror is connected to the output terminal of the first current mirror, and the output terminal of the third current mirror is used to output the first current. The fourth current mirror is connected to the third current mirror, and the input terminal of the fourth current mirror is used to receive the second input current. The fifth current mirror is connected to the second current mirror, and the output terminal of the fifth current mirror is used to output the fourth current.

6. The low-voltage multiplier circuit as described in claim 5, characterized in that, The first current mirror includes a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; the second current mirror includes a seventh MOSFET and an eighth MOSFET; the third current mirror includes a ninth MOSFET and a tenth MOSFET; the fourth current mirror includes an eleventh MOSFET and a twelfth MOSFET; and the fifth current mirror includes a thirteenth MOSFET, a fourteenth MOSFET, and a fifteenth MOSFET. The gate, drain, fifth, and sixth MOSFETs are used to receive a first input current. The sources of the fourth, fifth, sixth, seventh, and eighth MOSFETs are grounded. The drains of the sixth and seventh MOSFETs are used to output a second current. The gates of the seventh, eighth, and eighth MOSFETs are interconnected with the drain of the thirteenth MOSFET. The drains of the fifth, ninth, and tenth MOSFETs are interconnected. The drains of the tenth and eleventh MOS transistors are used to output a first current. The gates of the eleventh, twelfth, and fifteenth MOS transistors are used to connect a second input current. The gates of the thirteenth, fourteenth, and fifteenth MOS transistors are interconnected. The drain of the fourteenth MOS transistor is used to output a fourth current. The sources of the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth MOS transistors are used to connect to a power supply.

7. The low-voltage multiplier circuit as described in claim 6, characterized in that, The fourth, fifth, and sixth MOS transistors are the same size; the seventh and eighth MOS transistors are the same size; the ninth and tenth MOS transistors are the same size; the eleventh and twelfth MOS transistors are the same size; and the thirteenth, fourteenth, and fifteenth MOS transistors are the same size.

8. An electronic device, characterized in that, It includes multiple low-voltage multiplier circuits as described in any one of claims 1-7, and the multiple low-voltage multiplier circuits are cascaded.

9. The electronic device as claimed in claim 8, characterized in that, The electronic device also includes: Multiple current mirrors are provided, with their input terminals connected one-to-one to the output terminals of the multiple low-voltage multiplier circuits. The current mirrors are used to convert the current signals output by the low-voltage multiplier circuits into current sources and then output them.

10. The electronic device as claimed in claim 9, characterized in that, The electronic device also includes: The processor has its input terminal connected to the output terminals of the plurality of current mirrors. The processor is used to receive current sources output by the plurality of current mirrors and to perform conversion processing on the current sources.

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