A power-down retention circuit to avoid low-voltage interference timing in charging piles

Abstract

This utility model discloses a power-down retention circuit to avoid low-voltage interference timing in charging piles, comprising: an energy storage unit, an isolation unit, a power-down protection unit, and a power switching unit; the energy storage unit is connected to the power-down protection unit, the power-down protection unit is connected to the isolation unit, and the isolation unit is connected to the power switching unit. By controlling the power supply of the device during power failure through the isolation unit and the power switching unit, the power supply is switched to prevent the supercapacitor in the circuit from supplying power to the system, further ensuring that the core board timing is not affected by residual voltage interference during device restart. Compared with traditional power-down retention circuits, this utility model has simpler circuit components and lower cost. It can effectively maintain power supply briefly after system power failure, ensuring data preservation, and can disconnect the small voltage to discharge the system when the voltage drops below a certain threshold, solving the problem of power-on timing disorder during restart, thereby ensuring stable and reliable circuit operation.

Description

Technical Field

[0001] This utility model relates to the field of power failure protection technology, specifically to a power failure retention circuit that avoids timing interference from low voltage in charging piles. Background Technology

[0002] Most charging stations, especially high-power DC fast charging stations, are designed with a circuit to briefly maintain power supply after a power outage (usually called a backup power supply or UPS function). This is not to allow the vehicle to continue charging, but to perform some critical safety and state preservation operations. The conventional implementation method is to use a supercapacitor bank. However, this circuit has the following drawback in certain situations: after the power drops to a certain threshold, a small, continuous output voltage will remain. When the device is restarted, this small voltage will interfere with the product's startup timing, causing startup sequence disorder and preventing the product from starting. This design can shut down this undesirable low voltage during startup, thereby avoiding the situation where the product cannot start. Utility Model Content

[0003] The main purpose of this utility model is to provide a power-off retention circuit that avoids low-voltage interference in the timing of charging piles. After the device loses power to a certain threshold, there will be a small voltage continuously output. When the device is restarted, the small voltage will not interfere with the device startup timing, thus preventing the device from failing to restart.

[0004] A power-off retention circuit to avoid low-voltage interference timing in charging piles includes: an energy storage unit, an isolation unit, a power-off protection unit, and a power switching unit;

[0005] The energy storage unit, power failure protection unit, isolation unit, and power switching unit are connected in sequence;

[0006] The power failure protection unit includes:

[0007] The positive terminal of capacitor diode D6 is connected to two parallel branches. One parallel branch includes resistors R54, R55, and R90 connected in series. The other parallel branch includes resistors R38, R39, and R40 connected in series. Resistor R38 is connected in parallel across resistor R54, resistor R39 is connected in parallel across resistor R55, and resistor R40 is connected in parallel across resistor R90.

[0008] The negative terminal of capacitor diode D6 is connected to resistors R90 and R40.

[0009] Furthermore, the energy storage unit of this utility model includes:

[0010] The negative terminal of supercapacitor C62 is connected to the positive terminal of supercapacitor C63, the negative terminal of supercapacitor C63 is grounded, and the positive terminal of supercapacitor C62 is connected to the power-off protection unit.

[0011] Resistor R42 is connected in parallel across the supercapacitor C62, and resistor R43 is connected in parallel across the supercapacitor C63.

[0012] Furthermore, the isolation unit of this utility model includes:

[0013] The gate of MOSFET Q1 is connected to resistor R4, capacitor C78, ​​the gate of MOSFET Q2, and the power switching module. The source of MOSFET Q1 is connected to the source of MOSFET Q2, and also to the other end of resistor R4 and capacitor C78. The drain of MOSFET Q2 is connected to a 5V voltage source.

[0014] In this configuration, the drain of MOSFET Q1 is connected to the negative terminal of capacitor diode D6 in the power-down retention unit.

[0015] Furthermore, the power switching module of this utility model includes:

[0016] Resistor R6 is connected to the collector of transistor Q6, and the base of transistor Q6 is connected to resistors R138 and R139 and capacitor C117; the other end of resistor R139 is connected to the emitter of transistor Q6 and capacitor C117.

[0017] The other end of resistor R138 is connected to a 3.3V voltage source.

[0018] This invention controls the power supply of the device by using MOSFETs Q1 and Q2 and transistor Q6 to switch the power supply when the power is off, avoiding the use of farad capacitors in the circuit to power the system, and further ensuring that the timing of the core board will not be affected by residual voltage when the device restarts. Attached Figure Description

[0019] The accompanying drawings, which form part of this application, are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an undue limitation of the present invention. In the drawings:

[0020] Figure 1 This is a schematic diagram of the power-off retention circuit of this utility model. Detailed Implementation

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present utility model, and not all of them. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.

[0022] like Figure 1 As shown, the power-off retention circuit of this utility model for avoiding low-voltage interference timing of charging piles includes: an energy storage unit, an isolation unit, a power-off protection unit, and a power switching unit.

[0023] The energy storage unit is connected to the power failure protection unit, which is connected to the isolation unit, and the isolation unit is connected to the power switching unit.

[0024] The energy storage unit includes: supercapacitor C62, supercapacitor C63, resistor R42, and resistor R43;

[0025] The negative terminal of supercapacitor C62 is connected to the positive terminal of supercapacitor C63, the negative terminal of supercapacitor C63 is grounded, and the positive terminal of supercapacitor C62 is connected to the power-off protection unit.

[0026] Resistor R42 is connected in parallel across the supercapacitor C62, and resistor R43 is connected in parallel across the supercapacitor C63.

[0027] The power-off protection unit includes: capacitor and diode D6, resistors R54, R55, R38, R39, R90, and R40.

[0028] The positive terminal of capacitor diode D6 is connected to two parallel branches. One parallel branch includes resistors R54, R55, and R90 connected in series, and the other parallel branch includes resistors R38, R39, and R40 connected in series. Resistor R38 is connected in parallel across resistor R54, resistor R39 is connected in parallel across resistor R55, and resistor R40 is connected in parallel across resistor R90.

[0029] The negative terminal of capacitor diode D6 is connected to resistor R90, resistor R40 and isolation unit.

[0030] The isolation unit includes: MOSFET Q1, MOSFET Q2, capacitor C78, ​​and resistor R4;

[0031] The gate of MOSFET Q1 is connected to resistor R4, capacitor C78, ​​the gate of MOSFET Q2, and the power switching module. The source of MOSFET Q1 is connected to the source of MOSFET Q2, and also to the other end of resistor R4 and capacitor C78. The drain of MOSFET Q2 is connected to a 5V voltage source.

[0032] In this configuration, the drain of MOSFET Q1 is connected to the negative terminal of capacitor diode D6 in the power-down retention unit.

[0033] The power switching module includes: resistor R6, resistor R138, resistor R139, capacitor C117, and transistor Q6.

[0034] Resistor R6 is connected to the collector of transistor Q6, and the base of transistor Q6 is connected to resistors R138 and R139 and capacitor C117; the other end of resistor R139 is connected to the emitter of transistor Q6 and capacitor C117.

[0035] The other end of resistor R138 is connected to a 3.3V voltage source.

[0036] The following is a detailed explanation of the circuit operation:

[0037] When the circuit of this utility model is powered on, it controls the MOSFET switch to achieve power-down retention after the 3.3V voltage source is lost. That is, when the voltage is lower than a certain threshold, the MOSFET switch is turned off, and the power-down retention circuit can no longer supply power to the system. When the system is powered on again, there will be no interference from this small voltage, so the system can start up successfully and work normally.

[0038] In the power-down retention circuit, supercapacitors C62 and C63 are used to store electrical energy to continue supplying power to the system after a power outage; balancing resistors R42 and R43 are used to maintain the balance across the supercapacitors; resistors R54, R55, R90, R38, R39, and R10 are used to adjust the charging speed of the supercapacitors; and capacitor diode D6 ensures that the supercapacitors do not discharge externally under normal operating voltage. During power-down discharge, the current flows through capacitor diode D6, reducing losses.

[0039] Transistor Q6 is directly controlled by a 3.3V voltage source. After the system is powered on, the 3.3V voltage is output normally. At this time, transistor Q6 is turned on, and MOSFETs Q1 and Q2 are also turned on, so the supercapacitor can be charged normally. When the system voltage drops below 3.3V, making it impossible for transistor Q6 to turn on, MOSFET Q2 is turned off, and the supercapacitor stops supplying power to the system, ensuring that the low voltage at this time cannot supply power to the core board.

[0040] When the system is powered on again, the core board timing will not be affected by residual voltage, thus enabling it to start and work normally.

[0041] Compared with traditional power-off retention circuits, this utility model has simpler circuit components and lower cost. It can effectively maintain power supply briefly after the system is powered off to ensure the preservation of information data, and can also disconnect a small voltage to discharge the system when the voltage is lower than a certain threshold. This solves the problem of disordered power-on timing during restart, thereby ensuring the stable and reliable operation of the circuit.

[0042] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

[0043] Furthermore, it should be noted that if any directional indication (such as up, down, left, right, front, back, etc.) is involved in the embodiments of this utility model, the directional indication is only used to explain the relative positional relationship and movement of each component in a specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0044] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, in the embodiments of this utility model, "multiple" refers to two or more. Moreover, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

Claims

1. A power-down retention circuit to avoid low-voltage interference timing in charging piles, characterized in that, include: Energy storage unit, isolation unit, power failure protection unit, power switching unit; The energy storage unit, power failure protection unit, isolation unit, and power switching unit are connected in sequence; The power failure protection unit includes: The positive terminal of capacitor diode D6 is connected to two parallel branches. One parallel branch includes resistors R54, R55, and R90 connected in series. The other parallel branch includes resistors R38, R39, and R40 connected in series. Resistor R38 is connected in parallel across resistor R54, resistor R39 is connected in parallel across resistor R55, and resistor R40 is connected in parallel across resistor R90. The negative terminal of capacitor diode D6 is connected to resistor R90, resistor R40 and isolation unit.

2. The brown-out hold circuit to avoid low voltage glitch timing of a charging station of claim 1, wherein, Energy storage units include: The negative terminal of supercapacitor C62 is connected to the positive terminal of supercapacitor C63, the negative terminal of supercapacitor C63 is grounded, and the positive terminal of supercapacitor C62 is connected to the power-off protection unit. Resistor R42 is connected in parallel across the supercapacitor C62, and resistor R43 is connected in parallel across the supercapacitor C63.

3. The brown-out hold circuit to avoid charge-pit low voltage glitch timing of claim 1, wherein, The isolation unit includes: The gate of MOSFET Q1 is connected to resistor R4, capacitor C78, ​​the gate of MOSFET Q2, and the power switching module. The source of MOSFET Q1 is connected to the source of MOSFET Q2, and also to the other end of resistor R4 and capacitor C78. The drain of MOSFET Q2 is connected to a 5V voltage source. In this configuration, the drain of MOSFET Q1 is connected to the negative terminal of capacitor diode D6 in the power-down retention unit.

4. The brown-out hold circuit to avoid charge-pit low voltage glitch timing of claim 3, wherein, The power switching module includes: Resistor R6 is connected to the collector of transistor Q6, and the base of transistor Q6 is connected to resistors R138 and R139 and capacitor C117; the other end of resistor R139 is connected to the emitter of transistor Q6 and capacitor C117. The other end of resistor R138 is connected to a 3.3V voltage source.

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