Multi-power supply circuit and mobile device

Abstract

This application provides a multi-power supply circuit and a mobile device. The multi-power supply circuit includes: a power switching circuit configured to: when the mobile device is simultaneously connected to any two or more of a first power supply, a second power supply, and a third power supply, select one of the first power supply, the second power supply, or the third power supply as the power source according to the priority order; when the mobile device is only connected to any one of the first power supply, the second power supply, and the third power supply, select the first power supply, the second power supply, or the third power supply as the power source; and a power supply circuit for supplying power to the mobile device by outputting a rated voltage according to the connected power supply, wherein the first power supply is provided by the original first adapter of the mobile device, the second power supply is provided by the second adapter based on the Universal Serial Bus (USB) power supply, and the third power supply is provided by the third adapter based on the Ethernet cable power supply, with the priority order from high to low being the first power supply, the second power supply, and the third power supply.

Description

Technical Field

[0001] This application relates primarily to the field of power supply circuit technology, and in particular to a multi-power supply circuit and mobile device. Background Technology

[0002] Current mobile devices often only support a single power supply method, which means that users cannot power their devices in a timely manner when the corresponding adapter is not working or is unavailable. For example, in the field of point-of-sale (POS) terminals, most POS machines from different manufacturers require customized adapters, and even different types of POS machines from the same manufacturer require different types of adapters. This leads to problems such as a single power supply method, poor integration, and inconvenience caused by the need for customized adapters. Utility Model Content

[0003] The technical problem to be solved by this application is to provide a multi-power supply circuit and mobile device that can integrate multiple power supply methods and flexibly switch power supplies.

[0004] To address the aforementioned technical problems, this application provides a multi-power supply circuit suitable for switching between a first power supply, a second power supply, and a third power supply to power a mobile device. The multi-power supply circuit includes: a power switching circuit configured to: when the mobile device is simultaneously connected to any two or more of the first, second, and third power supplies, select one of the first, second, or third power supplies as the power source according to its priority order; when the mobile device is connected to only one of the first, second, and third power supplies, select the first, second, or third power supply as the power source; and a power supply circuit for outputting a rated voltage to power the mobile device based on the connected power supply, wherein the first power supply is provided by the mobile device's original first adapter, the second power supply is provided by a second adapter powered via a Universal Serial Bus (USB) system, and the third power supply is provided by a third adapter powered via an Ethernet cable system, with the priority order from highest to lowest being the first, second, and third power supplies.

[0005] Optionally, the second adapter is an adapter that is compatible with the Power Delivery protocol and has a Type-C interface.

[0006] Optionally, the Ethernet cable-based adapter is an adapter that complies with the Power over Ethernet protocol.

[0007] Optionally, the power supply circuit includes: a first power switch circuit for outputting a first power supply voltage according to the first power supply connected to it; a second power switch circuit for outputting a second power supply voltage according to the second power supply connected to it; a third power switch circuit for outputting a third power supply voltage according to the third power supply connected to it; and a BUCK circuit for converting the first power supply voltage, the second power supply voltage and / or the third power supply voltage into a rated voltage, wherein the first power supply voltage, the second power supply voltage and the third power supply voltage may be the same or different.

[0008] Optionally, the power switching circuit includes: a first switching circuit electrically connected to a second power switch circuit, configured such that when the first switching circuit is connected to a first power source, the second power switch circuit does not output a second supply voltage; a second switching circuit electrically connected to a third power switch circuit, configured such that when the second switching circuit is connected to the first power source, the third power switch circuit does not output a third supply voltage; and a third switching circuit electrically connected to a third power switch circuit, configured such that when the third switching circuit is connected to the second power source, the third power switch circuit does not output a third supply voltage.

[0009] Optionally, the first power switch circuit, the second power switch circuit, and the third power switch circuit all include: a reverse-feedback protection circuit, used to output a first supply voltage, a second supply voltage, or a third supply voltage according to the connected first power supply, second power supply, or third power supply, and to prevent voltage from flowing back from the output terminal of the first power switch circuit, the second power switch circuit, or the third power switch circuit to the corresponding input terminal.

[0010] Optionally, the first power switch circuit, the second power switch circuit, and the third power switch circuit all further include: a switch sub-circuit, used to enable the anti-reverse current circuit to output the first supply voltage, the second supply voltage, or the third supply voltage when the first power supply, the second power supply, or the third power supply is connected, and to enable the anti-reverse current circuit not to output the first supply voltage, the second supply voltage, or the third supply voltage when the first power supply, the second power supply, or the third power supply is not connected.

[0011] Optionally, the anti-reverse-drain circuit includes: a first PMOS transistor, the drain of which is connected to a first power supply, a second power supply, or a third power supply; a second PMOS transistor, the source of which is connected to the source of the first PMOS transistor, and the gate of which is connected to the gate of the first PMOS transistor; a first voltage divider resistor, the two ends of which are connected to the source and the gate of the second PMOS transistor, respectively; and a second voltage divider resistor, one end of which is connected to the gate of the second PMOS transistor, wherein when the other end of the second voltage divider resistor is grounded, the drain of the second PMOS transistor outputs a first supply voltage, a second supply voltage, or a third supply voltage.

[0012] Optionally, the anti-reverse-fighting circuit also includes a capacitor connected in parallel with the first voltage divider resistor.

[0013] Optionally, the switching sub-circuit includes: a third voltage divider resistor, one end of which is connected to a first power supply, a second power supply, or a third power supply; a fourth voltage divider resistor, one end of which is grounded; a first NMOS transistor, the gate of which is connected to the other end of the third voltage divider resistor and the other end of the fourth voltage divider resistor, the drain of which is connected to the other end of the second voltage divider resistor, and the source of which is grounded.

[0014] Optionally, the first switching circuit is electrically connected to the switching sub-circuit of the second power switch circuit, and the second and third switching circuits are respectively electrically connected to the switching sub-circuit of the third power switch circuit; the first, second, and third switching circuits each include: a fifth voltage divider resistor, one end of which is connected to the first or second power supply; a sixth voltage divider resistor, one end of which is grounded; a second NMOS transistor, the gate of which is connected to the other end of the fifth and sixth voltage divider resistors respectively, the drain of which is connected to the other end of the corresponding third voltage divider resistor, and the source of which is grounded.

[0015] Optionally, the multi-power supply circuit further includes: a first INT signal triggering circuit for outputting a first INT signal when the first power supply is connected; a second INT signal triggering circuit for outputting a second INT signal when the second power supply is connected; and a third INT signal triggering circuit for outputting a third INT signal when the third power supply is connected.

[0016] Optionally, the first INT signal trigger circuit, the second INT signal trigger circuit, and the third INT signal trigger circuit each include: a seventh voltage divider resistor, one end of which is connected to a first power supply, a second power supply, or a third power supply; an eighth voltage divider resistor, one end of which is grounded; a third NMOS transistor, the gate of which is connected to the other ends of the seventh and eighth voltage divider resistors respectively, and the source of which is grounded; and a ninth resistor, one end of which is connected to a fixed voltage level, and the other end of which is connected to the drain of the third NMOS transistor. When the first, second, or third power supply is connected, the other end of the ninth resistor is at a low voltage level, and the low voltage level is used as the first INT signal, the second INT signal, or the third INT signal.

[0017] To address the aforementioned technical problems, this application provides a mobile device suitable for being powered by a first power source, a second power source, and a third power source, comprising: a first power interface for connecting to the first power source; a second power interface for connecting to the second power source; a third power interface for connecting to the third power source; and a multi-power supply circuit as described in any embodiment of this application, wherein the output terminals of the first power interface, the second power interface, and the third power interface are electrically connected to the input terminal of the multi-power supply circuit.

[0018] Optionally, the second adapter is an adapter that uses the Power Delivery protocol and a Type-C interface, and the second power interface is a Type-C interface; the third adapter is an adapter that uses the Power over Ethernet protocol, and the third power interface is an RJ45 interface.

[0019] Optionally, the multi-power supply circuit includes a first power switch circuit, a second power switch circuit, and a third power switch circuit. The output terminal of the first power interface is electrically connected to the input terminal of the first power switch circuit, the second power switch circuit is electrically connected to the input terminal of the second power switch circuit, and the output terminal of the third power interface is electrically connected to the input terminal of the third power switch circuit.

[0020] Optionally, the mobile device also includes a CPU main control module; the multi-power supply circuit also includes at least one of a first INT signal triggering circuit, a second INT signal triggering circuit, and a third INT signal triggering circuit, and the CPU main control module is configured to acquire the first INT signal corresponding to the first INT signal triggering circuit, the second INT signal corresponding to the second INT signal triggering circuit, and / or the third INT signal corresponding to the third INT signal triggering circuit.

[0021] Optionally, when the multi-power supply circuit includes a third INT signal trigger circuit, the CPU main control module is configured to turn off the high-power function of the mobile device after receiving the third INT signal, wherein when the high-power function is running, the real-time power of the mobile device is higher than the rated power corresponding to the rated voltage.

[0022] Optionally, high-power features include printer functionality.

[0023] Optionally, the mobile device also includes a display module configured to display to the user that the high-power function is unavailable after the CPU main control module disables the high-power function.

[0024] Compared with the prior art, this application has the following advantages: In addition to providing power to the device using only the original first adapter, it integrates a second adapter based on Universal Serial Bus (USB) and a third adapter based on Ethernet cable to provide the second and third power supplies respectively, enabling the mobile device to flexibly choose the power supply method; the second adapter using the Power Delivery protocol and a Type-C interface, and the third adapter using the Power over Ethernet protocol, are readily available, further enhancing the power supply stability of the mobile device; after the mobile device's CPU main control module receives the third INT signal, it shuts down the high-power function of the mobile device, preventing the operation of the high-power function from affecting the power supply of the weaker third power supply to the mobile device, thus enabling the third power supply to support the stable operation of the mobile device. Attached Figure Description

[0025] The accompanying drawings are included to provide a further understanding of this application; they are incorporated into and constitute a part of this application. The drawings illustrate embodiments of this application and, together with this specification, serve to explain the principles of this application. In the drawings:

[0026] Figure 1 This is a schematic diagram of a multi-power supply circuit according to an embodiment of this application;

[0027] Figure 2 This is a structural block diagram of a power switching circuit and a power supply circuit according to an embodiment of this application;

[0028] Figure 3 This is a circuit diagram of a first power switch circuit according to an embodiment of this application;

[0029] Figure 4 This is a circuit diagram of a second power switch circuit and a first switching circuit according to an embodiment of this application;

[0030] Figure 5 This is a circuit diagram of a third power switch circuit, a second switching circuit, and a third switching circuit according to an embodiment of this application;

[0031] Figure 6 This is a circuit diagram of a first INT signal trigger circuit according to an embodiment of this application; and

[0032] Figure 7 This is a structural block diagram of a mobile device according to an embodiment of this application. Detailed Implementation

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0034] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0035] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0036] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0037] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0038] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0039] It should be understood that when a component is referred to as "on another component," "connected to another component," "coupled to another component," or "in contact with another component," it can be directly on, connected to, coupled to, or in contact with that other component, or there may be an intervening component. In contrast, when a component is referred to as "directly on another component," "directly connected to," "directly coupled to," or "directly in contact with" another component, there is no intervening component. Similarly, when a first component is referred to as "electrically contacting" or "electrically coupled to" a second component, there is an electrical path between the first and second components that allows current to flow. This electrical path may include capacitors, coupled inductors, and / or other components that allow current to flow, even if there is no direct contact between the conductive components.

[0040] This application proposes a multi-power supply circuit suitable for switching between a first power supply, a second power supply, and a third power supply to power a mobile device. The first power supply is provided by the mobile device's original first adapter, the second power supply is provided by a second adapter based on Universal Serial Bus (USB), and the third power supply is provided by a third adapter based on Ethernet cable. Preferably, the second adapter is an adapter compatible with the Power Delivery protocol and a Type-C interface. It should be noted that the second adapter corresponding to the multi-power supply circuit is a common adapter for most smartphones. Given the high penetration rate of smartphones, users using mobile devices with multi-power supply circuits can easily obtain a second adapter from their surroundings to power the mobile device even if the first adapter cannot be used. Preferably, the Ethernet cable-based adapter is an adapter compatible with the Power over Ethernet protocol. It should also be noted that the third adapter corresponding to the multi-power supply circuit has a completely different power supply protocol from the second adapter, and the Power over Ethernet protocol applicable to the third adapter has a wide audience and application scenarios. Therefore, users can also easily obtain a third adapter from their surroundings to power mobile devices with multi-power supply circuits. The following description, in conjunction with the accompanying drawings, details the power switching between the first, second, and third power supplies in the multi-power supply circuit and the specific details of powering mobile devices.

[0041] Figure 1 This is a schematic diagram of a multi-power supply circuit according to an embodiment of this application, referring to... Figure 1 As shown, the multi-power supply circuit 10 includes a power supply circuit 11, a power switching circuit 12, a first INT signal trigger circuit 13, a second INT signal trigger circuit 14, and a third INT signal trigger circuit 15. The power switching circuit 12 is configured such that: when the mobile device is simultaneously connected to any two or more of the first power supply DC_IN, the second power supply TYPEC_IN, and the third power supply POE_IN, one of these power supplies is selected as the power source according to its priority; when the mobile device is connected to only one of these power supplies, the first power supply DC_IN, the second power supply TYPEC_IN, and the third power supply POE_IN, that power supply is selected as the power source. The priority order from highest to lowest is: first power supply DC_IN, second power supply TYPEC_IN, and third power supply POE_IN. The power supply circuit 11 is used to supply power to the mobile device by outputting the rated voltage according to the connected power supply. Figure 1 The corresponding embodiment provides a multi-power supply circuit 10, which will be referred to below. Figure 1of Figures 2-6 The circuit structures of the power supply circuit 11 and the power switching circuit 12 are described exemplarily.

[0042] Figure 2 yes Figure 1 The corresponding embodiment shows the structural block diagram of the power switching circuit and the power supply circuit. Figure 3 yes Figure 1 The circuit diagram of the first power switch circuit in the corresponding embodiment is shown below. (Refer to...) Figure 2 and Figure 3 The power supply circuit 11 includes a first power switch circuit 111, which outputs a first supply voltage DC_OUT based on the input first power supply DC_IN. The first power switch circuit 111 includes a reverse current protection circuit 1111 and a switch sub-circuit 1112. The reverse current protection circuit 1111 outputs the first supply voltage DC_OUT based on the input first power supply DC_IN and prevents voltage from flowing back from the output terminal of the first power switch circuit 111 (i.e., the port where the first supply voltage DC_OUT is output) to the corresponding input terminal (i.e., the port where the first power supply DC_IN is input). Preferably, the reverse current protection circuit 1111 includes a first PMOS transistor Q2, a second PMOS transistor Q3, a first voltage divider resistor R4, a second voltage divider resistor R5, and a capacitor C1. Specifically, the drain (D) of the first PMOS transistor Q2 is connected to the first power supply DC_IN. The source (S) of the second PMOS transistor Q3 is connected to the source (S) of the first PMOS transistor Q2, and the gate (G) of the second PMOS transistor Q3 is connected to the gate (G) of the first PMOS transistor Q2. The two ends of the first voltage divider resistor R4 are connected to the source (S) and gate (G) of the second PMOS transistor Q3, respectively. One end of the second voltage divider resistor R5 is connected to the gate (G) of the second PMOS transistor Q3. The capacitor C1 is connected in parallel with the first voltage divider resistor R4. The switching sub-circuit 1112 is used to enable the anti-reverse current circuit 1111 to output the first supply voltage DC_OUT when the first power supply DC_IN is connected, and to prevent the anti-reverse current circuit 1111 from outputting the first supply voltage DC_OUT when the first power supply DC_IN is not connected. Preferably, the switching sub-circuit 1112 includes a third voltage divider resistor R6, a fourth voltage divider resistor R7, and a first NMOS transistor Q4. Specifically, one end of the third voltage divider resistor R6 is connected to the first power supply DC_IN, one end of the fourth voltage divider resistor R7 is grounded, the gate 1 of the first NMOS transistor Q4 is connected to the other end of the third voltage divider resistor R6 and the other end of the fourth voltage divider resistor R7, the drain 3 of the first NMOS transistor Q4 is connected to the other end of the second voltage divider resistor R5, and the source 2 of the first NMOS transistor Q4 is grounded.

[0043] Continue to refer to Figure 3The working principle of the first power switch circuit 111 is as follows: When the first adapter is connected, the connected first power supply DC_IN is forward-biased to the source S of the first PMOS transistor Q2 through the body diode of the first PMOS transistor Q2. Simultaneously, the connected first power supply DC_IN causes the voltage at one end of the gate G of the first NMOS transistor Q4 to rise and satisfy the conduction condition of the first NMOS transistor Q4, thus turning on the first NMOS transistor Q4. The conduction of the first NMOS transistor Q4 grounds one end of the second voltage divider resistor R5, thereby dividing the voltage between the first voltage divider resistor R4 and the second voltage divider resistor R5, causing the gate-source G voltage VGS of the first PMOS transistor Q2 and the second PMOS transistor Q3 to satisfy the conduction condition, i.e., the first PMOS transistor Q2 and the second PMOS transistor Q3 are turned on. Therefore, the connected first power supply DC_IN, through the turned-on first PMOS transistors Q2 and Q3, causes the first power switch circuit 111 to output the first supply voltage DC_OUT. In addition, to prevent the large capacitor in the back-end load system connected to the first power switch circuit 111 in the mobile device from causing excessive instantaneous current and power failure when the first PMOS transistor Q2 and the second PMOS transistor Q3 conduct quickly, an RC delay circuit is formed by capacitor C1 and second voltage divider resistor R5 in this embodiment. The RC delay circuit plays a role in soft start-up, that is, to protect the system from power failure, thereby solving the above-mentioned power failure problem.

[0044] Figure 4 yes Figure 1 The circuit diagrams of the second power switch circuit and the first switching circuit in the corresponding embodiment are shown below. (Refer to...) Figure 2 and Figure 4 The power supply circuit 11 also includes a second power switch circuit 112, and the power switching circuit 12 includes a first switching circuit 121. The second power switch circuit 112 is used to output a second power supply voltage TYPEC_OUT according to the connected second power supply TYPEC_IN. The first switching circuit 121 is electrically connected to the second power switch circuit 112, and the first switching circuit 121 is configured such that when the first power supply DC_IN is connected to the multi-power supply circuit 10, the second power switch circuit 112 does not output the second power supply voltage TYPEC_OUT.

[0045] Continue to refer to Figure 4The second power switch circuit 112 includes a reverse current protection sub-circuit 1121 and a switch sub-circuit 1122. The reverse current protection sub-circuit 1121 is used to output a second supply voltage TYPEC_OUT according to the input second power supply TYPEC_IN, and prevent voltage from flowing back from the output terminal of the second power switch circuit 112 (i.e., the port that outputs the second supply voltage TYPEC_OUT) to the corresponding input terminal (i.e., the port that inputs the second power supply TYPEC_IN). Preferably, the reverse current protection circuit 1121 includes a first PMOS transistor Q5, a second PMOS transistor Q6, a first voltage divider resistor R8, a second voltage divider resistor R10, and a capacitor C2. Specifically, the drain (D) of the first PMOS transistor Q5 is connected to the second power supply TYPEC_IN. The source (S) of the second PMOS transistor Q6 is connected to the source (S) of the first PMOS transistor Q5. The gate (G) of the second PMOS transistor Q6 is connected to the gate (G) of the first PMOS transistor Q5. The two ends of the first voltage divider resistor R8 are connected to the source (S) and gate (G) of the second PMOS transistor Q6, respectively. One end of the second voltage divider resistor R10 is connected to the gate (G) of the second PMOS transistor Q6. The capacitor C2 is connected in parallel with the first voltage divider resistor R8. The switching sub-circuit 1122 is used to enable the anti-reverse-current circuit 1121 to output the second supply voltage TYPEC_OUT when the second power supply TYPEC_IN is connected, and to prevent the anti-reverse-current circuit 1121 from outputting the second supply voltage TYPEC_OUT when the second power supply TYPEC_IN is not connected. Preferably, the switching sub-circuit 1122 includes a third voltage divider resistor R9, a fourth voltage divider resistor R12, and a first NMOS transistor Q7. Specifically, one end of the third voltage divider resistor R9 is connected to the second power supply TYPEC_IN, one end of the fourth voltage divider resistor R12 is grounded, the gate 1 of the first NMOS transistor Q7 is connected to the other ends of the third voltage divider resistor R9 and the fourth voltage divider resistor R12, the drain 3 of the first NMOS transistor Q7 is connected to the other end of the second voltage divider resistor R10, and the source 2 of the first NMOS transistor Q7 is grounded. It should be noted that the anti-reverse current injection sub-circuit 1121 and the switch sub-circuit 1122 have the same structure as the anti-reverse current injection sub-circuit 1111 and the switch sub-circuit 1112 in this embodiment, therefore their corresponding functions and working principles are the same, and will not be repeated here.

[0046] Continue to refer to Figure 4The first switching circuit 121 includes a fifth voltage divider resistor R11, a sixth voltage divider resistor R19, and a second NMOS transistor Q8. Specifically, one end of the fifth voltage divider resistor R11 is connected to the first power supply DC_IN, one end of the sixth voltage divider resistor R19 is grounded, the gate 1 of the second NMOS transistor Q8 is connected to the other ends of the fifth voltage divider resistor R11 and the sixth voltage divider resistor R19, the drain 3 of the second NMOS transistor Q8 is connected to the other end of the corresponding third voltage divider resistor R9, and the source 2 of the second NMOS transistor Q8 is grounded. The control principle of the first switching circuit 121 on the second power switch circuit 112 is as follows: When the first power supply DC_IN is connected, the voltage at the end of the sixth voltage divider resistor R19 connected to the gate 1 of the second NMOS transistor Q8 rises and reaches the conduction condition of the second NMOS transistor Q8, causing the second NMOS transistor Q8 to conduct. This, in turn, grounds the gate 1 of the first NMOS transistor Q7, preventing the first NMOS transistor Q7 from reaching the conduction condition when the second power supply TYPEC_IN is connected. Consequently, the second power switch circuit 112 cannot output the second supply voltage TYPEC_OUT. Therefore, the first switching circuit 121 achieves priority control between the first power supply DC_IN and the second power supply TYPEC_IN using simple electrical components. Furthermore, this priority control does not use integrated circuit chips or other software control, achieving simple and reliable hardware-level control and reducing the corresponding equipment cost.

[0047] Figure 5 yes Figure 1 The circuit diagrams of the third power switch circuit, the second switching circuit, and the third switching circuit in the corresponding embodiment are shown below. (Refer to...) Figure 2 and Figure 5 The power supply circuit 11 also includes a third power switch circuit 113, and the power switching circuit 12 also includes a second switching circuit 122 and a third switching circuit 123. The third power switch circuit 113 outputs a third power supply voltage POE_OUT based on the connected third power supply POE_IN. The second switching circuit 122 is electrically connected to the third power switch circuit 113. The second switching circuit 122 is configured such that when the second switching circuit 122 is connected to the first power supply DC_IN (i.e., when the multi-power supply circuit is connected to the first power supply DC_IN), the third power switch circuit 113 does not output the third power supply voltage POE_OUT. The third switching circuit 123 is electrically connected to the third power switch circuit 113. The third switching circuit 123 is configured such that when the third switching circuit 123 is connected to the second power supply TYPEC_IN (i.e., when the multi-power supply circuit is connected to the second power supply TYPEC_IN), the third power switch circuit 113 does not output the third power supply voltage POE_OUT.

[0048] Continue to refer to Figure 5The third power switch circuit 113 includes a reverse current protection sub-circuit 1131 and a switch sub-circuit 1132. The reverse current protection sub-circuit 1131 is used to output a third supply voltage POE_OUT based on the input third power supply POE_IN, and to prevent voltage from flowing back from the output terminal of the third power switch circuit 113 (i.e., the port that outputs the third supply voltage POE_OUT) to the corresponding input terminal (i.e., the port that inputs the third power supply POE_IN). Preferably, the reverse current protection circuit 1131 includes a first PMOS transistor Q9, a second PMOS transistor Q10, a first voltage divider resistor R13, a second voltage divider resistor R15, and a capacitor C3. Specifically, the drain (D) of the first PMOS transistor Q9 is connected to the third power supply POE_IN. The source (S) of the second PMOS transistor Q10 is connected to the source (S) of the first PMOS transistor Q9, and the gate (G) of the second PMOS transistor Q10 is connected to the gate (G) of the first PMOS transistor Q9. The two ends of the first voltage divider resistor R13 are connected to the source (S) and gate (G) of the second PMOS transistor Q10, respectively. One end of the second voltage divider resistor R15 is connected to the gate (G) of the second PMOS transistor Q10. The capacitor C3 is connected in parallel with the first voltage divider resistor R13. The switching sub-circuit 1132 is used to enable the anti-reverse current circuit 1131 to output the third supply voltage POE_OUT when the third power supply POE_IN is connected, and to prevent the anti-reverse current circuit 1131 from outputting the third supply voltage POE_OUT when the third power supply POE_IN is not connected. Preferably, the switching sub-circuit 1132 includes a third voltage divider resistor R14, a fourth voltage divider resistor R18, and a first NMOS transistor Q12. Specifically, one end of the third voltage divider resistor R14 is connected to the third power supply POE_IN, one end of the fourth voltage divider resistor R18 is grounded, the gate 1 of the first NMOS transistor Q12 is connected to the other ends of the third voltage divider resistor R14 and the fourth voltage divider resistor R18, the drain 3 of the first NMOS transistor Q12 is connected to the other end of the second voltage divider resistor R15, and the source 2 of the first NMOS transistor Q12 is grounded. It should be noted that the anti-reverse current injection sub-circuit 1131 and the switch sub-circuit 1132 have the same structure as the anti-reverse current injection sub-circuit 1111 and the switch sub-circuit 1112 in this embodiment, therefore their corresponding functions and working principles are the same and will not be repeated here.

[0049] Continue to refer to Figure 5The second switching circuit 122 includes a fifth voltage divider resistor R16, a sixth voltage divider resistor R17, and a second NMOS transistor Q13. Specifically, one end of the fifth voltage divider resistor R16 is connected to the first power supply DC_IN, one end of the sixth voltage divider resistor R17 is grounded, the gate 1 of the second NMOS transistor Q13 is connected to the other ends of the fifth voltage divider resistor R16 and the sixth voltage divider resistor R17, the drain 3 of the second NMOS transistor Q13 is connected to the other end of the corresponding third voltage divider resistor R14, and the source 2 of the second NMOS transistor Q13 is grounded. The third switching circuit 123 includes a fifth voltage divider resistor R21, a sixth voltage divider resistor R20, and a second NMOS transistor Q11. Specifically, one end of the fifth voltage divider resistor R21 is connected to the first power supply TYPEC_IN, one end of the sixth voltage divider resistor R20 is grounded, the gate 1 of the second NMOS transistor Q11 is connected to the other ends of the fifth voltage divider resistor R21 and the sixth voltage divider resistor R20 respectively, the drain 3 of the second NMOS transistor Q11 is connected to the other end of the corresponding third voltage divider resistor R14, and the source 2 of the second NMOS transistor Q11 is grounded. It should be noted that the circuit structure of the second switching circuit 122 and the third power switch circuit 113 is the same as that of the first switching circuit 121 and the second power switch circuit 112, so their functions and working principles are also the same. Here, we will only briefly explain: when the first power supply DC_IN is connected, the second NMOS transistor Q13 is turned on, which grounds the gate 1 of the first NMOS transistor Q12, thereby preventing the connected third power supply POE_IN from outputting the third supply voltage POE_OUT through the anti-reverse current circuit 1131. Furthermore, the circuit structures of the third switching circuit 123 and the third power switch circuit 113 are the same as those of the first switching circuit 121 and the second power switch circuit 112, and therefore their functions and working principles are also the same. Only a brief explanation is needed here: When the second power supply TYPEC_IN is connected, the second NMOS transistor Q11 is turned on, grounding the gate 1 of the first NMOS transistor Q12. This prevents the connected third power supply POE_IN from outputting the third supply voltage POE_OUT through the anti-reverse current circuit 1131. Thus, priority control between the first power supply DC_IN and the third power supply POE_IN can be achieved through the second switching circuit 122, and priority control between the second power supply TYPEC_IN and the third power supply POE_IN can be achieved through the third switching circuit 123. In conjunction with the priority control between the first power supply DC_IN and the second power supply TYPEC_IN implemented by the first switching circuit 121 as described in the previous embodiment, this embodiment implements the priority order of power supply switching from high to low as the first power supply DC_IN, the second power supply TYPEC_IN and the third power supply POE_IN through the power supply switching circuit 12. This avoids the problem of the multi-power supply circuit 10 failing to output the rated voltage effectively when two or more power supplies are connected at the same time.

[0050] Continue to refer to Figure 2 The BUCK circuit 114 is used to convert the first supply voltage DC_OUT, the second supply voltage TYPEC_OUT, and / or the third supply voltage POE_OUT to a rated voltage, wherein the first supply voltage, the second supply voltage, and the third supply voltage can be the same or different. For example, if the first supply voltage DC_OUT is 24V, the second supply voltage TYPEC_OUT is 20V, and the third supply voltage POE_OUT is 12V, and the rated voltage is 12V, then the BUCK circuit 114 will convert the first supply voltage DC_OUT and the second supply voltage TYPEC_OUT to their respective rated voltages. It should be noted that... Figure 2 The BUCK circuit 114 is electrically connected to the first power switch circuit 111 and the second power switch circuit 112 respectively. This is only an example for the case where both the first power supply voltage DC_OUT and the second power supply voltage TYPEC_OUT need to be converted. Correspondingly, in other embodiments, the BUCK circuit 114 can be electrically connected to any one or more of the first power switch circuit 111, the second power switch circuit 112 and the third power switch circuit 113 as needed, thereby realizing the conversion of the power supply voltage.

[0051] Continue to refer to Figure 1 The first INT signal trigger circuit 13 outputs a first INT signal when the first power supply DC_IN is connected; the second INT signal trigger circuit 14 outputs a second INT signal when the second power supply TYPEC_IN is connected; and the third INT signal trigger circuit 15 outputs a third INT signal when the third power supply POE_IN is connected. Further reference... Figure 6The first INT signal trigger circuit 13 includes a seventh voltage divider resistor R1, an eighth voltage divider resistor R2, a third NMOS transistor Q1, and a ninth resistor R3. Specifically, one end of the seventh voltage divider resistor R1 is connected to the first power supply DC_IN, one end of the eighth voltage divider resistor R2 is grounded, the gate 1 of the third NMOS transistor Q1 is connected to the other ends of the seventh voltage divider resistor R1 and the eighth voltage divider resistor R2 respectively, the source 2 of the third NMOS transistor Q1 is grounded, one end of the ninth resistor R3 is connected to a fixed level V10, and the other end of the ninth resistor R3 is connected to the drain 3 of the third NMOS transistor Q1. According to the above circuit structure, when the first INT signal trigger circuit 13 is connected to the first power supply DC_IN, the other end of the ninth resistor R3, i.e., the end connected to the drain 3 of the third NMOS transistor Q1, is at a low level, and this low level is the first INT signal INT1. It should be noted that the first INT signal triggering circuit 13, the second INT signal triggering circuit 14, and the third INT signal triggering circuit 15 in this embodiment have the same circuit structure. Therefore, the specific structure of the second INT signal triggering circuit 14 and the third INT signal triggering circuit 15, as well as their identical working principle and effects, will not be repeated here.

[0052] This application also proposes a mobile device with a multi-power supply circuit 10, which is adapted to be powered by a first power supply, a second power supply, and a third power supply. (Refer to...) Figure 7 The mobile device 100 includes a multi-power supply circuit 10, a first power interface 20, a second power interface 30, a third power interface 40, a CPU main control module 50, and a display module 60. The first power interface 20 is used to connect to a first power supply DC_IN, the second power interface 30 is used to connect to a second power supply TYPEC_IN, and the third power interface 40 is used to connect to a third power supply POE_IN. The output terminals of the first power interface 20, the second power interface 30, and the third power interface 40 are electrically connected to the input terminals of the multi-power supply circuit 10. Specifically, refer to... Figure 1 , Figure 2 and Figure 7 The output terminal of the first power interface 20 is connected to the input terminal of the first power switch circuit 111, the input terminal of the first switching circuit 121, the input terminal of the second switching circuit 122, and the input terminal of the first INT signal trigger circuit 13, respectively. The output terminal of the second power interface 30 is connected to the input terminal of the second power switch circuit 112, the input terminal of the third switching circuit 123, and the input terminal of the second INT signal trigger circuit 14, respectively. The output terminal of the third power interface 40 is connected to the input terminal of the third power switch circuit 113 and the input terminal of the third INT signal trigger circuit 15, respectively.

[0053] Preferably, for the second adapter that supports the Power Delivery protocol and the Type-C interface, the second power interface 30 is a Type-C interface. Preferably, for the third adapter that supports the Power over Ethernet protocol, the third power interface 40 is an RJ45 interface. The mobile device 100 supports multiple power sources simultaneously. Therefore, when there is a first power source DC_IN and / or a second power source TYPEC_IN other than the third power source POE_IN, the third power interface 40 can realize network communication functions. When the first power source DC_IN and / or the second power source TYPEC_IN cannot provide power, the multi-power supply circuit 10 immediately switches to the third power source POE_IN, thereby ensuring the normal operation of the mobile device 100. It should be noted that in this embodiment, the mobile device 100 is a POS machine. This POS machine can be used handheld or fixed in a certain position. When it is fixed in a certain position, it can be conveniently connected to multiple power sources for use. However, in other embodiments, this POS machine can also be handheld and connected to multiple power sources at the same time, or the mobile device 100 may be other devices that require stable power supply.

[0054] Continue to refer to Figure 1 and Figure 7The CPU main control module 50 is configured to acquire the first INT signal corresponding to the first INT signal triggering circuit 13, the second INT signal corresponding to the second INT signal triggering circuit 14, and the third INT signal corresponding to the third INT signal triggering circuit 15. It should be noted that in this embodiment, the multi-power supply circuit 10 includes the first INT signal triggering circuit 13, the second INT signal triggering circuit 14, and the third INT signal triggering circuit 15, but in other embodiments, it may include any one or more of these circuits. Preferably, when the multi-power supply circuit 10 includes the third INT signal triggering circuit 15, the CPU main control module 50 is configured to disable the high-power function of the mobile device 100 after receiving the third INT signal. When the high-power function is running, the real-time power of the mobile device 100 is higher than the rated power corresponding to the rated voltage, and the third power supply POE_IN corresponding to the third INT signal has a weak power supply capability, i.e., it is not suitable for running the high-power function. Therefore, it is necessary to disable the high-power function to avoid power failure during the third power supply POE_IN operation, which could damage the mobile device 100 or render it inoperable. Preferably, the high-power function includes a printer function. Preferably, the display module 60 is configured to display to the user that the high-power function is unavailable after the CPU main control module 50 disables the high-power function, for example, displaying any one or more of the following prompts: text, voice, or image, such as "Current power supply does not support printing." Exemplarily, the CPU main control module 50 in this embodiment is an existing control motherboard, model QCS6490. It should be noted that other models of existing control motherboards can be used to implement the above functions in other embodiments; specific models will not be listed individually.

[0055] The basic concepts have been described above. Obviously, for those skilled in the art, the above disclosure is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0056] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0057] Some aspects of this application can be executed entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. The aforementioned hardware or software may be referred to as a "data block," "module," "engine," "unit," "component," or "system." The processor may be one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DAPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or combinations thereof. Furthermore, aspects of this application may manifest as computer products residing in one or more computer-readable media, including computer-readable program code. For example, computer-readable media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic tapes, etc.), optical discs (e.g., compressed CDs, digital multifunction DVDs, etc.), smart cards, and flash memory devices (e.g., cards, sticks, key drives, etc.).

[0058] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the present application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0059] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0060] Although this application has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are only used to illustrate this application, and various equivalent changes or substitutions can be made without departing from the spirit of this application. Therefore, any changes or modifications to the above embodiments within the essential spirit of this application will fall within the scope of the claims of this application.

Claims

1. A multiple power supply power supply circuit, characterized by comprising: The multi-power supply circuit, adapted to perform power switching between a first power supply, a second power supply, and a third power supply and to power mobile devices, includes: The power switching circuit is configured such that: when the mobile device is simultaneously connected to any two or more of the first power source, the second power source, and the third power source, one of the first power source, the second power source, or the third power source is selected as the power supply according to the priority order; when the mobile device is only connected to any one of the first power source, the second power source, and the third power source, the connected first power source, the second power source, or the third power source is selected as the power supply. The power supply circuit is used to supply power to the mobile device by outputting a rated voltage according to the connected power supply. The first power supply is provided by the original first adapter of the mobile device, the second power supply is provided by the second adapter based on Universal Serial Bus (USB) power supply, and the third power supply is provided by the third adapter based on Ethernet cable power supply. The priority order from high to low is the first power supply, the second power supply, and the third power supply.

2. The multiple power supply power supply circuit of claim 1, wherein, The second adapter is an adapter that uses the PowerDelivery protocol and a Type-C interface.

3. The multiple power supply power supply circuit of claim 1, wherein, The Ethernet cable-based adapter is an adapter that uses the Power over Ethernet protocol.

4. The multiple power supply power supply circuit of claim 1, wherein, The power supply circuit includes: The first power switch circuit is used to output a first power supply voltage according to the first power supply connected to it; The second power switch circuit is used to output a second power supply voltage according to the second power supply connected to it; The third power switch circuit is used to output a third power supply voltage according to the connected third power supply; A BUCK circuit is used to convert the first supply voltage, the second supply voltage, and / or the third supply voltage into the rated voltage, wherein the first supply voltage, the second supply voltage, and the third supply voltage may be the same or different.

5. The multiple power supply power supply circuit of claim 4, wherein, The power switching circuit includes: The first switching circuit is electrically connected to the second power switch circuit. The first switching circuit is configured such that when the first switching circuit is connected to the first power supply, the second power switch circuit does not output the second power supply voltage. The second switching circuit is electrically connected to the third power switch circuit. The second switching circuit is configured such that when the second switching circuit is connected to the first power source, the third power switch circuit does not output the third power supply voltage; and The third switching circuit is electrically connected to the third power switch circuit. The third switching circuit is configured such that when the third switching circuit is connected to the second power supply, the third power switch circuit does not output the third power supply voltage.

6. The multiple power supply power supply circuit of claim 5, wherein, The first power switch circuit, the second power switch circuit, and the third power switch circuit all include: The anti-reverse flow circuit is used to output the first supply voltage, the second supply voltage, or the third supply voltage according to the first power supply, the second power supply, or the third power supply connected to it, and to prevent the voltage from flowing back from the output terminal of the first power switch circuit, the second power switch circuit, or the third power switch circuit to the corresponding input terminal.

7. The multiple power supply power supply circuit of claim 6, wherein, The first power switch circuit, the second power switch circuit, and the third power switch circuit all further include: The switching sub-circuit is used to enable the anti-reverse current circuit to output the first supply voltage, the second supply voltage, or the third supply voltage when the first power supply, the second power supply, or the third power supply is connected, and to enable the anti-reverse current circuit to not output the first supply voltage, the second supply voltage, or the third supply voltage when the first power supply, the second power supply, or the third power supply is not connected.

8. The multiple power supply power supply circuit of claim 7, wherein, The anti-reverse injection circuit includes: The drain of the first PMOS transistor is connected to the first power supply, the second power supply, or the third power supply. The second PMOS transistor has its source connected to the source of the first PMOS transistor, and its gate connected to the gate of the first PMOS transistor. The first voltage divider resistor is connected to the source and gate of the second PMOS transistor, respectively. The second voltage divider resistor has one end connected to the gate of the second PMOS transistor. When the other end of the second voltage divider resistor is grounded by the switching sub-circuit, the drain of the second PMOS transistor outputs the first supply voltage, the second supply voltage, or the third supply voltage.

9. The multiple power supply power supply circuit of claim 8, wherein, The anti-reverse-flush circuit also includes a capacitor connected in parallel with the first voltage divider resistor.

10. The multiple power supply power supply circuit of claim 8, wherein, The switching sub-circuit includes: The third voltage divider resistor, one end of which is connected to the first power supply, the second power supply, or the third power supply; The fourth voltage divider resistor, one end of which is grounded; The first NMOS transistor has its gate connected to the other end of the third voltage divider resistor and the other end of the fourth voltage divider resistor, its drain connected to the other end of the second voltage divider resistor, and its source grounded.

11. The multiple power supply power supply circuit of claim 10, wherein, The first switching circuit is electrically connected to the switching sub-circuit of the second power switch circuit, and the second switching circuit and the third switching circuit are respectively electrically connected to the switching sub-circuit of the third power switch circuit. The first switching circuit, the second switching circuit, and the third switching circuit each include: The fifth voltage divider resistor, one end of which is connected to the first power supply or the second power supply; The sixth voltage divider resistor, one end of which is grounded; The second NMOS transistor has its gate connected to the other end of the fifth voltage divider resistor and the other end of the sixth voltage divider resistor, respectively. The drain of the second NMOS transistor is connected to the other end of the corresponding third voltage divider resistor, and the source of the second NMOS transistor is grounded.

12. The multiple power supply power supply circuit of claim 1, wherein, The multi-power supply circuit also includes: The first INT signal trigger circuit is used to output the first INT signal when the first power supply is connected; The second INT signal trigger circuit is used to output the second INT signal when the second power supply is connected; The third INT signal trigger circuit is used to output the third INT signal when the third power supply is connected.

13. The multi-power supply circuit as described in claim 12, characterized in that, The first INT signal trigger circuit, the second INT signal trigger circuit, and the third INT signal trigger circuit all include: The seventh voltage divider resistor, one end of which is connected to the first power supply, the second power supply, or the third power supply; The eighth voltage divider resistor, one end of which is grounded; The third NMOS transistor has its gate connected to the other end of the seventh voltage divider resistor and the other end of the eighth voltage divider resistor, respectively, and its source is grounded. The ninth resistor has one end connected to a fixed voltage level and the other end connected to the drain of the third NMOS transistor. When the first power supply, the second power supply, or the third power supply is connected, the other end of the ninth resistor is at a low level, and the low level is used as the first INT signal, the second INT signal, or the third INT signal.

14. A mobile device, comprising: Suitable for being powered by a first power source, a second power source, and a third power source, including: The first power interface is used to connect to the first power source; The second power interface is used to connect the second power source; A third power interface is used to connect the third power source; and The multi-power supply circuit according to any one of claims 1-13, wherein the output terminal of the first power interface, the output terminal of the second power interface and the output terminal of the third power interface are respectively electrically connected to the input terminal of the multi-power supply circuit.

15. The mobile device of claim 14, wherein, The second adapter is an adapter that uses the PowerDelivery protocol and a Type-C interface, and the second power interface is a Type-C interface; The third adapter is an adapter that uses the Power over Ethernet protocol, and the third power interface is an RJ45 interface.

16. The mobile device of claim 14, wherein, The multi-power supply circuit includes a first power switch circuit, a second power switch circuit, and a third power switch circuit. The output terminal of the first power interface is electrically connected to the input terminal of the first power switch circuit, the second power switch circuit is electrically connected to the input terminal of the second power switch circuit, and the output terminal of the third power interface is electrically connected to the input terminal of the third power switch circuit.

17. The mobile device of claim 14, wherein, The mobile device also includes a CPU main control module; The multi-power supply circuit further includes at least one of the first INT signal triggering circuit, the second INT signal triggering circuit, and the third INT signal triggering circuit. The CPU main control module is configured to acquire the first INT signal corresponding to the first INT signal triggering circuit, the second INT signal corresponding to the second INT signal triggering circuit, and / or the third INT signal corresponding to the third INT signal triggering circuit.

18. The mobile device of claim 17, wherein, When the multi-power supply circuit includes the third INT signal trigger circuit, the CPU main control module is configured to turn off the high-power function of the mobile device after receiving the third INT signal, wherein when the high-power function is running, the real-time power of the mobile device is higher than the rated power corresponding to the rated voltage.

19. The mobile device of claim 18, wherein, The high-power function includes a printer function.

20. The mobile device of claim 18, wherein, The mobile device also includes a display module, which is configured to display to the user that the high-power function is unavailable after the CPU main control module disables the high-power function.

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