Control circuit and image sensor

Abstract

This invention provides a control circuit and an image sensor. The control circuit includes at least one control group. The control group includes an nth control unit and an mth control unit, corresponding to the nth row of pixel units and the mth row of pixel units, respectively. Each control unit includes a first control module. Within the control group, the first control module in the i-th control unit operates in a first stage and, under the control of the n-th row address signal and the m-th row address signal, generates an overflow switch control signal for the i-th row based at least on a mode enable signal. Here, n and m are both natural numbers greater than or equal to 1, and i is either n or m. The control circuit and image sensor provided by this invention solve the technical problem of the lack of an effective driving scheme for dual-mode LOFIC pixel structures in the prior art.

Description

Technical Field

[0001] This utility model relates to the field of image sensor technology, and in particular to a control circuit and an image sensor. Background Technology

[0002] Dynamic range is a key factor in the imaging quality of image sensors, and a high dynamic range can output scene image information over a wider range of light intensities, presenting richer image details. With technological advancements, the demands on the dynamic range of image sensors are increasing, leading to the growing application of LOFIC pixel structures. Therefore, effectively driving LOFIC pixel structures to achieve LOFIC functionality has become crucial.

[0003] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this utility model and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this utility model. Utility Model Content

[0004] In view of the shortcomings of the prior art described above, the purpose of this utility model is to provide a control circuit and an image sensor to solve the technical problem that there is no effective driving scheme for dual-mode LOFIC pixel structure in the prior art.

[0005] To achieve the above and other related objectives, this utility model provides a control circuit, including at least one control group, wherein:

[0006] The control group includes an nth control unit and an mth control unit, corresponding to the nth row of pixel units and the mth row of pixel units, respectively. The control unit includes a first control module.

[0007] Within the control group, the first control module in the i-th control unit operates in the first stage and, under the control of the n-th row address signal and the m-th row address signal, generates the i-th row overflow switch control signal based at least on the mode enable signal; where n and m are both natural numbers greater than or equal to 1, and i is n or m.

[0008] Optionally, the first control module in the i-th control unit generates the i-th row overflow switch control signal based on the mode enable signal and the latch enable signal, wherein the first stage is the exposure stage and / or the idle stage.

[0009] Optionally, the first control module includes:

[0010] The first control section controls whether the overflow switch control signal of the i-th row is pulled to the first potential based on the latch enable signal;

[0011] The second control section controls whether the overflow switch control signal of the i-th row is pulled to the first potential based on the mode enable signal.

[0012] The third control section controls whether the overflow switch control signal of the i-th row is pulled to the second potential based on the latch enable signal and the mode enable signal.

[0013] Optionally, the first control section includes a first switch, a second switch, a third switch, and a fourth switch, wherein: the control terminal of the first switch receives the latch enable signal; the first terminal of the first switch is connected to a first potential line; the second terminal of the first switch is connected to the first terminal of the second switch; the control terminal of the second switch receives the first latch address signal of the i-th row; the second terminal of the second switch is connected to the first terminal of the third switch; the control terminal of the third switch receives the read address signal of the n-th row; the second terminal of the third switch is connected to the first terminal of the fourth switch; the control terminal of the fourth switch receives the read address signal of the m-th row; and the second terminal of the fourth switch is connected to a signal output line.

[0014] And / or, the second control section includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a ninth switch, wherein: the control terminal of the fifth switch receives the mode enable signal; the first terminal of the fifth switch is connected to a first potential line; the second terminal of the fifth switch is connected to the first terminal of the sixth switch; the control terminal of the sixth switch receives the second latch address signal of the i-th row; the second terminal of the sixth switch is connected to the first terminal of the seventh switch; the control terminal of the seventh switch receives the exposure address signal of the i-th row; the second terminal of the seventh switch is connected to the first terminal of the eighth switch; the control terminal of the eighth switch receives the readout address signal of the n-th row; the second terminal of the eighth switch is connected to the first terminal of the ninth switch; the control terminal of the ninth switch receives the readout address signal of the m-th row; and the second terminal of the ninth switch is connected to a signal output line.

[0015] And / or, the third control section includes a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch, wherein: the control terminal of the tenth switch receives the inverted signal of the exposure address signal of the i-th row; the first terminal of the tenth switch is connected to the second terminal of the eleventh switch; the second terminal of the tenth switch is connected to a signal output line; the control terminal of the eleventh switch receives the inverted signal of the readout address signal of the n-th row; the first terminal of the eleventh switch is connected to the second terminal of the twelfth switch; the control terminal of the twelfth switch receives the inverted signal of the readout address signal of the m-th row; the first terminal of the twelfth switch... The second terminals of the thirteenth and fourteenth switches are respectively connected. The control terminal of the thirteenth switch receives the first latch address signal of the i-th row. The first terminal of the thirteenth switch is respectively connected to the second terminals of the fifteenth and sixteenth switches. The control terminal of the fourteenth switch receives the latch enable signal. The first terminal of the fourteenth switch is connected to the second terminal of the sixteenth switch. The control terminal of the fifteenth switch receives the second latch address signal of the i-th row. The first terminal of the fifteenth switch is connected to the second potential line. The control terminal of the sixteenth switch receives the mode enable signal. The first terminal of the sixteenth switch is connected to the second potential line.

[0016] Optionally, the control unit further includes a second control module; wherein, within the control group, the second control module in the i-th control unit operates in the second stage and, under the control of the i-th row address signal, generates the i-th row overflow switch control signal based on the initial control signal of the second stage;

[0017] And / or, the control unit further includes a third control module; wherein, within the control group, the third control module in the i-th control unit operates in the third stage, and under the control of the i-th row address signal, generates the i-th row overflow switch control signal based on the initial control signal of the third stage;

[0018] And / or, the control group further includes two latch address units, denoted as the nth latch address unit and the mth latch address unit, which correspond to the first control modules in the nth control unit and the mth control unit, respectively, to generate the second latch address signal of the corresponding row based on the latch enable signal and the first latch address signal of the corresponding row;

[0019] And / or, m = n + 1.

[0020] Optionally, when the control unit includes a second control module, the second control module includes: a fourth control part, which controls whether the overflow switch control signal of the i-th row is pulled to a first potential based on the second stage initial control signal; and a fifth control part, which controls whether the overflow switch control signal of the i-th row is pulled to a second potential based on the second stage initial control signal.

[0021] And / or, when the control group further includes two latch address units, the two latch address units in the control group have the same structure, including a NOR gate, wherein: the first input of the NOR gate is connected to the latch enable signal, the second input of the NOR gate is connected to the first latch address signal of the corresponding row, and the output of the NOR gate generates the second latch address signal of the corresponding row.

[0022] Optionally, the fourth control section includes a seventeenth switch and an eighteenth switch, wherein: the control terminal of the seventeenth switch receives the inverted signal of the exposure address signal of the i-th row, the first terminal of the seventeenth switch is connected to the first potential line, the second terminal of the seventeenth switch is connected to the first terminal of the eighteenth switch, the control terminal of the eighteenth switch receives the second stage initial control signal, and the second terminal of the eighteenth switch is connected to the signal output line;

[0023] And / or, the fifth control section includes a nineteenth switch and a twentieth switch, wherein: the control terminal of the nineteenth switch receives the second stage initial control signal, the first terminal of the nineteenth switch is connected to the second terminal of the twentieth switch, the second terminal of the nineteenth switch is connected to the signal output line, the control terminal of the twentieth switch receives the exposure address signal of the i-th row, and the first terminal of the twentieth switch is connected to the second potential line.

[0024] Optionally, when the control unit includes a third control module, the third control module includes:

[0025] The sixth control section controls whether the overflow switch control signal of the i-th row is pulled to the first potential based on the initial control signal of the third stage;

[0026] The seventh control section controls whether the overflow switch control signal of the i-th row is pulled to the second or third potential based on the initial control signal of the third stage.

[0027] Optionally, the sixth control section includes a twenty-first switch and a twenty-second switch, wherein: the control terminal of the twenty-first switch receives the inverted signal of the read address signal of the i-th row, the first terminal of the twenty-first switch is connected to the first potential line, the second terminal of the twenty-first switch is connected to the first terminal of the twenty-second switch, the control terminal of the twenty-second switch receives the initial control signal of the third stage, and the second terminal of the twenty-second switch is connected to the signal output line.

[0028] The seventh control section includes a 23rd switch and a 24th switch, wherein: the control terminal of the 23rd switch receives the initial control signal of the third stage, the first terminal of the 23rd switch is connected to the second terminal of the 24th switch, the second terminal of the 23rd switch is connected to the signal output line, the control terminal of the 24th switch receives the read address signal of the i-th row, and the first terminal of the 24th switch is connected to the second potential line or the third potential line.

[0029] Optionally, the third control module further includes an eighth control section;

[0030] The eighth control section includes a 25th switch, wherein: the control terminal of the 25th switch receives the read address signal of another row, the first terminal of the 25th switch is connected to the second potential line or the third potential line, and the second terminal of the 25th switch is connected to the signal output line;

[0031] Alternatively, the eighth control section may further include a 26th switch, a 27th switch, and a 28th switch, wherein: the first terminal of the 25th switch is changed from being connected to the corresponding potential line to being connected to the second terminal of the 26th switch; the control terminal of the 26th switch receives a mode enable signal; the first terminal of the 26th switch is connected to a second potential line or a third potential line; the control terminal of the 27th switch receives a mode enable signal; the first terminal of the 27th switch is connected to a first potential line; the second terminal of the 27th switch is connected to the first terminal of the 28th switch; the control terminal of the 28th switch receives an inverted signal of the read address signal of another row; and the second terminal of the 28th switch is connected to a signal output line.

[0032] Optionally, the second stage includes a reset stage, and the third stage includes a readout stage.

[0033] This utility model also provides an image sensor, including:

[0034] A pixel circuit includes a plurality of pixel units arranged in an array, wherein the pixel units are dual-mode LOFIC pixel structures;

[0035] The control circuit described in any of the above provides corresponding overflow switch control signals to the pixel units of each row at least in the first stage.

[0036] Optionally, the pixel unit includes:

[0037] The first reset module is connected to the corresponding floating diffusion node and is used to perform a reset operation on at least the floating diffusion node.

[0038] A photosensitive module, connected to the floating diffusion node, is used to accumulate photogenerated electrons and at least transfer them to the floating diffusion node to output a pixel signal;

[0039] The overflow module includes a first overflow path and a second overflow path, which are respectively connected to both sides of the photosensitive module. In the first overflow mode, the overflowed photogenerated electrons are stored through the first overflow path to output an overflow signal. In the second overflow mode, the overflowed photogenerated electrons are stored through the second overflow path to output an overflow signal.

[0040] An output module, connected to the floating diffusion node, is used to amplify and output the corresponding signal;

[0041] Alternatively, the pixel unit may further include a gain module and / or a second reset module;

[0042] The gain module is connected to the floating diffusion node and is used to switch between different conversion gains;

[0043] The second reset module is connected to the overflow module and is used to at least reset the overflow module.

[0044] Optionally, the first reset module includes a first reset transistor, wherein: the control terminal of the first reset transistor receives a first reset control signal corresponding to the row, the first terminal of the first reset transistor is connected to the floating diffusion node, and the second terminal of the first reset transistor is connected to a fourth potential;

[0045] And / or, the photosensitive module includes a transmission transistor and a photosensitive element, wherein: the control terminal of the transmission transistor receives a transmission control signal for the corresponding row, the first terminal of the transmission transistor is connected to the floating diffusion node, and the second terminal of the transmission transistor is connected to a fifth potential via the photosensitive element;

[0046] And / or, the overflow module includes an overflow transistor, an overflow switch, and an overflow capacitor, wherein: the control terminal of the overflow transistor receives an overflow control signal; the first terminal of the overflow transistor is connected to the first terminal of the overflow capacitor; the second terminal of the overflow transistor is connected to the photosensitive module; the control terminal of the overflow switch receives an overflow switch control signal corresponding to the row; the first terminal of the overflow switch is connected to the floating diffusion node; the second terminal of the overflow switch is connected to the first terminal of the overflow capacitor; and the second terminal of the overflow capacitor is connected to a sixth potential; wherein the path where the overflow transistor is located is the first overflow path, and the path where the overflow switch is located is the second overflow path;

[0047] And / or, the output module includes a source follower transistor and a select transistor, wherein: the control terminal of the source follower transistor is connected to the floating diffusion node, the first terminal of the source follower transistor is connected to the second terminal of the select transistor, the second terminal of the source follower transistor is connected to a seventh potential, the control terminal of the select transistor receives a selection control signal for the corresponding row, and the first terminal of the select transistor is connected to the corresponding column line;

[0048] When the pixel unit includes a gain module, the gain module includes a first gain transistor, wherein: the control terminal of the first gain transistor receives a first gain control signal for the corresponding row, the first terminal of the first gain transistor is connected to an eighth potential, and the second terminal of the first gain transistor is connected to the floating diffusion node; or, the gain module further includes a second gain transistor, wherein: the first terminal of the first gain transistor is changed from being connected to the eighth potential to being connected to the second terminal of the second gain transistor, the control terminal of the second gain transistor receives a second gain control signal for the corresponding row, and the first terminal of the second gain transistor is connected to the eighth potential;

[0049] When the pixel unit includes a second reset module, the second reset module includes a second reset transistor, wherein: the control terminal of the second reset transistor receives a second reset control signal for the corresponding row, the first terminal of the second reset transistor is connected to a ninth potential, and the second terminal of the second reset transistor is connected to the second terminal of the overflow capacitor.

[0050] Optionally, when the overflow module includes an overflow switch, and the pixel unit includes a gain module and the gain module includes at least a first gain transistor, the first end of the overflow switch is changed from being connected to the floating diffusion node to being connected to the first end of the first gain transistor.

[0051] And / or, the pixel units in the nth row and the pixel units in the mth row constitute a pixel group; when the pixel unit includes a gain module and the gain module includes a first gain transistor: within the pixel group, in two pixel units in the same column, the first terminals of the two first gain transistors are changed from being connected to the eighth potential to being connected to each other; when the pixel unit includes a gain module and the gain module includes a second gain transistor: within the pixel group, in two pixel units in the same column, the first terminals of the two second gain transistors are changed from being connected to the eighth potential to being connected to each other.

[0052] As described above, the control circuit and image sensor of this utility model, through the design of the control module, can effectively drive the dual-mode LOFIC pixel structure, be compatible with two overflow modes, and also perform overflow switch control at each stage, thereby achieving smooth control of complex pixel structures. Attached Figure Description

[0053] Figure 1 The diagram shows a structural schematic of a control circuit.

[0054] Figure 2 This is a schematic diagram of another control circuit structure.

[0055] Figure 3 This is another schematic diagram of a control circuit.

[0056] Figure 4 The diagram shows the structure of an image sensor.

[0057] Figure 5 The diagram shows the structure of a pixel circuit.

[0058] Figure 6 Displayed as a truth table of mode enable and latch enable signals.

[0059] Figure 7 This is a schematic diagram of the first control module in the first overflow mode during the exposure stage.

[0060] Figure 8 The diagram shows the signal timing of the first control module in the latching state under the first overflow mode.

[0061] Figure 9 The diagram shows the signal timing of the first control module in the non-latched state under the first overflow mode.

[0062] Figure 10 This is a schematic diagram showing the equivalent state of the latch in the second overflow mode of the first control module during the exposure stage.

[0063] Figure 11The diagram shows the signal timing of the first control module in the latched state under the second overflow mode.

[0064] Figure 12 This is a schematic diagram showing the equivalent state of the first control module in the second overflow mode during the exposure stage, corresponding to the non-latch state.

[0065] Figure 13 The diagram shows the signal timing of the first control module in the non-latched state under the second overflow mode.

[0066] Figure 14 This is a schematic diagram showing the equivalent state of the latch in the first overflow mode of the first control module during the idle phase.

[0067] Figure 15 This is a schematic diagram showing the equivalent state of the latch in the second overflow mode of the first control module during the idle phase.

[0068] Figure 16 This is a schematic diagram showing the equivalent state of the first control module in the second overflow mode during the idle phase, corresponding to the non-latched state.

[0069] Component designation explanation

[0070] 10 Image Sensors

[0071] 100 Control Circuit

[0072] 100a Control Group

[0073] 110 Control Unit

[0074] 111 First Control Module

[0075] 111a First Control Section

[0076] 111b Second Control Section

[0077] 111c Third Control Section

[0078] 112 Second Control Module

[0079] 112a Fourth Control Section

[0080] 112b Fifth Control Section

[0081] 113 Third Control Module

[0082] 113a Sixth Control Section

[0083] 113b Seventh Control Section

[0084] 113c Eighth Control Section

[0085] 200-pixel circuit

[0086] 200a pixel group

[0087] 210 pixel unit

[0088] 211 First Reset Module

[0089] 212 Photosensitive Module

[0090] 213 Overflow Module

[0091] 214 Output Module

[0092] 215 Gain Module

[0093] 216 Second Reset Module Detailed Implementation

[0094] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.

[0095] Please see Figures 1 to 16 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this utility model. Therefore, the illustrations only show the components related to this utility model and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0096] Example 1

[0097] like Figure 1 As shown, this embodiment provides a control circuit 100, including at least one control group 100a; wherein, the control group 100a includes two control units 110, denoted as the nth control unit and the mth control unit, and respectively corresponding to the control of the nth row of pixel units and the mth row of pixel units, where n and m are both natural numbers greater than or equal to 1. In this embodiment, m = n + 1; in other implementations, the control units in the control group 100a can also be shared in other ways.

[0098] In this embodiment, the two control units 110 within the control group 100a have identical structures, including a first control module 111. Furthermore, it also includes at least one of a second control module 112 and a third control module 113; alternatively, it may include both a second control module 112 and a third control module 113.

[0099] Regarding the first control module 111:

[0100] Within control group 100a, the first control module 111 in the i-th control unit operates in the first stage. Under the control of the n-th row address signal and the m-th row address signal, it generates the i-th row overflow switch control signal based at least on the mode enable signal mode_en, and further generates the i-th row overflow switch control signal based on the mode enable signal mode_en and the latch enable signal lat_enb; where i is n or m. In practical applications, the first stage is the exposure stage and / or the idle stage. In this embodiment, the first stage is typically the exposure stage and the idle stage.

[0101] In one embodiment, the first control module 111 includes a first control part 111a, a second control part 111b, and a third control part 111c. Wherein:

[0102] The first control section 111a controls whether the overflow switch control signal of the i-th row is pulled to the first potential, such as the transmission power supply potential TXVDD, based on the latch enable signal lat_enb.

[0103] In one example, the first control section 111a includes a first switch M1, a second switch M2, a third switch M3, and a fourth switch M4. Specifically: the control terminal of the first switch M1 receives a latch enable signal lat_enb; the first terminal of the first switch M1 is connected to a first potential line to access a first potential; the second terminal of the first switch M1 is connected to the first terminal of the second switch M2; and the control terminal of the second switch M2 receives the first latch address signal of the i-th row (e.g., lat_add1). <n>At this point, i = n; for example, lat_add1<n+1> At this point (i = m = n + 1), the second terminal of the second switch M2 is connected to the first terminal of the third switch M3, and the control terminal of the third switch M3 receives the read address signal rp_add for the nth row. <n>The second terminal of the third switch M3 is connected to the first terminal of the fourth switch M4. The control terminal of the fourth switch M4 receives the read address signal rp_add for the m-th row.<n+1> The second terminal of the fourth switch M4 is connected to the signal output line to output the overflow switch control signal of the i-th row (e.g., OFSW). <n>In this case, i = n; for example, OFSW<n+1> (At this time, i = m = n + 1). In this example, the first switch M1, the second switch M2, the third switch M3, and the fourth switch M4 are PMOS transistors, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0104] The second control section 111b controls whether the overflow switch control signal of the i-th row is pulled to the first potential, for example, the transmission power supply potential TXVDD, based on the mode enable signal mode_en.

[0105] In one example, the second control section 111b includes a fifth switch M5, a sixth switch M6, a seventh switch M7, an eighth switch M8, and a ninth switch M9. Specifically: the control terminal of the fifth switch M5 receives the mode enable signal `mode_en`; the first terminal of the fifth switch M5 is connected to the first potential line to access the first potential; the second terminal of the fifth switch M5 is connected to the first terminal of the sixth switch M6; and the control terminal of the sixth switch M6 receives the second latch address signal of the i-th row (e.g., `lat_add2`). <n>In this case, i = n; for example, lat_add2<n+1> At this point, i = m = n + 1), the second terminal of the sixth switch M6 is connected to the first terminal of the seventh switch M7, and the control terminal of the seventh switch M7 receives the exposure address signal of the i-th row (e.g., sp_add). <n>In this case, i = n; for example, sp_add<n+1> At this point (i = m = n + 1), the second terminal of the seventh switch M7 is connected to the first terminal of the eighth switch M8, and the control terminal of the eighth switch M8 receives the read address signal rp_add for the nth row. <n>The second terminal of the eighth switch M8 is connected to the first terminal of the ninth switch M9. The control terminal of the ninth switch M9 receives the read address signal rp_add for the m-th row.<n+1> The second terminal of the ninth switch M9 is connected to the signal output line to output the overflow switch control signal of the i-th row (e.g., OFSW). <n>In this case, i = n; for example, OFSW<n+1> (At this time, i = m = n + 1). In this example, the fifth switch M5, the sixth switch M6, the seventh switch M7, the eighth switch M8, and the ninth switch M9 are PMOS transistors, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0106] The third control section 111c controls whether the overflow switch control signal of the i-th row is pulled to the second potential, for example, the first negative voltage potential NVDD1, based on the latch enable signal lat_enb and the mode enable signal mode_en.

[0107] In one example, the third control section 111c includes a tenth switch M10, an eleventh switch M11, a twelfth switch M12, a thirteenth switch M13, a fourteenth switch M14, a fifteenth switch M15, and a sixteenth switch M16. Specifically, the control terminal of the tenth switch M10 receives the inverted signal (e.g., sp_addb) of the exposure address signal for the i-th row. <n>In this case, i = n; for example, sp_addb<n+1> At this point, i = m = n + 1), the first terminal of the tenth switch M10 is connected to the second terminal of the eleventh switch M11, and the second terminal of the tenth switch M10 is connected to the signal output line to output the overflow switch control signal of the i-th row (e.g., OFSW). <n>In this case, i = n; for example, OFSW<n+1> At this point (i = m = n + 1), the control terminal of the eleventh switch M11 receives the inverted signal rp_addb of the read address signal for the nth row. <n>The first terminal of the eleventh switch M11 is connected to the second terminal of the twelfth switch M12. The control terminal of the twelfth switch M12 receives the inverted signal rp_addb of the read address signal of the m-th row.<n+1> The first terminal of the twelfth switch M12 is connected to the second terminal of the thirteenth switch M13 and the second terminal of the fourteenth switch M14, respectively. The control terminal of the thirteenth switch M13 receives the first latch address signal of the i-th row (e.g., lat_add1). <n>At this point, i = n; for example, lat_add1<n+1> At this point, i = m = n + 1), the first terminal of the thirteenth switch M13 is connected to the second terminal of the fifteenth switch M15 and the second terminal of the sixteenth switch M16, respectively. The control terminal of the fourteenth switch M14 receives the latch enable signal lat_enb, and the first terminal of the fourteenth switch M14 is connected to the second terminal of the sixteenth switch M16. The control terminal of the fifteenth switch M15 receives the second latch address signal of the i-th row (e.g., lat_add2). <n>In this case, i = n; for example, lat_add2<n+1> At this point (i = m = n + 1), the first terminal of the fifteenth switch M15 is connected to the second potential line to access the second potential. The control terminal of the sixteenth switch M16 receives the mode enable signal mode_en, and the first terminal of the sixteenth switch M16 is connected to the second potential line to access the second potential. In this example, the tenth switch M10, the eleventh switch M11, the twelfth switch M12, the thirteenth switch M13, the fourteenth switch M14, the fifteenth switch M15, and the sixteenth switch M16 are NMOS transistors, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0108] In practical applications, control group 100a also includes two latch address units 120, denoted as the nth latch address unit and the mth latch address unit, which correspond to the first control module 111 in the nth control unit and the mth control unit, respectively, to generate the second latch address signal for the corresponding row based on the latch enable signal lat_enb and the first latch address signal for the corresponding row. In this embodiment, the two latch address units 120 in control group 100a have the same structure, including a NOR gate, wherein: the first input of the NOR gate is connected to the latch enable signal lat_enb, the second input of the NOR gate is connected to the first latch address signal for the corresponding row, and the output of the NOR gate generates the second latch address signal for the corresponding row; taking the nth latch address unit as an example, the first input of the NOR gate is connected to the latch enable signal lat_enb, and the second input of the NOR gate is connected to the first latch address signal lat_add1 for the nth row. <n>The output of the NOR gate generates the second latch address signal lat_add2 for the nth row. <n>Taking the m-th latch address unit as an example, the first input of the NOR gate is connected to the latch enable signal lat_enb, and the second input of the NOR gate is connected to the first latch address signal lat_add1 of the m-th row.<n+1> The output of the NOR gate generates the second latch address signal lat_add2 for the m-th row.<n+1> .

[0109] Regarding the second control module 112:

[0110] Within control group 100a, the second control module 112 in the i-th control unit operates in the second stage and, under the control of the i-th row address signal, generates the i-th row overflow switch control signal based on the second stage initial control signal sp_ofswb. In practical applications, the second stage includes a reset stage; as an optional scheme, this reset stage is a global reset stage.

[0111] In one embodiment, the second control module 112 includes a fourth control section 112a and a fifth control section 112b.

[0112] in:

[0113] The fourth control section 112a controls whether the overflow switch control signal of the i-th row is pulled to the first potential, for example, the transmission power supply potential TXVDD, based on the second-stage initial control signal sp_ofswb.

[0114] In one example, the fourth control section 112a includes a seventeenth switch M17 and an eighteenth switch M18. Specifically, the control terminal of the seventeenth switch M17 receives the inverted signal of the exposure address signal for the i-th row (e.g., sp_addb). <n>In this case, i = n; for example, sp_addb<n+1> At this point, i = m = n + 1), the first terminal of the seventeenth switch M17 is connected to the first potential line to access the first potential, the second terminal of the seventeenth switch M17 is connected to the first terminal of the eighteenth switch M18, the control terminal of the eighteenth switch M18 receives the second-stage initial control signal sp_ofswb, and the second terminal of the eighteenth switch M18 is connected to the signal output line to output the overflow switch control signal of the i-th row (e.g., OFSW). <n>In this case, i = n; for example, OFSW<n+1> (At this time, i = m = n + 1). In this example, the seventeenth switch M17 and the eighteenth switch M1 are PMOS transistors, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0115] The fifth control section 112b controls whether the overflow switch control signal of the i-th row is pulled to the second potential, for example, the first negative voltage potential NVDD1, based on the second-stage initial control signal sp_ofswb.

[0116] In one example, the fifth control section 112b includes a nineteenth switch M19 and a twentieth switch M20. Specifically: the control terminal of the nineteenth switch M19 receives the second-stage initial control signal sp_ofswb; the first terminal of the nineteenth switch M19 is connected to the second terminal of the twentieth switch M20; and the second terminal of the nineteenth switch M19 is connected to a signal output line to output the overflow switch control signal (e.g., OFSW) for the i-th row. <n>In this case, i = n; for example, OFSW<n+1> At this point, i = m = n + 1), the control terminal of the twentieth switch M20 receives the exposure address signal for the i-th row (e.g., sp_add). <n>In this case, i = n; for example, sp_add<n+1> At this point, i = m = n + 1), the first terminal of the twentieth switch M20 is connected to the second potential line to access the second potential. In this example, the nineteenth switch M19 and the twentieth switch M20 are NMOS transistors, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0117] Regarding the third control module 113:

[0118] Within control group 100a, the third control module 113 in the i-th control unit operates in the third stage and, under the control of the i-th row address signal, generates the i-th row overflow switch control signal based on the initial control signal rp_ofswb of the third stage. In practical applications, the third stage includes a readout stage.

[0119] In one embodiment, the third control module 113 includes a sixth control section 113a and a seventh control section 113b, and further includes an eighth control section 113c, such as... Figure 2 and Figure 3 As shown. Wherein:

[0120] The sixth control section 113a controls whether the overflow switch control signal of the i-th row is pulled to the first potential, for example, the transmission power supply potential TXVDD, based on the initial control signal rp_ofswb of the third stage.

[0121] In one example, the sixth control section 113a includes a twenty-first switch M21 and a twenty-second switch M22. Specifically, the control terminal of the twenty-first switch M21 receives the inverted signal of the read address signal for the i-th row (e.g., rp_addb). <n>At this point, i = n; for example, rp_addb<n+1> At this point, i = m = n + 1), the first terminal of the twenty-first switch M21 is connected to the first potential line to access the first potential, the second terminal of the twenty-first switch M21 is connected to the first terminal of the twenty-second switch M22, the control terminal of the twenty-second switch M22 receives the third-stage initial control signal rp_ofswb, and the second terminal of the twenty-second switch M22 is connected to the signal output line to output the overflow switch control signal of the i-th row (e.g., OFSW). <n>In this case, i = n; for example, OFSW<n+1> (At this time, i = m = n + 1). In this example, the twenty-first switch M21 and the twenty-second switch M22 are PMOS transistors, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0122] The seventh control section 113b controls whether the overflow switch control signal of the i-th row is pulled to the second potential, for example, the first negative voltage potential NVDD1, based on the initial control signal rp_ofswb of the third stage.

[0123] In one example, the seventh control section 113b includes a twenty-third switch M23 and a twenty-fourth switch M24. Specifically: the control terminal of the twenty-third switch M23 receives the third-stage initial control signal rp_ofswb; the first terminal of the twenty-third switch M23 is connected to the second terminal of the twenty-fourth switch M24; and the second terminal of the twenty-third switch M23 is connected to the signal output line to output the overflow switch control signal (e.g., OFSW) for the i-th row. <n>In this case, i = n; for example, OFSW<n+1> At this point, i = m = n + 1), the control terminal of the 24th switch M24 receives the read address signal of the i-th row (e.g., rp_add). <n>At this point, i = n; for example, rp_add<n+1> At this point (i = m = n + 1), the first terminal of the twenty-fourth switch M24 is connected to the second potential line to access the second potential. In this example, the twenty-third switch M23 and the twenty-fourth switch M24 are NMOS transistors, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0124] To provide an alternative control scheme, an eighth control section 113c is added to the third control module 113, such as... Figure 2 and Figure 3 As shown; wherein: this alternative control scheme can be provided only in the first overflow mode (e.g., OFG overflow mode), or it can be provided simultaneously in the first overflow mode (e.g., OFG overflow mode) and the second overflow mode (non-OFG overflow mode). When provided only in the first overflow mode, as Figure 2 As shown, the eighth control section 113c includes a twenty-fifth switch transistor M25; wherein: the control terminal of the twenty-fifth switch transistor M25 receives the read address signal of another row (e.g., rp_add).<n+1> At this point, i = n; for example, rp_add <n>At this time, i = m = n + 1), the first terminal of the 25th switch M25 is connected to the second potential line to access the second potential, and the second terminal of the 25th switch M25 is connected to the signal output line. When provided simultaneously in the first overflow mode and the second overflow mode, such as Figure 3 As shown, the eighth control section 113c includes, in addition to the twenty-fifth switch M25, the twenty-sixth switch M26, the twenty-seventh switch M27, and the twenty-eighth switch M28; wherein: the control terminal of the twenty-fifth switch M25 receives the read address signal of another row (e.g., rp_add).<n+1> At this point, i = n; for example, rp_add <n>At this time, i = m = n + 1), the first terminal of the 25th switch M25 is connected to the second terminal of the 26th switch M26, the second terminal of the 25th switch M25 is connected to the signal output line, the control terminal of the 26th switch M26 receives the mode enable signal mode_en, the first terminal of the 26th switch M26 is connected to the second potential line to access the second potential, the control terminal of the 27th switch M27 receives the mode enable signal mode_en, the first terminal of the 27th switch M27 is connected to the first potential line to access the first potential, the second terminal of the 27th switch M27 is connected to the first terminal of the 28th switch M28, and the control terminal of the 28th switch M28 receives the inverted signal of the read address signal of another row (e.g., rp_addb).<n+1> At this point, i = n; for example, rp_addb <n>At this point (i = m = n + 1), the second terminal of the twenty-eighth switch M28 is connected to the signal output line. Additionally, the twenty-fifth switch M25 and the twenty-sixth switch M26 are NMOS transistors, and the twenty-seventh switch M27 and the twenty-eighth switch M28 are PMOS transistors. Furthermore, the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal. It should be noted that "another row" refers to a row within control group 100a that is different from the i-th row. If the i-th row is the n-th row, then the other row is the m-th row; if the i-th row is the m-th row, then the other row is the n-th row.

[0125] In practical applications, the second potential is a shared potential for multiple modules and is usually derived from the pixel circuit, thus introducing noise. To avoid noise interference during the readout stage, an independent third potential can be used instead of the second potential. In this case, the seventh control section 113b controls whether the overflow switch control signal of the i-th row is pulled to the third potential, such as the second negative voltage potential NVDD2, based on the third-stage initial control signal rp_ofswb. Correspondingly, the first terminal of the twenty-fourth switch M24 is changed from being connected to the second potential line to being connected to the third potential line. When the third control module 113 also includes an eighth control section 113c, the first terminal of the twenty-fifth switch M25 is changed from being connected to the second potential line to being connected to the third potential line, or the first terminal of the twenty-sixth switch M26 is changed from being connected to the second potential line to being connected to the third potential line.

[0126] Example 2

[0127] like Figure 4 As shown, this embodiment provides an image sensor 10, including a pixel circuit 200 and a control circuit 100. Wherein:

[0128] The pixel circuit 200 includes a plurality of pixel units 210 arranged in an array, wherein the pixel unit 210 is a dual-mode LOFIC pixel structure. It should be noted that the so-called dual-mode LOFIC pixel structure refers to a pixel structure with two overflow paths, and each overflow path corresponds to one overflow mode.

[0129] In one implementation, such as Figure 5 As shown, the pixel unit 210 includes a first reset module 211, a photosensitive module 212, an overflow module 213, and an output module 214. Further, it also includes at least one of a gain module 215 and a second reset module 216; alternatively, it may include both a gain module 215 and a second reset module 216.

[0130] A first reset module 211, connected to a corresponding floating diffusion node FD, is used to perform a reset operation on at least that floating diffusion node FD. In one example, the first reset module 211 includes a first reset transistor M29, wherein the control terminal of the first reset transistor M29 receives a first reset control signal for the corresponding row, such as RST. <n>or RST<n+1> The first terminal of the first reset transistor M29 is connected to the corresponding floating diffusion node FD, and the second terminal of the first reset transistor M29 is connected to a fourth potential, such as the reset potential OFBTM. In this example, the first reset transistor M29 is an NMOS transistor, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0131] Photosensitive module 212, connected to a corresponding floating diffusion node FD, is used to accumulate photogenerated electrons and at least transfer them to the floating diffusion node FD to output a pixel signal. In one example, photosensitive module 212 includes a transmission transistor M30 and a photosensitive element PD, wherein: the control terminal of the transmission transistor M30 receives a transmission control signal for the corresponding row, such as TX. <n>or TX<n+1> The first terminal of the transfer transistor M30 is connected to the corresponding floating diffusion node FD, and the second terminal of the transfer transistor M30 is connected to a fifth potential, such as the reference ground potential, via the photosensitive element PD. In this example, the transfer transistor M30 is an NMOS transistor, with the control terminal being the gate terminal, the first terminal being the source terminal, and the second terminal being the drain terminal, corresponding to the photosensitive element PD and the floating diffusion node FD, respectively. The photosensitive element PD is a photodiode. In practical applications, the transfer transistor M30 and the photosensitive element PD are in a one-to-one correspondence; the number of each can be one or more, without much restriction.

[0132] The overflow module 213 includes a first overflow path and a second overflow path, which are respectively connected to both sides of the photosensitive module 212. For example, the first overflow path is connected to the end of the transmission transistor M30 closer to the photosensitive element PD, and the second overflow path is connected to the end of the transmission transistor M30 farther from the photosensitive element PD. In the first overflow mode, the overflowed photogenerated electrons are stored through the first overflow path to output an overflow signal. In the second overflow mode, the overflowed photogenerated electrons are stored through the second overflow path to output an overflow signal. In one example, the overflow module 213 includes an overflow transistor M31, an overflow switch transistor M32, and an overflow capacitor COF, wherein: the control terminal of the overflow transistor M31 receives an overflow control signal OFG; the first terminal of the overflow transistor M31 is connected to the first terminal of the overflow capacitor COF; the second terminal of the overflow transistor M31 is connected to the photosensitive module 212, for example, connected to the second terminal of the transmission transistor M30; and the control terminal of the overflow switch transistor M32 receives an overflow switch control signal corresponding to the row, for example, OFSW. <n>or OFSW<n+1> The first terminal of overflow switch M32 is connected to the corresponding floating diffusion node FD, and the second terminal of overflow switch M32 is connected to the first terminal of overflow capacitor COF. The second terminal of overflow capacitor COF is connected to a sixth potential, for example, overflow potential VRM_BST. The path of overflow transistor M31 is the first overflow path, corresponding to the first overflow mode, for example, OFG overflow mode. The path of overflow switch M32 is the second overflow path, corresponding to the second overflow mode, for example, non-OFG overflow mode. In this example, overflow transistor M31 and overflow switch M32 are NMOS transistors, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0133] Output module 214, connected to the corresponding floating diffusion node FD, is used to amplify and output the corresponding signals (typically including pixel signals and overflow signals). In one example, output module 214 includes a source follower transistor M33 and a select transistor M34, wherein: the control terminal of the source follower transistor M33 is connected to the corresponding floating diffusion node FD; the first terminal of the source follower transistor M33 is connected to the second terminal of the select transistor M34; the second terminal of the source follower transistor M33 is connected to a seventh potential, such as the pixel power supply potential PIXVDD; and the control terminal of the select transistor M34 receives the selection control signal for the corresponding row, such as RS. <n>or RS<n+1> The first terminal of the select transistor M34 is connected to the corresponding column line for signal output. In this example, the source follower transistor M33 and the select transistor M34 are NMOS transistors, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0134] Gain module 215, connected to the corresponding floating diffusion node, is used for switching between different conversion gains. In one example, gain module 215 includes a first gain transistor M35 to provide dual conversion gain; wherein: the control terminal of the first gain transistor M35 receives a first gain control signal corresponding to the row, such as DCG. <n>or DCG<n+1> The first terminal of the first gain transistor M35 is connected to the eighth potential, such as the reference ground potential, and the second terminal of the first gain transistor M35 is connected to the corresponding floating diffusion node FD. In this example, the first gain transistor M35 is an NMOS transistor, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal. In practical applications, to provide more conversion gain, the pixel units in the nth row and the pixel units in the mth row are defined as forming a pixel group. Within this pixel group, in two pixel units in the same column, the first terminals of the two first gain transistors M35 are no longer connected to the eighth potential, but are connected to each other. In another example, the gain module 215 includes a second gain transistor M36 in addition to the first gain transistor M35 to provide triple conversion gain; wherein: the control terminal of the first gain transistor M35 receives the first gain control signal of the corresponding row, such as DCG. <n>or DCG<n+1> The first terminal of the first gain transistor M35 is connected to the second terminal of the second gain transistor M36. The second terminal of the first gain transistor M35 is connected to the corresponding floating diffusion node FD. The control terminal of the second gain transistor M36 receives the second gain control signal for the corresponding row, such as TCG. <n>or TCG<n+1> The first terminal of the second gain transistor M36 is connected to the eighth potential. In this example, the first gain transistor M35 and the second gain transistor M36 are NMOS transistors, and the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal. In practical applications, to provide more conversion gain, the pixel units in the nth row and the pixel units in the mth row are defined as a pixel group. Within this pixel group, in two pixel units in the same column, the first terminals of the two second gain transistors M36 are no longer connected to the eighth potential, but are connected to each other. In this embodiment, when the pixel unit 210 includes the gain module 215, the first terminal of the overflow switch transistor M32 is usually no longer connected to the corresponding floating diffusion node FD, but is connected to the first terminal of the first gain transistor M35.

[0135] Of course, in other implementations, to provide more conversion gain, the gain module 215 includes more gain transistors besides the first gain transistor M35 and the second gain transistor M36, such as the gain transistors connected in series, to provide more gain beyond the three-conversion gain. In this case, the first terminal of the last gain transistor is connected to the eighth potential. Additionally, correspondingly, when the first terminal of the overflow switch M32 is no longer connected to the corresponding floating diffusion node FD, it can be connected to the first terminals of other gain transistors besides the last gain transistor, depending on the requirements.

[0136] The second reset module 216, connected to the overflow module 213, is used to perform a reset operation on at least the overflow module 213, thereby achieving a fast reset of the overflow module 213. In one example, the second reset module 216 includes a second reset transistor M37, wherein the control terminal of the second reset transistor M37 receives a second reset control signal corresponding to the row, such as OF_RST. <n>or OF_RST<n+1> The first terminal of the second reset transistor M37 is connected to the ninth potential, for example, the reset potential OFBTM, and the second terminal of the second reset transistor M37 is connected to the second terminal of the overflow capacitor COF. Furthermore, the first terminal of the second reset transistor M37 is directly connected to the second terminal of the first reset transistor M29. In this example, the second reset transistor M37 is an NMOS transistor, and its control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0137] Regarding pixel unit 210: In the first overflow mode, for example, OFG overflow mode, the photosensitive element PD overflows after accumulating electrons, and the overflowed electrons leak through the overflow transistor M31 to the first terminal of the overflow capacitor COF; the control signal of the overflow switch transistor M32 is the overflow switch control signal. In this mode, the requirements for the overflow switch control signal are: during the reset stage and readout stage, it follows the changes of the digital control signal; during the exposure stage, it is at a low level; during the idle stage, it can choose whether to enter the latching state according to the requirements, that is, it can be at a high level or a low level depending on the application scenario. In the second overflow mode, for example, in the non-OFG overflow mode, the overflow transistor M31 is completely turned off. After the photosensitive element PD accumulates electrons, it overflows. The overflowed electrons leak at least through the overflow switch transistor M32 to the first terminal of the overflow capacitor COF. For example, the photosensitive element PD accumulates electrons and overflows through the transmission transistor TX. Of course, it may also leak through the first gain transistor M35 and the overflow switch transistor M32 to the first terminal of the overflow capacitor COF. The control signal of the overflow switch transistor M32 is the overflow switch control signal. In this mode, the requirements for the overflow switch control signal are: during the reset and readout stages, it follows the changes of the digital control signal; during the exposure stage, it is at a high level; during the idle stage, it can choose whether to enter the latching state according to the requirements. That is, it can be at a high level or a low level depending on the application scenario.

[0138] The control circuit 100 provides overflow switch control signals to the pixel units of each row at least in a first stage; furthermore, it provides overflow switch control signals to the pixel units of each row in at least one of a second stage and a third stage. The control circuit 100 is implemented using the circuit structure described in Embodiment 1, the relevant details of which can be found above and will not be repeated here.

[0139] Accordingly, this embodiment also provides a control method for an image sensor 10, including a first stage, and further including at least one of a second stage and a third stage; wherein the image sensor 10 is implemented using the structure described above, and the relevant content can be found above, and will not be repeated here.

[0140] In the first stage, the first control module in the i-th control unit operates and generates the overflow switch control signal for the i-th row to control the pixel unit in the i-th row to operate in the corresponding overflow mode; wherein, the first stage includes an exposure stage (i.e., the exposure stage) and an idle stage (i.e., the idle stage).

[0141] Taking i=n as an example, the working conditions during the exposure phase and the idle phase are explained separately; the truth tables for the mode enable signal mode_en and the latch enable signal lat_enb in different modes and states are as follows: Figure 6 As shown.

[0142] When the first stage is the exposure stage:

[0143] In the first overflow mode, for example, in OFG overflow mode,

[0144] The mode enable signal mode_en is high, the latch enable signal lat_enb is low, and the first latch address signal lat_add1 of the nth row is... <n>When the signal is high, the second latch address signal lat_add2 in the nth row is... <n>If the signal is low, the signal output line is pulled to the second potential through the third control section 111c, and the overflow switch control signal OFSW in the nth row... <n>When the level is low, the first control module 111, as follows: Figure 7 As shown, the relevant timing sequence is as follows Figure 8 and Figure 9 As shown in the expo phase.

[0145] In the second overflow mode, for example, in the non-OFG overflow mode,

[0146] If the mode enable signal mode_en is low, the latch enable signal lat_enb is low, and the first latch address signal lat_add1 of the nth row... <n>When the signal is high, the second latch address signal lat_add2 in the nth row is... <n>If the signal is low, the signal output line is pulled to the first potential through the second control section 111b, and the overflow switch control signal OFSW in the nth row... <n>When the signal is high, the first control module 111, as follows: Figure 10 As shown, the relevant timing sequence is as follows Figure 11 As shown in the expo phase.

[0147] If the mode enable signal mode_en is low, the latch enable signal lat_enb is high, and the first latch address signal lat_add1 of the nth row... <n>When the signal is high, the second latch address signal lat_add2 in the nth row is... <n>If the signal is low, the signal output line is pulled to the first potential through the second control section 111b, and the overflow switch control signal OFSW in the nth row... <n>When the signal is high, the first control module 111, as follows: Figure 12 As shown, the relevant timing sequence is as follows Figure 13 As shown in the expo phase.

[0148] As can be seen, during the exposure stage, in the first overflow mode (e.g., OFG overflow mode), the overflow switch control signal OFSW for the nth row... <n>When the overflow level is low, in the second overflow mode (e.g., non-OFG overflow mode), the overflow switch control signal OFSW in the nth row is... <n>It is a high level.

[0149] When the first phase is an idle phase:

[0150] In the first overflow mode, for example, in OFG overflow mode,

[0151] For the latched state, the mode enable signal mode_en is high, the latch enable signal lat_enb is low, and the first latch address signal lat_add1 of the nth row is... <n>When the signal is low, the second latch address signal lat_add2 in the nth row is... <n>If the signal is high, the signal output line is pulled to the first potential through the first control section 111a, and the overflow switch control signal OFSW in the nth row... <n>When the signal is high, the first control module 111, as follows: Figure 14 As shown, the relevant timing sequence is as follows Figure 8 The idle phase is shown in the diagram.

[0152] In the non-latched state, the mode enable signal mode_en is high, the latch enable signal lat_enb is low, and the first latch address signal lat_add1 of the nth row is... <n>When the signal is high, the second latch address signal lat_add2 in the nth row is... <n>If the signal is low, the signal output line is pulled to the second potential through the third control section 111c, and the overflow switch control signal OFSW in the nth row... <n>When the level is low, the first control module 111, as follows: Figure 7 As shown, the relevant timing sequence is as follows Figure 9 The idle phase is shown in the diagram.

[0153] In the second overflow mode, for example, in the non-OFG overflow mode,

[0154] For the latched state, the mode enable signal mode_en is low, the latch enable signal lat_enb is low, and the first latch address signal lat_add1 of the nth row is also low. <n>When the signal is low, the second latch address signal lat_add2 in the nth row is... <n>If the signal is high, the signal output line is pulled to the first potential through the first control section 111a, and the overflow switch control signal OFSW in the nth row... <n>When the signal is high, the first control module 111, as follows: Figure 15 As shown, the relevant timing sequence is as follows Figure 11 As shown in the idle phase;

[0155] In the non-latched state, the mode enable signal mode_en is low, the latch enable signal lat_enb is high, and the first latch address signal lat_add1 of the nth row is... <n>When the signal is low, the second latch address signal lat_add2 in the nth row is... <n>If the signal is low, the signal output line is pulled to the first potential through the second control section 111b, and the overflow switch control signal OFSW in the nth row... <n>When the signal is high, the first control module 111, as follows: Figure 16 As shown, the relevant timing sequence is as follows Figure 13 The idle phase is shown in the diagram.

[0156] As can be seen, during the idle phase, in the first overflow mode (e.g., OFG overflow mode), for the latched state, the overflow switch control signal OFSW in the nth row... <n>When the signal is high, for the non-latched state, the overflow switch control signal OFSW in the nth row is... <n>When the signal is low, in the second overflow mode (e.g., non-OFG overflow mode), for the latched state, the overflow switch control signal OFSW in the nth row is... <n>When the signal is high, for the non-latched state, the overflow switch control signal OFSW in the nth row is... <n>It is a high level.

[0157] In the second stage, the second control module in the i-th control unit works and generates the overflow switch control signal for the i-th row to control the pixel unit in the i-th row to work in the corresponding overflow mode; wherein, the second stage is the reset stage (i.e., the sp stage).

[0158] Taking i=n as an example, the working situation of the reset stage is explained; among them, the initial control signal sp_ofswb in the second stage is an externally provided digital control signal.

[0159] In arbitrary overflow mode: if the initial control signal sp_ofswb of the second stage is low, then the signal output line is pulled to the first potential through the fourth control section 112a, and the overflow switch control signal OFSW of the nth row... <n>If the initial control signal sp_ofswb in the second stage is high, then the signal output line is pulled to the second potential through the fifth control section 112b, and the overflow switch control signal OFSW in the nth row is high. <n>It is a low level.

[0160] As can be seen, during the reset phase, regardless of whether it is in the first overflow mode or the second overflow mode, the overflow switch control signal OFSW in the nth row... <n>They all follow the changes in the initial control signal sp_ofswb in the second stage.

[0161] In the third stage, the third control module in the i-th control unit works and generates the overflow switch control signal for the i-th row to control the pixel unit in the i-th row to work in the corresponding overflow mode; the third stage is the readout stage (i.e., the rp stage).

[0162] Taking i=n as an example, the working situation of the readout stage is explained; among them, the initial control signal rp_ofswb in the third stage is an externally provided digital control signal.

[0163] for Figure 1 The circuit shown is as follows:

[0164] In arbitrary overflow mode: if the initial control signal rp_ofswb in the third stage is low, then the signal output line is pulled to the first potential through the sixth control section 113a, and the overflow switch control signal OFSW in the nth row... <n>If the initial control signal rp_ofswb in the third stage is high, then the signal output line is pulled to the third potential through the seventh control section 113b, and the overflow switch control signal OFSW in the nth row is high. <n>It is a low level.

[0165] for Figure 2 The circuit shown is as follows:

[0166] In any overflow mode, the 25th switch M25 in the eighth control section 113c is turned off, which does not affect the sixth control section 113a and the seventh control section 113b.

[0167] Additionally, during line-by-line readout, in arbitrary overflow mode: when reading out pixel units in the nth row, the overflow switch control signal OFSW for the mth row...<n+1> It is at a low potential; when a readout operation is performed on the pixel unit of the m-th row, the overflow switch control signal OFSW for the n-th row is... <n>It is at a low potential.

[0168] for Figure 3 The circuit shown is as follows:

[0169] In any overflow mode, the 25th switch M25 in the eighth control section 113c is turned off, which does not affect the sixth control section 113a and the seventh control section 113b.

[0170] In addition, during the line-by-line reading process

[0171] In the first overflow mode, for example, in OFG overflow mode,

[0172] When a readout operation is performed on the pixel unit of the nth row, the overflow switch control signal OFSW for the mth row...<n+1> It is at a low potential; when a readout operation is performed on the pixel unit of the m-th row, the overflow switch control signal OFSW for the n-th row is... <n>The potential is low; thus, adjacent rows can be selected to the second potential line with lower noise, which is beneficial to the low noise requirement of the quantization row.

[0173] In the second overflow mode, for example, in the non-OFG overflow mode,

[0174] When a readout operation is performed on the pixel unit of the nth row, the overflow switch control signal OFSW for the mth row...<n+1> It is at a high potential; when a readout operation is performed on the pixel unit of the m-th row, the overflow switch control signal OFSW of the n-th row is high. <n>This is a high potential; thus, adjacent rows can be selected to the second potential line with lower noise, which is beneficial for the low noise requirement of the quantization row.

[0175] As can be seen, during the readout phase, regardless of whether it is in the first overflow mode or the second overflow mode, the overflow switch control signal OFSW for the nth row... <n>They all follow the changes in the initial control signal rp_ofswb in the third stage.

[0176] In summary, the control circuit and image sensor of this invention, through the design of the control module, can effectively drive a dual-mode LOFIC pixel structure, be compatible with both overflow modes, and perform overflow switch control at each stage, thereby achieving smooth control of complex pixel structures. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0177] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A control circuit, characterized by Includes at least one control group, wherein: The control group includes an nth control unit and an mth control unit, corresponding to the nth row of pixel units and the mth row of pixel units, respectively. The control unit includes a first control module. Within the control group, the first control module in the i-th control unit operates in the first stage and, under the control of the n-th row address signal and the m-th row address signal, generates the i-th row overflow switch control signal based at least on the mode enable signal. Where n and m are both natural numbers greater than or equal to 1, and i is either n or m.

2. The control circuit of claim 1, wherein, The first control module in the i-th control unit generates the i-th row overflow switch control signal based on the mode enable signal and the latch enable signal, wherein the first stage is the exposure stage and / or the idle stage.

3. The control circuit according to claim 2, characterized in that, The first control module includes: The first control section controls whether the overflow switch control signal of the i-th row is pulled to the first potential based on the latch enable signal; The second control section controls whether the overflow switch control signal of the i-th row is pulled to the first potential based on the mode enable signal. The third control section controls whether the overflow switch control signal of the i-th row is pulled to the second potential based on the latch enable signal and the mode enable signal.

4. The control circuit of claim 3, wherein, The first control section includes a first switch, a second switch, a third switch, and a fourth switch, wherein: the control terminal of the first switch receives the latch enable signal; the first terminal of the first switch is connected to a first potential line; the second terminal of the first switch is connected to the first terminal of the second switch; the control terminal of the second switch receives the first latch address signal of the i-th row; the second terminal of the second switch is connected to the first terminal of the third switch; the control terminal of the third switch receives the read address signal of the n-th row; the second terminal of the third switch is connected to the first terminal of the fourth switch; the control terminal of the fourth switch receives the read address signal of the m-th row; and the second terminal of the fourth switch is connected to a signal output line. And / or, the second control section includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a ninth switch, wherein: the control terminal of the fifth switch receives the mode enable signal; the first terminal of the fifth switch is connected to a first potential line; the second terminal of the fifth switch is connected to the first terminal of the sixth switch; the control terminal of the sixth switch receives the second latch address signal of the i-th row; the second terminal of the sixth switch is connected to the first terminal of the seventh switch; the control terminal of the seventh switch receives the exposure address signal of the i-th row; the second terminal of the seventh switch is connected to the first terminal of the eighth switch; the control terminal of the eighth switch receives the readout address signal of the n-th row; the second terminal of the eighth switch is connected to the first terminal of the ninth switch; the control terminal of the ninth switch receives the readout address signal of the m-th row; and the second terminal of the ninth switch is connected to a signal output line. And / or, the third control section includes a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch, wherein: the control terminal of the tenth switch receives the inverted signal of the exposure address signal of the i-th row; the first terminal of the tenth switch is connected to the second terminal of the eleventh switch; the second terminal of the tenth switch is connected to a signal output line; the control terminal of the eleventh switch receives the inverted signal of the readout address signal of the n-th row; the first terminal of the eleventh switch is connected to the second terminal of the twelfth switch; the control terminal of the twelfth switch receives the inverted signal of the readout address signal of the m-th row; the first terminal of the twelfth switch... The second terminals of the thirteenth and fourteenth switches are respectively connected. The control terminal of the thirteenth switch receives the first latch address signal of the i-th row. The first terminal of the thirteenth switch is respectively connected to the second terminals of the fifteenth and sixteenth switches. The control terminal of the fourteenth switch receives the latch enable signal. The first terminal of the fourteenth switch is connected to the second terminal of the sixteenth switch. The control terminal of the fifteenth switch receives the second latch address signal of the i-th row. The first terminal of the fifteenth switch is connected to the second potential line. The control terminal of the sixteenth switch receives the mode enable signal. The first terminal of the sixteenth switch is connected to the second potential line.

5. The control circuit according to any one of claims 1 to 4, characterized by The control unit further includes a second control module; wherein, within the control group, the second control module in the i-th control unit operates in the second stage and, under the control of the i-th row address signal, generates the i-th row overflow switch control signal based on the initial control signal of the second stage; And / or, the control unit further includes a third control module; wherein, within the control group, the third control module in the i-th control unit operates in the third stage, and under the control of the i-th row address signal, generates the i-th row overflow switch control signal based on the initial control signal of the third stage; And / or, the control group further includes two latch address units, denoted as the nth latch address unit and the mth latch address unit, which correspond to the first control modules in the nth control unit and the mth control unit, respectively, to generate the second latch address signal of the corresponding row based on the latch enable signal and the first latch address signal of the corresponding row; And / or, m = n + 1.

6. The control circuit of claim 5, wherein, When the control unit includes a second control module, the second control module includes: a fourth control part, which controls whether the overflow switch control signal of the i-th row is pulled to a first potential based on the second stage initial control signal; and a fifth control part, which controls whether the overflow switch control signal of the i-th row is pulled to a second potential based on the second stage initial control signal. And / or, when the control group further includes two latch address units, the two latch address units in the control group have the same structure, including a NOR gate, wherein: the first input of the NOR gate is connected to the latch enable signal, the second input of the NOR gate is connected to the first latch address signal of the corresponding row, and the output of the NOR gate generates the second latch address signal of the corresponding row.

7. The control circuit of claim 6, wherein, The fourth control section includes a seventeenth switch and an eighteenth switch, wherein: the control terminal of the seventeenth switch receives the inverted signal of the exposure address signal of the i-th row, the first terminal of the seventeenth switch is connected to the first potential line, the second terminal of the seventeenth switch is connected to the first terminal of the eighteenth switch, the control terminal of the eighteenth switch receives the second stage initial control signal, and the second terminal of the eighteenth switch is connected to the signal output line; And / or, the fifth control section includes a nineteenth switch and a twentieth switch, wherein: the control terminal of the nineteenth switch receives the second stage initial control signal, the first terminal of the nineteenth switch is connected to the second terminal of the twentieth switch, the second terminal of the nineteenth switch is connected to the signal output line, the control terminal of the twentieth switch receives the exposure address signal of the i-th row, and the first terminal of the twentieth switch is connected to the second potential line.

8. The control circuit of claim 5, wherein, When the control unit includes a third control module, the third control module includes: The sixth control section controls whether the overflow switch control signal of the i-th row is pulled to the first potential based on the initial control signal of the third stage; The seventh control section controls whether the overflow switch control signal of the i-th row is pulled to the second or third potential based on the initial control signal of the third stage.

9. The control circuit of claim 8, wherein, The sixth control section includes a 21st switch and a 22nd switch, wherein: the control terminal of the 21st switch receives the inverted signal of the read address signal of the i-th row, the first terminal of the 21st switch is connected to the first potential line, the second terminal of the 21st switch is connected to the first terminal of the 22nd switch, the control terminal of the 22nd switch receives the initial control signal of the third stage, and the second terminal of the 22nd switch is connected to the signal output line. The seventh control section includes a 23rd switch and a 24th switch, wherein: the control terminal of the 23rd switch receives the initial control signal of the third stage, the first terminal of the 23rd switch is connected to the second terminal of the 24th switch, the second terminal of the 23rd switch is connected to the signal output line, the control terminal of the 24th switch receives the read address signal of the i-th row, and the first terminal of the 24th switch is connected to the second potential line or the third potential line.

10. The control circuit according to claim 8 or 9, characterized in that, The third control module also includes an eighth control section; The eighth control section includes a 25th switch, wherein: the control terminal of the 25th switch receives the read address signal of another row, the first terminal of the 25th switch is connected to the second potential line or the third potential line, and the second terminal of the 25th switch is connected to the signal output line; Alternatively, the eighth control section may further include a 26th switch, a 27th switch, and a 28th switch, wherein: the first terminal of the 25th switch is changed from being connected to the corresponding potential line to being connected to the second terminal of the 26th switch; the control terminal of the 26th switch receives a mode enable signal; the first terminal of the 26th switch is connected to a second potential line or a third potential line; the control terminal of the 27th switch receives a mode enable signal; the first terminal of the 27th switch is connected to a first potential line; the second terminal of the 27th switch is connected to the first terminal of the 28th switch; the control terminal of the 28th switch receives an inverted signal of the read address signal of another row; and the second terminal of the 28th switch is connected to a signal output line.

11. The control circuit according to claim 5, characterized in that, The second stage includes a reset stage, and the third stage includes a readout stage.

12. An image sensor, comprising: include: A pixel circuit includes a plurality of pixel units arranged in an array, wherein the pixel units are dual-mode LOFIC pixel structures; The control circuit as described in any one of claims 1 to 11 provides corresponding overflow switch control signals to the pixel units of each row at least in the first stage.

13. The image sensor of claim 12, wherein, The pixel unit includes: The first reset module is connected to the corresponding floating diffusion node and is used to perform a reset operation on at least the floating diffusion node. A photosensitive module, connected to the floating diffusion node, is used to accumulate photogenerated electrons and at least transfer them to the floating diffusion node to output a pixel signal; The overflow module includes a first overflow path and a second overflow path, which are respectively connected to both sides of the photosensitive module. In the first overflow mode, the overflowed photogenerated electrons are stored through the first overflow path to output an overflow signal. In the second overflow mode, the overflowed photogenerated electrons are stored through the second overflow path to output an overflow signal. An output module, connected to the floating diffusion node, is used to amplify and output the corresponding signal; Alternatively, the pixel unit may further include a gain module and / or a second reset module; The gain module is connected to the floating diffusion node and is used to switch between different conversion gains; The second reset module is connected to the overflow module and is used to at least reset the overflow module.

14. The image sensor of claim 13, wherein, The first reset module includes a first reset transistor, wherein: the control terminal of the first reset transistor receives a first reset control signal corresponding to the row, the first terminal of the first reset transistor is connected to the floating diffusion node, and the second terminal of the first reset transistor is connected to a fourth potential; And / or, the photosensitive module includes a transmission transistor and a photosensitive element, wherein: the control terminal of the transmission transistor receives a transmission control signal for the corresponding row, the first terminal of the transmission transistor is connected to the floating diffusion node, and the second terminal of the transmission transistor is connected to a fifth potential via the photosensitive element; And / or, the overflow module includes an overflow transistor, an overflow switch, and an overflow capacitor, wherein: the control terminal of the overflow transistor receives an overflow control signal; the first terminal of the overflow transistor is connected to the first terminal of the overflow capacitor; the second terminal of the overflow transistor is connected to the photosensitive module; the control terminal of the overflow switch receives an overflow switch control signal corresponding to the row; the first terminal of the overflow switch is connected to the floating diffusion node; the second terminal of the overflow switch is connected to the first terminal of the overflow capacitor; and the second terminal of the overflow capacitor is connected to a sixth potential; wherein the path where the overflow transistor is located is the first overflow path, and the path where the overflow switch is located is the second overflow path; And / or, the output module includes a source follower transistor and a select transistor, wherein: the control terminal of the source follower transistor is connected to the floating diffusion node, the first terminal of the source follower transistor is connected to the second terminal of the select transistor, the second terminal of the source follower transistor is connected to a seventh potential, the control terminal of the select transistor receives a selection control signal for the corresponding row, and the first terminal of the select transistor is connected to the corresponding column line; When the pixel unit includes a gain module, the gain module includes a first gain transistor, wherein: the control terminal of the first gain transistor receives a first gain control signal for the corresponding row, the first terminal of the first gain transistor is connected to an eighth potential, and the second terminal of the first gain transistor is connected to the floating diffusion node; or, the gain module further includes a second gain transistor, wherein: the first terminal of the first gain transistor is changed from being connected to the eighth potential to being connected to the second terminal of the second gain transistor, the control terminal of the second gain transistor receives a second gain control signal for the corresponding row, and the first terminal of the second gain transistor is connected to the eighth potential; When the pixel unit includes a second reset module, the second reset module includes a second reset transistor, wherein: the control terminal of the second reset transistor receives a second reset control signal for the corresponding row, the first terminal of the second reset transistor is connected to a ninth potential, and the second terminal of the second reset transistor is connected to the second terminal of the overflow capacitor.

15. The image sensor of claim 14, wherein, In the case where the overflow module includes an overflow switch, when the pixel unit includes a gain module and the gain module includes at least a first gain transistor, the first end of the overflow switch is changed from being connected to the floating diffusion node to being connected to the first end of the first gain transistor. And / or, the pixel units in the nth row and the pixel units in the mth row constitute a pixel group; when the pixel unit includes a gain module and the gain module includes a first gain transistor: within the pixel group, in two pixel units in the same column, the first terminals of the two first gain transistors are changed from being connected to the eighth potential to being connected to each other; when the pixel unit includes a gain module and the gain module includes a second gain transistor: within the pixel group, in two pixel units in the same column, the first terminals of the two second gain transistors are changed from being connected to the eighth potential to being connected to each other.

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