A ltcc multilayer duplexer

Abstract

This invention provides an LTCC multilayer duplexer, comprising a ceramic substrate, a connection port disposed on the bottom surface of the ceramic substrate, and a circuit structure layer disposed inside the ceramic substrate. It employs a lumped parameter model design to achieve the specific electrical performance requirements of a novel, miniaturized, wideband, low-insertion-loss LTCC duplexer. The low-frequency path utilizes a second-order low-pass filter. In the high-frequency band, a bridging capacitor is introduced to create a transmission zero in the low-frequency passband, enhancing the high-frequency passband's low-frequency suppression capability. Furthermore, a higher-order approach is used to simply and effectively broaden the high-frequency passband range. This invention not only effectively achieves frequency division between low-frequency and high-frequency signals and effectively broadens the high-frequency passband bandwidth, but also possesses advantages such as miniaturization, low loss, high suppression, high isolation, high reliability, low cost, excellent consistency, and suitability for large-scale production. Additionally, it adapts to the new trend of electronic component integration and miniaturization.

Description

Technical Field

[0001] This utility model relates to the technical field of duplexers, and in particular to an LTCC multilayer duplexer. Background Technology

[0002] Low Temperature Co-fired Ceramic (LTCC) technology is a novel co-firing technology developed in 1982 by Hughes Aircraft Company in the United States, based on High Temperature Co-fired Ceramic (HTCC). It involves creating precisely thick and dense green ceramic tapes from low-temperature sintered ceramic powder, which serve as circuit board materials. The desired circuit patterns are then fabricated on these green ceramic tapes using processes such as laser drilling, micro-hole injection, and precision conductor paste printing. Multiple passive components are embedded within these tapes, which are then stacked together and sintered at 900°C to create passive integrated components with a three-dimensional circuit network. This process can also produce three-dimensional circuit boards with built-in passive components. ICs and active devices can be mounted on the surface of these boards, ultimately creating passive / active integrated functional modules.

[0003] As smartphones, mobile devices, and other equipment continue to evolve towards miniaturization and multi-band operation, higher demands are being placed on duplexers. On the one hand, the trend towards device miniaturization necessitates that duplexers have smaller dimensions to better integrate within the limited space of a circuit board. For example, in the internal space of a mobile phone, an excessively large duplexer would occupy too much space, hindering the layout of other components and the overall slim and lightweight design of the phone.

[0004] On the other hand, the development of multi-band technology requires duplexers to have excellent performance, accurately process signals from different frequency bands, effectively isolate and filter transmitted and received signals, ensure that signal transmission in each frequency band does not interfere with each other, and have low insertion loss to maintain signal strength and accuracy. Therefore, it is urgent to solve the above problems. Utility Model Content

[0005] To address the above problems, this utility model provides a miniaturized, broadband, low insertion loss LTCC multilayer duplexer.

[0006] This utility model achieves the above objective through the following technical solution: an LCTT multilayer duplexer, comprising a ceramic substrate, a connection port disposed on the bottom surface of the ceramic substrate, and a circuit structure layer disposed inside the ceramic substrate, wherein the circuit structure layer comprises:

[0007] The first layer consists of a first metal plane, a second metal plane, a third metal plane, a fourth metal plane, a fifth metal plane, and a sixth metal plane that are mutually insulated on a ceramic dielectric substrate.

[0008] The second layer consists of a first metal plane, a second metal plane, and a third metal plane that are mutually insulated on a ceramic dielectric substrate. The first metal plane of the second layer is connected to the fifth metal plane of the first layer through a first conductive post, the first metal plane of the second layer is connected to the first metal plane of the first layer through a second conductive post, and the second metal plane of the second layer is connected to the second metal plane of the first layer through a third conductive post.

[0009] The third layer consists of three mutually insulated metal planes: a first metal plane, a second metal plane, a third metal plane, and a fourth metal plane. The third metal plane is connected to the first metal plane via a fourth conductive post, and the fourth metal plane is connected to the second metal plane via a fifth conductive post.

[0010] The fourth layer consists of a first metal plane, a second metal plane, and a third metal plane that are mutually insulated on a ceramic dielectric substrate. The third metal plane is connected to the sixth metal plane of the first layer by a sixth conductive post, and the second metal plane is connected to the second metal plane of the third layer by a seventh conductive post.

[0011] The fifth layer consists of three mutually insulated metal planes: a first metal plane, a second metal plane, and a third metal plane. The third metal plane is connected to the first metal plane via an eighth conductive post, the first metal plane is connected to the fourth metal plane via a ninth conductive post, and the second metal plane and the fourth metal plane are connected via a tenth conductive post.

[0012] The sixth layer has a first metal plane and a second metal plane that are mutually insulated on a ceramic dielectric substrate. The first metal plane of the sixth layer is connected to the first metal plane of the fourth layer through an eleventh conductive post, and the second metal plane of the sixth layer is connected to the third metal plane of the fourth layer through a twelfth conductive post.

[0013] The seventh layer consists of three mutually insulated metal coils: a first metal coil, a second metal coil, and a third metal coil. One end of the third metal coil is connected to the second metal plane of the fifth layer via a thirteenth conductive post. One end of the second metal coil is connected to the first metal plane of the fifth layer via a fourteenth conductive post. One end of the first metal coil is connected to the second metal plane of the sixth layer via a fifteenth conductive post.

[0014] The eighth layer has a first metal coil and a second metal coil printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil is connected to the other end of the first metal coil in the seventh layer through a sixteenth conductive post, and one end of the second metal coil in the eighth layer is connected to the other end of the second metal coil in the seventh layer through a seventeenth conductive post.

[0015] The ninth layer has a first metal coil and a second metal coil printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil is connected to the other end of the first metal coil in the eighth layer through an eighteenth conductive post, and one end of the second metal coil is connected to the other end of the second metal coil in the eighth layer through a nineteenth conductive post.

[0016] The tenth layer has a first metal coil and a second metal coil printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil is connected to the first metal plane of the third layer through a twentieth conductive post, one end of the second metal coil is connected to the third metal plane of the third layer through a twentieth conductive post, the other end of the first metal coil is connected to the other end of the first metal coil of the ninth layer through a twentieth conductive post, and the other end of the second metal coil is connected to the other end of the second metal coil of the ninth layer through a twentieth conductive post.

[0017] The eleventh layer has a first metal coil printed on a ceramic dielectric substrate, and one end of the first metal coil in the eleventh layer is connected to one end of the first metal coil in the tenth layer through a twenty-fourth conductive post.

[0018] The twelfth layer has three mutually insulated metal coils printed on a ceramic dielectric substrate: a first metal coil, a second metal coil, and a third metal coil. One end of the second metal coil is connected to the second metal plane of the fourth layer via a twenty-fifth conductive post. One end of the third metal coil is connected to the other end of the third metal coil of the seventh layer via a twenty-sixth conductive post. One end of the first metal coil is connected to the other end of the first metal coil of the eleventh layer via a twenty-seventh conductive post.

[0019] The thirteenth layer has three mutually insulated metal coils printed on a ceramic dielectric substrate: a first metal coil, a second metal coil, and a third metal coil. One end of the first metal coil is connected to the other end of the first metal coil in the twelfth layer via a twenty-eighth conductive post. One end of the second metal coil is connected to the other end of the second metal coil in the twelfth layer via a twenty-ninth conductive post. One end of the third metal coil is connected to the other end of the third metal coil in the twelfth layer via a thirtieth conductive post.

[0020] The fourteenth layer comprises three mutually insulated metal coils: a first metal coil, a second metal coil, and a third metal coil. One end of the first metal coil is connected to the second metal plane of the second layer via a 31-conductive post. One end of the second metal coil is connected to the second metal coil of the tenth layer via a 32-conductive post. One end of the third metal coil is connected to the first metal plane of the sixth layer via a 33-conductive post. The other end of the first metal coil is connected to the other end of the first metal coil of the thirteenth layer via a 34-conductive post. The other end of the second metal coil is connected to the other end of the second metal coil of the thirteenth layer via a 35-conductive post. The other end of the third metal coil is connected to the other end of the third metal coil of the thirteenth layer via a 36-conductive post.

[0021] Furthermore, the connection ports include a first port, a second port, a third port, a fourth port, a fifth port, and a sixth port.

[0022] Furthermore, the first port, the third port, and the fifth port are all grounded ports, the second port is the public port, the sixth port is the low-frequency port, and the fourth port is the high-frequency port.

[0023] Furthermore, the first metal plane of layer one is connected to the first port, the second metal plane of layer one is connected to the second port, the third metal plane of layer one is connected to the third port, the fourth metal plane of layer one is connected to the fourth port, the fifth metal plane of layer one is connected to the fifth port, and the sixth metal plane of layer one is connected to the sixth port.

[0024] Furthermore, the top surface of the ceramic substrate is printed with a directional marking pattern.

[0025] Furthermore, the metal planes in the second to sixth layers are all capacitor substrates.

[0026] Compared with existing technologies, the advantages of this invention are as follows: Based on LTCC technology, this invention uses a lumped parameter model to design and achieve the special electrical performance requirements of a novel miniaturized, wideband, low-insertion-loss LTCC duplexer. The low-frequency path is constructed using a second-order low-pass filter. In the high-frequency band, a bridging capacitor is introduced to create a transmission zero in the low-frequency passband, enhancing the high-frequency passband's low-frequency suppression capability. Furthermore, a higher-order approach is used to simply and effectively broaden the high-frequency passband range. This invention not only effectively achieves frequency division between low-frequency and high-frequency signals and effectively broadens the high-frequency passband bandwidth, but also possesses advantages such as miniaturization, low loss, high suppression, high isolation, high reliability, low cost, excellent consistency, and suitability for large-scale production. In addition, it adapts to the new trend of electronic component integration and miniaturization. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the equivalent circuit of the LTCC multilayer duplexer of this utility model;

[0028] Figure 2 This is a three-dimensional perspective view of the duplexer of this utility model;

[0029] Figure 3 This is a schematic diagram of the internal structure of the duplexer of this utility model;

[0030] Figure 4 This is a graph showing the electrical characteristics of the duplexer of this invention.

[0031] Figure 5 This is a schematic diagram of the first layer circuit planar structure of the duplexer of this utility model;

[0032] Figure 6 This is a schematic diagram of the second-layer circuit planar structure of the duplexer of this utility model;

[0033] Figure 7 This is a schematic diagram of the third-layer circuit planar structure of the duplexer of this utility model;

[0034] Figure 8 This is a schematic diagram of the fourth layer circuit planar structure of the duplexer of this utility model;

[0035] Figure 9 This is a schematic diagram of the fifth layer circuit planar structure of the duplexer of this utility model.

[0036] Figure 10 This is a schematic diagram of the sixth layer circuit planar structure of the duplexer of this utility model;

[0037] Figure 11 This is a schematic diagram of the seventh layer circuit planar structure of the duplexer of this utility model;

[0038] Figure 12This is a schematic diagram of the eighth layer circuit planar structure of the duplexer of this utility model;

[0039] Figure 13 This is a schematic diagram of the ninth layer circuit planar structure of the duplexer of this utility model;

[0040] Figure 14 This is a schematic diagram of the tenth layer circuit planar structure of the duplexer of this utility model;

[0041] Figure 15 This is a schematic diagram of the eleventh layer circuit planar structure of the duplexer of this utility model;

[0042] Figure 16 This is a schematic diagram of the twelfth layer circuit planar structure of the duplexer of this utility model;

[0043] Figure 17 This is a schematic diagram of the thirteenth layer circuit planar structure of the duplexer of this utility model;

[0044] Figure 18 This is a schematic diagram of the fourteenth layer circuit planar structure of the duplexer of this utility model. Detailed Implementation

[0045] To facilitate understanding of this utility model, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "left," "right," "inner," "outer," and similar expressions used in this specification are for illustrative purposes only.

[0046] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0047] like Figure 1 As shown, this utility model provides an equivalent circuit for an LTCC multilayer duplexer, including a common port 1, a low-frequency port 2 and a high-frequency port 3. An inductor L1 and an inductor L2 are connected in series between the common port 1 and the low-frequency port 2. A grounding capacitor C1 is connected between the inductor L1 and the inductor L2. A grounding capacitor C2 is connected between the inductor L2 and the low-frequency port 2.

[0048] A capacitor C3, a capacitor C4, an inductor L4, and a capacitor C8 are connected in series between common port 1 and high-frequency port 3. A grounding inductor L3 is connected between capacitor C3 and capacitor C4. A grounding capacitor C6 is connected between capacitor C4 and inductor L4. A grounding capacitor C7 is connected between inductor L4 and capacitor C8. A grounding inductor L5 is connected between capacitor C8 and high-frequency port 3. A bridging capacitor C5 is connected between capacitor C4 and inductor L4. The other end of the bridging capacitor C5 is connected between common port 1 and capacitor C3.

[0049] Specifically, the equivalent circuit consists of a combination of low-frequency and high-frequency paths. The low-frequency path is a circuit connected in series between common port 1 and low-frequency port 2, providing a signal path from 617MHz to 960MHz. The high-frequency path is a circuit connected in series between common port 1 and high-frequency port 3, providing a signal path from 1427MHz to 2690MHz. Grounding capacitors C1 and C2 form zeros in the low-pass stopband, enhancing the out-of-band rejection of the low-pass filter. The introduced bridging capacitor C5 and grounding inductor L3 form transmission zeros in the low-end stopband of the high-frequency path, while the introduced grounding capacitors C6 and C7 form transmission zeros in the high-end stopband of the high-frequency path, effectively improving the stopband attenuation of the high-frequency path. Furthermore, the use of a higher-order approach effectively widens the high-frequency bandwidth. Low-frequency port 2 is the low-frequency input / output port, and high-frequency port 3 is the high-frequency input / output port.

[0050] refer to Figures 2 to 18 As shown, the LCTT multilayer duplexer to be protected by this utility model includes a ceramic substrate, a connection port disposed on the bottom surface of the ceramic substrate, and a circuit structure layer disposed inside the ceramic substrate. The circuit structure layer includes: a first layer, on which mutually insulating layers 1-1, 1-2, 1-3, 1-4, 1-5, and 1-6 are printed on the ceramic dielectric substrate.

[0051] The second layer consists of three mutually insulated metal planes: a first metal plane 2-1, a second metal plane 2-2, and a third metal plane 2-3. The first metal plane 2-1 is connected to the fifth metal plane 1-5 of the first layer via a first conductive post 4. The first metal plane 2-1 is connected to the first metal plane 1-1 of the first layer via a second conductive post 5. The second metal plane 2-2 is connected to the second metal plane 1-2 of the first layer via a third conductive post 6.

[0052] The third layer comprises three mutually insulated metal planes: a first metal plane 3-1, a second metal plane 3-2, a third metal plane 3-3, and a fourth metal plane 3-4, printed on a ceramic dielectric substrate. The third metal plane 3-3 is connected to the third metal plane 1-3 of the first layer via a fourth conductive post 7, and the fourth metal plane 3-4 is connected to the third metal plane 2-3 of the second layer via a fifth conductive post 8. The first metal plane 2-1 of the second layer and the first metal plane 3-1 of the third layer form a grounding capacitor C1; the second metal plane 2-2 of the second layer and the second metal plane 3-2 of the third layer form a capacitor C3; the third metal plane 2-3 of the second layer and the third metal plane 3-3 of the third layer form a grounding capacitor C6; and the second metal plane 2-2 of the second layer and the fourth metal plane 3-4 of the third layer form a bridging capacitor C5.

[0053] The fourth layer consists of three mutually insulated metal planes: a first metal plane 4-1, a second metal plane 4-2, and a third metal plane 4-3. The third metal plane 4-3 is connected to the sixth metal plane 1-6 of the first layer via a sixth conductive post 9, and the second metal plane 4-2 is connected to the second metal plane 3-2 of the third layer via a seventh conductive post 10. The first metal plane 4-1 and the third metal plane 3-3 together form a grounding capacitor C7. The second metal plane 4-2, the fourth metal plane 3-4, and the second metal plane 5-2 together form a capacitor C4.

[0054] The fifth layer comprises three mutually insulated metal planes: a first metal plane 5-1, a second metal plane 5-2, and a third metal plane 5-3. The third metal plane 5-3 is connected to the first metal plane 2-1 via an eighth conductive post 11. The first metal plane 5-1 is connected to the fourth metal plane 1-4 via a ninth conductive post 12. The second metal plane 5-2 and the fourth metal plane 3-4 are connected via a tenth conductive post 13. The first metal plane 5-1, the first metal plane 4-1, and the first metal plane 6-1 together form capacitor C8. The third metal plane 5-3, the third metal plane 4-3, the first metal plane 2-1, and the second metal plane 6-2 together form grounding capacitor C2.

[0055] The sixth layer has a first metal plane 6-1 and a second metal plane 6-2 of the sixth layer that are insulated from each other printed on the ceramic dielectric substrate. The first metal plane 6-1 of the sixth layer is connected to the first metal plane 4-1 of the fourth layer through the eleventh conductive post 14, and the second metal plane 6-2 of the sixth layer is connected to the third metal plane 4-3 of the fourth layer through the twelfth conductive post 15.

[0056] The seventh layer has three mutually insulated metal coils 7-1, 7-2, and 7-3 printed on a ceramic dielectric substrate. One end of the third metal coil 7-3 (labeled 7-3b) is connected to the second metal plane 5-2 of the fifth layer via a thirteenth conductive post 16. One end of the second metal coil 7-2 (labeled 7-2a) is connected to the first metal plane 5-1 of the fifth layer via a fourteenth conductive post 17. One end of the first metal coil 7-1 (labeled 7-1b) is connected to the second metal plane 6-2 of the sixth layer via a fifteenth conductive post 18.

[0057] The eighth layer has a first metal coil 8-1 and a second metal coil 8-2 printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil 8-1 (labeled 8-1b) is connected to the other end of the first metal coil 7-1 (labeled 7-1a) through the sixteenth conductive post 19, and one end of the second metal coil 8-2 (labeled 8-2a) is connected to the other end of the second metal coil 7-2 (labeled 7-2b) through the seventeenth conductive post 20.

[0058] The ninth layer has a first metal coil 9-1 and a second metal coil 9-2 printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil 9-1 (labeled 9-1b) is connected to the other end of the first metal coil 8-1 (labeled 8-1a) of the eighth layer through the eighteenth conductive post 21. One end of the second metal coil 9-2 (labeled 9-2a) is connected to the other end of the second metal coil 8-2 (labeled 8-2b) of the eighth layer through the nineteenth conductive post 22.

[0059] The tenth layer has two mutually insulated metal coils, a first metal coil 10-1 and a second metal coil 10-2, printed on a ceramic dielectric substrate. One end of the first metal coil 10-1 (labeled 10-1a) is connected to the first metal plane 3-1 of the third layer via a twentieth conductive post 23. One end of the second metal coil 10-2 (labeled 10-2a) is connected to the third metal plane 3-3 of the third layer via a twenty-first conductive post 24. The other end of the first metal coil 10-1 (labeled 10-1b) is connected to the other end of the first metal coil 9-1 (labeled 9-1a) of the ninth layer. The layers are connected by the twenty-second conductive post 25, and the other end of the second metal coil 10-2 of layer ten (labeled 10-2b) is connected to the other end of the second metal coil 9-2 of layer nine (labeled 9-2b) by the twenty-third conductive post 26; the first metal coil 7-1 of layer seven, the first metal coil 8-1 of layer eight, the first metal coil 9-1 of layer nine, and the first metal coil 10-1 of layer ten together form inductor L2; the second metal coil 7-2 of layer seven, the second metal coil 8-2 of layer eight, the second metal coil 9-2 of layer nine, and the second metal coil 10-2 of layer ten together form grounding inductor L5;

[0060] The eleventh layer has a first metal coil 11-1 printed on a ceramic dielectric substrate. One end of the first metal coil 11-1 (labeled 11-1a) is connected to one end of the first metal coil 10-1 (labeled 10-1a) through a twenty-fourth conductive post 27.

[0061] The twelfth layer has three mutually insulated metal coils printed on a ceramic substrate: a first metal coil 12-1, a second metal coil 12-2, and a third metal coil 12-3. One end of the second metal coil 12-2 (labeled 12-2a) is connected to the second metal plane 4-2 of the fourth layer via a twenty-fifth conductive post 28. One end of the third metal coil 12-3 (labeled 12-3b) is connected to the other end of the third metal coil 7-3 (labeled 7-3a) of the seventh layer via a twenty-sixth conductive post 29. One end of the first metal coil 12-1 (labeled 12-1a) is connected to the other end of the first metal coil 11-1 (labeled 11-1b) of the eleventh layer via a twenty-seventh conductive post 30.

[0062] The thirteenth layer has three mutually insulated metal coils printed on a ceramic substrate: a first metal coil 13-1, a second metal coil 13-2, and a third metal coil 13-3. One end of the first metal coil 13-1 (labeled 13-1a) is connected to the other end of the first metal coil 12-1 (labeled 12-1b) via a twenty-eighth conductive post 31. One end of the second metal coil 13-2 (labeled 13-2a) is connected to the other end of the second metal coil 12-2 (labeled 12-2b) via a twenty-ninth conductive post 32. One end of the third metal coil 13-3 (labeled 13-3b) is connected to the other end of the third metal coil 12-3 (labeled 12-3a) via a thirtieth conductive post 33.

[0063] The fourteenth layer comprises three mutually insulated metal coils: a first metal coil 14-1, a second metal coil 14-2, and a third metal coil 14-3. One end of the first metal coil 14-1 (labeled 14-1a) is connected to the second metal plane 2-2 of the second layer via a 31-conductive post 34. One end of the second metal coil 14-2 (labeled 14-2a) is connected to one end of the second metal coil 10-2 (labeled 10-2a) of the tenth layer via a 32-conductive post 35. One end of the third metal coil 14-3 (labeled 14-3b) is connected to the first metal plane 6-1 of the sixth layer. The other end of the first metal coil 14-1 of layer fourteen (labeled 14-1b) is connected to the other end of the first metal coil 13-1 of layer thirteen (labeled 13-1b) via the thirty-three conductive posts 36. The other end of the second metal coil 14-2 of layer fourteen (labeled 14-2b) is connected to the other end of the second metal coil 13-2 of layer thirteen (labeled 13-2b) via the thirty-five conductive posts 38. The other end of the third metal coil 14-3 of layer fourteen (labeled 14-3a) is connected to the other end of the third metal coil 13-3 of layer thirteen (labeled 13-3a) via the thirty-six conductive posts 39. The first metal coil 11-1 of layer eleven, the first metal coil 12-1 of layer twelve, the first metal coil 13-1 of layer thirteen, and the first metal coil 14-1 of layer fourteen together form inductor L1; the second metal coil 12-2 of layer twelve, the second metal coil 13-2 of layer thirteen, and the second metal coil 14-2 of layer fourteen together form grounding inductor L3; the third metal coil 7-3 of layer seven, the third metal coil 12-3 of layer twelve, the third metal coil 13-3 of layer thirteen, and the third metal coil 14-3 of layer fourteen together form inductor L4.

[0064] The connection ports include port P1, port P2, port P3, port P4, port P5, and port P6. Ports P1, P3, and P5 are all ground ports; port P2 is public port 1; port P6 is low-frequency port 2; and port P4 is high-frequency port 3. Layer 1's first metal plane 1-1 is connected to port P1; layer 1's second metal plane 1-2 is connected to port P2; layer 1's third metal plane 1-3 is connected to port P3; layer 1's fourth metal plane 1-4 is connected to port P4; layer 1's fifth metal plane 1-5 is connected to port P5; and layer 1's sixth metal plane 1-6 is connected to port P6. The top surface of the ceramic substrate is printed with a direction indicator pattern. It should be noted that the metal planes in layers 2 through 6 are all capacitor substrates.

[0065] refer to Figure 4 As shown, within parentheses of each curve name, 1 represents the common port, 2 represents the high-frequency port output, and 3 represents the low-frequency port output. Figures 5 to 18 In the diagram, each circle represents the cross-section of the corresponding conductive post, and they are not numbered. Those skilled in the art can easily understand this by... Figure 3 The inference is made as shown, and the corresponding conductive column's symbol is obtained without any doubt. The corresponding symbol is clear and easy to understand, so it will not be elaborated on here.

[0066] This invention is based on LTCC technology and employs a lumped parameter model to design a novel miniaturized, wideband, low-insertion-loss LTCC duplexer to meet the specific electrical performance requirements. The low-frequency path uses a second-order low-pass filter, while the high-frequency band is enhanced by introducing a bridging capacitor to create a transmission zero in the low-frequency passband, thus improving the high-frequency passband's low-frequency suppression capability. Furthermore, a higher-order design effectively and simply widens the high-frequency passband range. This invention not only effectively achieves frequency division between low-frequency and high-frequency signals, effectively widening the high-frequency passband bandwidth, but also boasts a size of only 1.6mm*0.8mm*0.7mm. It offers advantages such as miniaturization, low loss, high suppression, high isolation, high reliability, low cost, excellent consistency, and suitability for large-scale production. Additionally, it adapts to the new trend of electronic component integration and miniaturization.

[0067] In summary, the technical solution of this utility model can fully and effectively achieve the aforementioned objectives. Furthermore, the structure and functional principles of this utility model have been fully verified in the embodiments, achieving the expected effects and objectives. Without departing from the principles and essence of this utility model, various changes or modifications can be made to the embodiments. Therefore, this utility model includes all substitutions within the scope mentioned in the patent application claims, and any equivalent changes made within the scope of this patent application are within the scope of the patent application.

Claims

1. An LTCC multilayer duplexer, characterized in that, It includes a ceramic substrate, a connection port disposed on the bottom surface of the ceramic substrate, and a circuit structure layer disposed inside the ceramic substrate, wherein the circuit structure layer includes: The first layer consists of a first metal plane (1-1), a second metal plane (1-2), a third metal plane (1-3), a fourth metal plane (1-4), a fifth metal plane (1-5), and a sixth metal plane (1-6) that are mutually insulated on a ceramic dielectric substrate. The second layer consists of a first metal plane (2-1), a second metal plane (2-2), and a third metal plane (2-3) that are mutually insulated on a ceramic dielectric substrate. The first metal plane (2-1) of the second layer is connected to the fifth metal plane (1-5) of the first layer through a first conductive post (4). The first metal plane (2-1) of the second layer is connected to the first metal plane (1-1) of the first layer through a second conductive post (5). The second metal plane (2-2) of the second layer is connected to the second metal plane (1-2) of the first layer through a third conductive post (6). The third layer consists of three mutually insulated metal planes: a first metal plane (3-1), a second metal plane (3-2), a third metal plane (3-3), and a fourth metal plane (3-4). The third metal plane (3-3) is connected to the third metal plane (1-3) of the first layer via a fourth conductive post (7), and the fourth metal plane (3-4) is connected to the third metal plane (2-3) of the second layer via a fifth conductive post (8). The fourth layer consists of a first metal plane (4-1), a second metal plane (4-2), and a third metal plane (4-3) that are mutually insulated on a ceramic dielectric substrate. The third metal plane (4-3) is connected to the sixth metal plane (1-6) of the first layer by a sixth conductive post (9), and the second metal plane (4-2) of the fourth layer is connected to the second metal plane (3-2) of the third layer by a seventh conductive post (10). The fifth layer consists of three mutually insulated metal planes: a first metal plane (5-1), a second metal plane (5-2), and a third metal plane (5-3). The third metal plane (5-3) is connected to the first metal plane (2-1) via an eighth conductive post (11). The first metal plane (5-1) is connected to the fourth metal plane (1-4) via a ninth conductive post (12). The second metal plane (5-2) and the fourth metal plane (3-4) are connected via a tenth conductive post (13). The sixth layer has a first metal plane (6-1) and a second metal plane (6-2) of the sixth layer printed on a ceramic dielectric substrate. The first metal plane (6-1) of the sixth layer is connected to the first metal plane (4-1) of the fourth layer through an eleventh conductive post (14), and the second metal plane (6-2) of the sixth layer is connected to the third metal plane (4-3) of the fourth layer through a twelfth conductive post (15). The seventh layer has a first metal coil (7-1), a second metal coil (7-2), and a third metal coil (7-3) printed on a ceramic dielectric substrate. One end of the third metal coil (7-3) is connected to the second metal plane (5-2) of the fifth layer through a thirteenth conductive post (16). One end of the second metal coil (7-2) is connected to the first metal plane (5-1) of the fifth layer through a fourteenth conductive post (17). One end of the first metal coil (7-1) is connected to the second metal plane (6-2) of the sixth layer through a fifteenth conductive post (18). The eighth layer has a first metal coil (8-1) and a second metal coil (8-2) printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil (8-1) is connected to the other end of the first metal coil (7-1) of the seventh layer through a sixteenth conductive post (19), and one end of the second metal coil (8-2) of the eighth layer is connected to the other end of the second metal coil (7-2) of the seventh layer through a seventeenth conductive post (20). The ninth layer has a first metal coil (9-1) and a second metal coil (9-2) printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil (9-1) is connected to the other end of the first metal coil (8-1) of the eighth layer through an eighteenth conductive post (21), and one end of the second metal coil (9-2) of the ninth layer is connected to the other end of the second metal coil (8-2) of the eighth layer through a nineteenth conductive post (22). The tenth layer has a first metal coil (10-1) and a second metal coil (10-2) printed on a ceramic dielectric substrate, which are insulated from each other. One end of the first metal coil (10-1) is connected to the first metal plane (3-1) of the third layer through the twentieth conductive post (23). One end of the second metal coil (10-2) is connected to the third metal plane (3-3) of the third layer through the twentieth conductive post (24). The other end of the first metal coil (10-1) is connected to the other end of the first metal coil (9-1) of the ninth layer through the twentieth conductive post (25). The other end of the second metal coil (10-2) is connected to the other end of the second metal coil (9-2) of the ninth layer through the twentieth conductive post (26). The eleventh layer has a first metal coil (11-1) printed on a ceramic dielectric substrate. One end of the first metal coil (11-1) of the eleventh layer is connected to one end of the first metal coil (10-1) of the tenth layer through a twenty-fourth conductive post (27). The twelfth layer has a first metal coil (12-1), a second metal coil (12-2), and a third metal coil (12-3) printed on a ceramic dielectric substrate. One end of the second metal coil (12-2) is connected to the second metal plane (4-2) of the fourth layer through a twenty-fifth conductive post (28). One end of the third metal coil (12-3) is connected to the other end of the third metal coil (7-3) of the seventh layer through a twenty-sixth conductive post (29). One end of the first metal coil (12-1) is connected to the other end of the first metal coil (11-1) of the eleventh layer through a twenty-seventh conductive post (30). The thirteenth layer has three mutually insulated metal coils: a first metal coil (13-1), a second metal coil (13-2), and a third metal coil (13-3). One end of the first metal coil (13-1) is connected to the other end of the first metal coil (12-1) of the twelfth layer through a twenty-eighth conductive post (31). One end of the second metal coil (13-2) is connected to the other end of the second metal coil (12-2) of the twelfth layer through a twenty-ninth conductive post (32). One end of the third metal coil (13-3) is connected to the other end of the third metal coil (12-3) of the twelfth layer through a thirtieth conductive post (33). The fourteenth layer comprises three mutually insulated metal coils: a first metal coil (14-1), a second metal coil (14-2), and a third metal coil (14-3). One end of the first metal coil (14-1) is connected to the second metal plane (2-2) of the second layer via thirty-one conductive posts (34). One end of the second metal coil (14-2) is connected to one end of the second metal coil (10-2) of the tenth layer via thirty-two conductive posts (35). One end of the third metal coil (14-3) is connected to the first metal plane (2-2) of the sixth layer via thirty-two conductive posts (35). The metal planes (6-1) are connected by thirty-three conductive posts (36), the other end of the first metal coil (14-1) of layer fourteen is connected to the other end of the first metal coil (13-1) of layer thirteen by thirty-four conductive posts (37), the other end of the second metal coil (14-2) of layer fourteen is connected to the other end of the second metal coil (13-2) of layer thirteen by thirty-five conductive posts (38), and the other end of the third metal coil (14-3) of layer fourteen is connected to the other end of the third metal coil (13-3) of layer thirteen by thirty-six conductive posts (39).

2. The LTCC multilayer duplexer according to claim 1, characterized in that: The connection ports include a first port (P1), a second port (P2), a third port (P3), a fourth port (P4), a fifth port (P5), and a sixth port (P6).

3. The LTCC multilayer duplexer according to claim 2, characterized in that: The first port (P1), the third port (P3) and the fifth port (P5) are all grounded ports, the second port (P2) is the public port (1), the sixth port (P6) is the low-frequency port (2), and the fourth port (P4) is the high-frequency port (3).

4. An LTCC multilayer duplexer according to claim 3, characterized in that: The first metal plane (1-1) of layer one is connected to the first port (P1), the second metal plane (1-2) of layer one is connected to the second port (P2), the third metal plane (1-3) of layer one is connected to the third port (P3), the fourth metal plane (1-4) of layer one is connected to the fourth port (P4), the fifth metal plane (1-5) of layer one is connected to the fifth port (P5), and the sixth metal plane (1-6) of layer one is connected to the sixth port (P6).

5. An LTCC multilayer duplexer according to claim 1, characterized in that: The top surface of the ceramic substrate is printed with a directional marking pattern.

6. An LTCC multilayer duplexer according to claim 1, characterized in that: The metal planes in the second to sixth layers are all capacitor substrates.

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