Chip bonding structure and electronic device

Abstract

The utility model discloses a kind of chip bonding structure and electronic device, it is related to chip bonding packaging technical field, wherein, chip bonding structure includes substrate and first chip;Substrate has first area;First chip is located in first area, and bonding point is provided on first chip, bonding point is connected with first lead and second lead, and first lead and second lead are used to respectively apply opposite stress to bonding point when testing.The technical scheme provided by the utility model can improve cycle test life.

Description

Technical Field

[0001] This utility model relates to the field of chip bonding and packaging technology, and in particular to a chip bonding structure and electronic device. Background Technology

[0002] For chip bonding and packaging technology, PCsec (Power Cycling) testing is usually performed. Due to the alternating hot and cold cycles and the impact of current, the bonding points are subjected to stress, which may cause them to fall off. As a result, the lower bridge FRD (Fast Recovery Diode) has a low number of interval cycles in PCsec testing, resulting in a low cycle test life. Utility Model Content

[0003] The main objective of this invention is to propose a chip bonding structure and electronic device that aims to improve cycle test lifespan.

[0004] To achieve the above objectives, this utility model proposes a chip bonding structure, comprising:

[0005] A substrate having a first region;

[0006] A first chip is disposed in the first region. The first chip has a bonding point, and the bonding point is connected to a first lead and a second lead. The first lead and the second lead are used to apply opposite stresses to the bonding point respectively during testing.

[0007] In one embodiment, the first lead and the second lead are used to apply opposite stresses of equal magnitude to the bonding point during testing.

[0008] In one embodiment, the first lead and the second lead are symmetrically distributed along the centerline passing through the bonding point.

[0009] In one embodiment, the substrate further has an independent potential region and a second region located on opposite sides of the first region, and the first lead and the second lead extend to the independent potential region and the second region, respectively.

[0010] In one embodiment, the first chip has a plurality of bonding points spaced apart along a first direction, and each of the bonding points is connected to a first lead and a second lead extending toward the independent potential region and the second region, respectively.

[0011] In one embodiment, the independent potential region is provided with an independent potential element, one end of the first lead is connected to the bonding point, and the other end of the first lead is connected to the independent potential element.

[0012] In one embodiment, the independent potentiometer includes a conductive portion and an insulating portion, with one end of the first lead away from the bonding point connected to the conductive portion, and the insulating portion disposed on the conductive portion for isolating the conductive portion from external conductive structures.

[0013] In one embodiment, the independent potential element is an island or an insulating structural element.

[0014] In one embodiment, the second region is provided with a second chip, one end of the second lead is connected to the bonding point, and the other end of the second lead is connected to the second chip.

[0015] To achieve the above objectives, this utility model also proposes an electronic device, including a device body and a chip bonding structure as described above, wherein the chip bonding structure is disposed on the device body.

[0016] The technical solution of this utility model involves connecting a first lead and a second lead to the bonding point of the first chip. During PCsec testing, under alternating heating and cooling cycles and current surges, the first and second leads can apply opposite stresses to the corresponding bonding points during testing. This transforms the stress generated at the bonding points during PCsec testing from unilateral to bilateral, achieving mutual cancellation of bidirectional stress. This reduces the risk of bonding points detaching due to stress, increases the number of interval cycles in PCsec testing, and effectively improves the cycle life. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 A schematic diagram of an embodiment of the chip bonding structure provided by this utility model;

[0019] Figure 2 for Figure 1 A partial structural diagram;

[0020] Figure 3 for Figure 2 A partial structural diagram.

[0021] Explanation of icon numbers:

[0022] label name label name 100 Chip bonding structure 20 First chip 10 base 21 bonding point a First District 30 First lead b Independent potential region 40 Second lead c Second Zone 50 isolated island d First direction 60 Second chip

[0023] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present utility model.

[0025] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0026] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0027] For chip bonding and packaging technology, PCsec (Power Cycling) testing is usually performed. Due to the stress caused by thermal cycling and current impact, the bonding points are subjected to stress, which may lead to the risk of detachment. As a result, the lower bridge FRD (Fast Recovery Diode) has a low number of interval cycles in PCsec testing, resulting in a low cycle test life.

[0028] Based on the above problems, this utility model proposes a chip bonding structure 100, which aims to improve the cycle test life.

[0029] Please see Figures 1 to 3In one embodiment of the present invention, the chip bonding structure 100 includes a substrate 10 and a first chip 20; the substrate 10 has a first region a; the first chip 20 is disposed in the first region a, and the first chip 20 is provided with a bonding point 21, the bonding point 21 is connected to a first lead 30 and a second lead 40, the first lead 30 and the second lead 40 are used to apply opposite stresses to the bonding point 21 respectively during testing.

[0030] The technical solution of this utility model involves connecting a first lead 30 and a second lead 40 to the bonding point 21 of the first chip 20. During PCsec testing, under alternating heating and cooling cycles and current surges, the first lead 30 and the second lead 40 can apply opposite stresses to the corresponding bonding point 21 during testing. This transforms the stress generated on the bonding point 21 during PCsec testing from unilateral to bilateral, achieving mutual cancellation of bidirectional stress. This reduces the risk of the bonding point 21 detaching due to stress, increases the number of interval cycles in PCsec testing, and effectively improves the cycle test life.

[0031] In this embodiment, the substrate 10 serves as a carrier for the first chip 20, the first lead 30, the second lead 40, and other structures. When the chip bonding structure 100 is applied to an electronic device, it can be encapsulated using a package.

[0032] In practical applications, the first lead 30 and the second lead 40 can apply opposite stresses to the bonding point 21 during testing, and the magnitudes can be the same or different. As long as the stress generated on the bonding point 21 during the PCsec test due to alternating hot and cold cycles and current surges can be transformed from unilateral stress to bilateral stress, so that the stress on the bonding point 21 can be released to a certain extent through the first lead 30.

[0033] Furthermore, the length, dimensions, and other parameters of the first lead 30 and the second lead 40 can be the same or different, depending on the actual application.

[0034] In practical applications, the first lead 30 and the second lead 40 can be made of conductive materials such as copper, aluminum, and silver.

[0035] Furthermore, the first lead 30 and the second lead 40 can be connected to the corresponding bonding point 21 by means of welding, bonding, screw connection, snap-fit, etc. Of course, in some embodiments, in order to ensure the reliability of the connection between the first lead 30 and the second lead 40 and the bonding point 21, welding can be used to connect the first lead 30 and the second lead 40 to the corresponding bonding point 21.

[0036] Please see Figures 1 to 3 In one embodiment of the present invention, the first lead 30 and the second lead 40 are used to apply opposite stresses of the same magnitude to the bonding point 21 during testing.

[0037] With this configuration, during PCsec testing, under alternating heating and cooling cycles and current surges, the first lead 30 and the second lead 40 can apply opposite stresses of the same magnitude to the corresponding bonding points 21 during testing. This effectively transforms the stress on the bonding points 21 caused by alternating heating and cooling cycles and current surges during PCsec testing from unilateral to bilateral stress, allowing the stress on the bonding points 21 to be fully released through the first lead 30. This further reduces the risk of the bonding points 21 falling off due to stress and increases the number of interval cycles in PCsec testing, thereby effectively improving the cycle life.

[0038] Please see Figure 1 In one embodiment of this utility model, the first lead 30 and the second lead 40 are symmetrically distributed along the center line passing through the bonding point 21.

[0039] With this configuration, two leads of the same length and size can be used as the first lead 30 and the second lead 40. The first lead 30 and the second lead are symmetrically distributed along the center line passing through the corresponding bonding point 21. This allows the first lead 30 and the second lead 40 to apply opposite stresses of the same magnitude to the corresponding bonding point 21 during testing. This eliminates the need to separately prepare multiple leads of different lengths and sizes as the first lead 30 and the second lead 40, simplifies the manufacturing process, and enables a foolproof design to prevent installation errors.

[0040] Please see Figures 1 to 3 In one embodiment of the present invention, the substrate 10 further has independent potential regions b and second regions c located on opposite sides of the first region a, and the first lead 30 and the second lead 40 extend to the independent potential regions b and c, respectively.

[0041] This configuration, by extending the first lead 30 and the second lead 40 to the independent potential region b and the second region c respectively, makes it easier for the first lead 30 and the second lead 40 to be connected to the devices in the independent potential region b and the second region c respectively.

[0042] Please see Figure 1 In one embodiment of the present invention, the first chip 20 is provided with a plurality of bonding points 21 distributed at intervals along the first direction d, and each bonding point 21 is connected to a first lead 30 and a second lead 40 extending to an independent potential region b and a second region c, respectively.

[0043] With this configuration, by connecting a first lead 30 and a second lead 40 to each bonding point 21, during the PCsec test, under alternating hot and cold cycles and current surges, the stress generated on the first lead 30 and the stress generated on the second lead 40 can cancel each other out. This transforms the stress on each bonding point 21 from unilateral to bilateral under alternating hot and cold cycles and current surges, allowing the stress on the bonding point 21 to be released to a certain extent through the first lead 30. This reduces the creep rate of the bonding point 21 during the PCsec test, thereby significantly reducing the risk of the bonding point 21 falling off due to stress. It also increases the number of interval cycles in the PCsec test, effectively improving the cycle test life, for example, by more than 50%.

[0044] In some embodiments, the direction from the first lead 30 to the second lead 40 is defined as the lead arrangement direction, and the first direction d may be set at an angle to the lead arrangement direction.

[0045] Please see Figures 1 to 3 In one embodiment of this utility model, an independent potential region b is provided with an independent potential element, one end of the first lead 30 is connected to the bonding point 21, and the other end of the first lead 30 is connected to the independent potential element.

[0046] It should be noted that an independent potential component refers to a structural component whose potential is independent of the potential on the first chip 20. By setting an independent potential component in the independent potential region b, the potential on the independent potential component can be prevented from affecting the potential on the first chip 20.

[0047] With this configuration, by setting an independent potential element within the independent potential region b of the substrate 10, the potential of the independent potential element is independent of the potential on the first chip 20, thus ensuring that the potential on the independent potential element will not affect the potential on the first chip 20, thereby guaranteeing the performance of the chip bonding structure 100. At the same time, by connecting the end of the first lead 30 away from the bonding point 21 to the independent potential element, the first lead 30 can be pulled by the independent potential element. In this way, during PCsec testing, under alternating hot and cold cycles and current surges, the first lead 30 can better apply the corresponding stress to the corresponding bonding point 21 during testing.

[0048] In practical applications, independent potential components can be fixedly connected to the independent potential region b of the substrate 10 by means of welding, bonding, screw connection, snap-fit, etc.

[0049] In one embodiment of this utility model, the independent potential element includes a conductive part and an insulating part. The end of the first lead 30 away from the bonding point 21 is connected to the conductive part, and the insulating part is disposed on the conductive part. The insulating part is used to isolate the conductive part from the external conductive structure.

[0050] With this configuration, the first lead 30 is pulled by the conductive part. During PCsec testing, under alternating hot and cold cycles and current surges, the first lead 30 can better apply the corresponding stress to the corresponding bonding point 21. At the same time, the insulating part isolates the conductive part from the external conductive structure, preventing conduction between the conductive part and the external conductive structure. This ensures that the potential of the conductive part is independent not only from the potential on the first chip, but also from the potential of the external conductive structure, thus preventing the potential of the conductive part from affecting the positioning on the first chip and the potential of the external conductive structure.

[0051] In practical applications, the insulating part can be provided to wrap around the conductive part so that the first lead 30 passes through the insulating part and connects to the conductive part; or, the insulating part can be provided on the periphery of the conductive part to isolate the conductive part from the external conductive structure.

[0052] It should be noted that external conductive structures can refer to components such as circuit boards and resistors in electronic devices.

[0053] Please see Figures 1 to 3 In one embodiment of this utility model, the independent potential element is an island 50 or an insulating structural element.

[0054] With this configuration, by using island 50 or insulating structural components as independent potential components, island 50 phenomenon or insulation phenomenon can be generated in the independent potential region b of substrate 10, so that the circuit has a current path in the independent potential region b but no current actually flows through it. This can effectively prevent the potential on island 50 or insulating structural components from affecting the potential on the first chip 20.

[0055] It should be noted that insulating structural components refer to structural components with insulating parts, and do not mean that all structures are insulating structures. For example, insulating structural components can be copper-clad ceramic substrates, or other structural components that include both conductive and insulating parts.

[0056] In some embodiments, the island 50 can be a structure formed by tightly bonding metal to a ceramic substrate using active metal brazing.

[0057] Please see Figure 1 In one embodiment of the present invention, a second chip 60 is provided in the second region c, one end of the second lead 40 is connected to the bonding point 21, and the other end of the second lead 40 is connected to the second chip 60.

[0058] This configuration is because the second chip 60 is located in the second region c. During use, the second lead 40 is typically used to achieve the bonding connection between the first chip 20 and the second chip 60. Therefore, during PCsec testing, under alternating hot and cold cycles and current surges, the second lead 40 will generate a first stress pulling towards the bonding point 21. At the same time, the first lead 30 will also generate a second stress pulling towards the bonding point 21. Since the first stress and the second stress are in opposite directions, the second stress can at least partially offset the first stress, thereby effectively releasing the stress generated by the second lead 40 under alternating hot and cold cycles and current surges through the first lead 30.

[0059] Please see Figures 1 to 3 In one embodiment of this utility model, the first lead 30 and / or the second lead 40 are arc-shaped lines.

[0060] This configuration, by using curved lines as the first lead 30 and / or the second lead 40, can avoid interference between the first lead 30 and / or the second lead 40 and other devices; and the curved line design can provide a more stable bonding effect to meet the design requirements of chip packaging, thereby improving bonding quality and reliability.

[0061] Please see Figures 1 to 3 In one embodiment of this utility model, the first lead 30 and / or the second lead 40 are copper wires or aluminum wires.

[0062] This configuration, using copper or aluminum wires as the first lead 30 and / or the second lead 40, provides excellent electrical and thermal conductivity, thereby improving the chip's performance and reliability.

[0063] This utility model also proposes an electronic device, which includes a device body and a chip bonding structure 100. The specific structure of the chip bonding structure 100 is as described in the above embodiments. Since this electronic device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The chip bonding structure 100 is disposed on the device body.

[0064] The above description is merely an exemplary embodiment of the present utility model and does not limit the patent scope of the present utility model. Any equivalent structural transformations made based on the technical concept of the present utility model and the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.

Claims

1. A chip bonding structure, characterized in that, include: A substrate having a first region; A first chip is disposed in the first region. The first chip has a bonding point, and the bonding point is connected to a first lead and a second lead. The first lead and the second lead are used to apply opposite stresses to the bonding point respectively during testing.

2. The chip bonding structure as described in claim 1, characterized in that, The first lead and the second lead are used to apply opposite stresses of equal magnitude to the bonding point during testing.

3. The chip bonding structure as described in claim 2, characterized in that, The first lead and the second lead are symmetrically distributed along the center line passing through the bonding point.

4. The chip bonding structure as described in any one of claims 1 to 3, characterized in that, The substrate also has an independent potential region and a second region located on opposite sides of the first region, and the first lead and the second lead extend to the independent potential region and the second region, respectively.

5. The chip bonding structure as described in claim 4, characterized in that, The first chip has a plurality of bonding points spaced apart along a first direction, and each bonding point is connected to a first lead and a second lead extending into the independent potential region and the second region, respectively.

6. The chip bonding structure as described in claim 4, characterized in that, The independent potential region is provided with an independent potential element, one end of the first lead is connected to the bonding point, and the other end of the first lead is connected to the independent potential element.

7. The chip bonding structure as described in claim 6, characterized in that, The independent potentiometer includes a conductive part and an insulating part. The end of the first lead away from the bonding point is connected to the conductive part. The insulating part is disposed on the conductive part and is used to isolate the conductive part from external conductive structures.

8. The chip bonding structure as described in claim 7, characterized in that, The independent potential element is an island or an insulating structural element.

9. The chip bonding structure as described in claim 4, characterized in that, The second region is provided with a second chip, one end of the second lead is connected to the bonding point, and the other end of the second lead is connected to the second chip.

10. An electronic device, characterized in that, It includes a device body and a chip bonding structure as described in any one of claims 1 to 9, wherein the chip bonding structure is disposed on the device body.

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