Switching tube envelope circuit and electronic device

Abstract

The application relates to a switching tube blocking circuit and electronic equipment, and belongs to the technical field of electronic circuits. The switching tube blocking circuit is arranged between a control circuit and a buffer circuit, the buffer circuit is connected with a switching tube, the switching tube blocking circuit comprises a logic circuit, when the power supply voltage of the control circuit is less than a preset voltage, the logic circuit outputs a blocking signal to the buffer circuit, so that the buffer circuit stops buffering the control signal of the control circuit, and the switching tube is blocked; thus, the logic circuit can also make the output of the buffer circuit be in a high resistance state in response to an enabling signal output by the control circuit in the case that the control signal is disconnected, so as to block the switching tube and reduce the possibility of the switching tube being mis-conducted in the case that the control signal is disconnected, and the reliability and safety of the switching tube blocking circuit are improved.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a switching transistor blocking circuit and electronic equipment. Background Technology

[0002] Switching transistors are widely used in industrial control. Their drive circuit design requires controllability to prevent accidental turn-on. Figure 1 The diagram shows the relevant switching transistor control logic. The control circuit is usually powered by the supply voltage VCC (e.g., 3.3V). The 3.3V supply is usually generated from a 5V supply through a linear power supply. Chips using this type of linear power supply often require the 5V supply to rise above 3.3V by a certain voltage, such as 4V, before a 3.3V power output can be generated. In order to ensure that the switching transistor drive circuit can reliably control the switching transistor and to give the drive circuit a certain anti-interference capability, the buffer in the buffer circuit is usually powered by a 5V supply. This allows the high-level 3.3V pulse signal generated by the control circuit to be converted into a high-level 5V pulse signal by the buffer. When the switching transistor needs to be turned on, the control circuit first turns on the buffer and then sends a switching transistor drive signal. The switching transistor drive signal then passes through the switching transistor drive circuit to control the switching transistor to turn on or off.

[0003] During power-up, the buffer typically operates normally once the power supply voltage reaches 3V or higher. Therefore, when the actual 5V power supply voltage rises to the buffer's minimum operating voltage, the buffer is already operational. However, if the control circuit hasn't reached its minimum operating voltage and hasn't initialized, its output signal remains uncontrollable. This uncontrollable output signal can then be transmitted to the switching transistor via the buffer and drive circuit, posing a risk of accidental switching on and potentially damaging the transistor, creating a safety hazard. To address this, a switching transistor blocking circuit is implemented. When the control circuit's supply voltage VCC is lower than a preset voltage (3.3V), the circuit outputs a monitoring signal to block the buffer. However, this blocking circuit often fails when the control circuit disconnects the pulse signal and its supply voltage exceeds the preset voltage. The uncontrollable state of the buffer circuit's input often leads to accidental switching on, potentially causing accidents and resulting in poor reliability and safety.

[0004] Therefore, the reliability and safety of the related switching transistor blocking circuit are poor. Utility Model Content

[0005] The purpose of this application is to provide a switching transistor blocking circuit and electronic device, which aims to solve the problems of poor reliability and safety of related switching transistor blocking circuits.

[0006] This application provides a switching transistor blocking circuit, which is disposed between a control circuit and a buffer circuit. The buffer circuit is connected to the switching transistor. The switching transistor blocking circuit includes:

[0007] A logic circuit is provided to output a blocking signal to the buffer circuit when the power supply voltage of the control circuit is less than a preset voltage, so that the buffer circuit stops buffering the control signal of the control circuit and blocks the switching transistor from conducting.

[0008] In one embodiment, the switching transistor blocking circuit further includes a monitoring circuit connected to the logic circuit. The monitoring circuit monitors the power supply voltage of the control circuit and outputs a monitoring signal to the logic circuit when the power supply voltage is less than a preset voltage, so that the logic circuit outputs the blocking signal.

[0009] In one embodiment, the logic circuit includes:

[0010] An inverting module, connected to the control circuit, is used to invert the enable signal of the control circuit when the power supply voltage of the control circuit is less than a preset voltage, so as to output an enable level signal.

[0011] A buffer module, connected to the monitoring circuit, is used to buffer the monitoring signal so as to output a monitoring level signal;

[0012] The arithmetic module, connected to the inverting module, the buffer module, and the buffer circuit, is used to perform a NAND operation on the enable level signal and the monitoring level signal to output a blocking level signal as the blocking signal.

[0013] In one embodiment, the inverting module includes an inverter and a first resistor;

[0014] The input terminal of the inverter and the first terminal of the first resistor are connected to form the input terminal of the inverter module, which is connected to the control circuit and is used to receive the enable signal when the power supply voltage of the control circuit is less than the preset voltage.

[0015] The output terminal of the inverter constitutes the output terminal of the inverting module and is connected to the arithmetic module to output the enable level signal;

[0016] The second end of the first resistor constitutes the power supply terminal of the inverting module, so as to be connected to the supply voltage.

[0017] In one embodiment, the buffer module includes a buffer;

[0018] The input terminal of the buffer constitutes the input terminal of the buffer module and is connected to the monitoring circuit to receive the monitoring signal;

[0019] The output terminal of the buffer constitutes the output terminal of the buffer module, and is connected to the arithmetic module to output the monitoring level signal.

[0020] In one embodiment, the arithmetic module includes a NAND gate, a second resistor, and a third resistor;

[0021] The first input terminal of the NAND gate constitutes the first input terminal of the arithmetic module and is connected to the inverting module to receive the enable level signal;

[0022] The second input terminal of the NAND gate and the first terminal of the second resistor are connected and together form the second input terminal of the arithmetic module, which is connected to the buffer module to receive the monitoring level signal;

[0023] The output terminal of the NAND gate and the first terminal of the third resistor are connected to form the output terminal of the arithmetic module, which is connected to the buffer circuit to output the blocking level signal as the blocking signal;

[0024] The second end of the second resistor and the second end of the third resistor are both connected to the first power supply.

[0025] In one embodiment, the monitoring circuit includes a monitoring chip, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor;

[0026] The power supply terminal of the monitoring chip, the first terminal of the fourth resistor, and the first terminal of the seventh resistor are connected and together constitute the power supply voltage input terminal of the monitoring circuit, so as to be connected to the power supply voltage;

[0027] The second end of the fourth resistor is connected to the manual reset trigger input terminal and the power fault output terminal of the monitoring chip; the first end of the fifth resistor is connected to the first power supply; the second end of the fifth resistor is connected to the first end of the sixth resistor and the power fault input terminal of the monitoring chip; and the second end of the sixth resistor is connected to the power ground.

[0028] The automatic low-reset output terminal of the monitoring chip and the second terminal of the seventh resistor are connected and together form the output terminal of the monitoring circuit, which is connected to the buffer circuit to output the monitoring signal.

[0029] In one embodiment, the buffer circuit includes a buffer chip, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor;

[0030] The first end of the eighth resistor constitutes the blocking signal input terminal of the buffer circuit and is connected to the monitoring circuit to receive the blocking signal;

[0031] The second end of the eighth resistor is connected to the enable terminal of the buffer chip;

[0032] The first input terminal of the buffer chip, the second input terminal of the buffer chip, the first terminal of the ninth resistor, and the first terminal of the tenth resistor together constitute the control signal input terminal of the buffer circuit, which is connected to the control circuit to receive the control signal.

[0033] The first output terminal of the buffer chip, the second output terminal of the buffer chip, the first terminal of the eleventh resistor, and the first terminal of the twelfth resistor together constitute the control signal output terminal of the buffer circuit to output the buffered control signal.

[0034] The second end of the ninth resistor and the second end of the tenth resistor are connected and together form the power supply voltage input terminal of the buffer circuit, so as to connect the power supply voltage;

[0035] The second terminal of the eleventh resistor and the second terminal of the twelfth resistor are both connected to the first power supply.

[0036] In one embodiment, the control circuitry includes a microprocessor;

[0037] The power supply terminal of the microprocessor constitutes the power supply voltage input terminal of the control circuit and is connected to the monitoring circuit to receive the power supply voltage.

[0038] The first general-purpose input / output terminal and the second general-purpose input / output terminal of the microprocessor constitute the control signal output terminal of the control circuit, which is connected to the buffer circuit to output the control signal;

[0039] The third general-purpose input / output terminal of the microprocessor constitutes the enable signal output terminal of the control circuit, and is connected to the logic circuit to output an enable signal.

[0040] This utility model embodiment also provides an electronic device, which includes the above-described switching transistor blocking circuit.

[0041] The beneficial effects of this utility model embodiment compared with the prior art are as follows: By placing the switching transistor blocking circuit between the control circuit and the buffer circuit, and connecting the buffer circuit to the switching transistor, the switching transistor blocking circuit includes a logic circuit. When the supply voltage of the control circuit is less than a preset voltage, the logic circuit outputs a blocking signal to the buffer circuit, so that the buffer circuit stops buffering the control signal of the control circuit, thereby blocking the switching transistor from conducting. Thus, when the control signal is disconnected, the logic circuit can also respond to the enable signal output by the control circuit to make the output of the buffer circuit high impedance, thereby blocking the switching transistor from conducting. This reduces the possibility of the switching transistor being mis-converted when the control signal is disconnected, and improves the reliability and safety of the switching transistor blocking circuit. Attached Figure Description

[0042] To more clearly illustrate the technical utility model in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of a related switching transistor control circuit.

[0044] Figure 2 This is a schematic diagram of a switching transistor blocking circuit provided in an embodiment of this application;

[0045] Figure 3 This is a schematic diagram of another structure of the switching transistor blocking circuit provided in an embodiment of this application;

[0046] Figure 4 A schematic diagram of the logic circuit in a switching transistor blocking circuit provided in an embodiment of this application;

[0047] Figure 5 This is a partial example circuit schematic diagram of a switching transistor blocking circuit provided in an embodiment of this application. Detailed Implementation

[0048] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0049] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0050] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0052] Figure 2 A schematic diagram of the switching transistor blocking circuit provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0053] The aforementioned switching transistor blocking circuit is located between the control circuit 10 and the buffer circuit 30. The buffer circuit 30 is connected to the switching transistor 90. The switching transistor blocking circuit includes a logic circuit 50.

[0054] The logic circuit 50 is used to output a blocking signal to the buffer circuit 30 when the power supply voltage of the control circuit is less than the preset voltage, so that the buffer circuit 30 stops buffering the control signal of the control circuit 10 and blocks the switching transistor 90 from conducting.

[0055] In specific implementation, the buffer circuit 30 is used to respond to the blocking signal, and the output terminal of the buffer circuit 30 becomes a high impedance state, so that the input signal of the buffer circuit 30 cannot be transmitted to the output side of the buffer circuit.

[0056] It is understandable that the preset voltage is related to the performance of the microprocessor in the control circuit 10. When the supply voltage VCC is less than the preset voltage, the control signal output by the microprocessor is in an uncontrollable state; when the supply voltage VCC is greater than or equal to the preset voltage, the control signal output by the microprocessor is in a controllable state.

[0057] like Figure 3As shown, the switching transistor blocking circuit also includes a monitoring circuit 20 connected to the logic circuit 50. The monitoring circuit 20 is used to monitor the power supply voltage of the control circuit 10. When the power supply voltage is less than the preset voltage, it outputs a monitoring signal to the logic circuit 50 so that the logic circuit 50 outputs a blocking signal.

[0058] By configuring a monitoring circuit through the above technical solution, the power supply voltage of the control circuit 10 is monitored, and the function of blocking waves during power-on is realized.

[0059] like Figure 4 As shown, the logic circuit 50 includes an inverting module 51, a buffer module 52, and an arithmetic module 53.

[0060] The inverting module 51 is connected to the control circuit 10 and is used to invert the enable signal of the control circuit 10 when the supply voltage of the circuit is less than the preset voltage, so as to output an enable level signal.

[0061] The buffer module 52 is connected to the monitoring circuit 20 and is used to buffer the monitoring signal so as to output the monitoring level signal.

[0062] The arithmetic module 53, connected to the inverting module 51, the buffer module 52 and the buffer circuit 30, is used to perform NAND operations on the enable level signal and the monitoring level signal to output a blocking level signal as a blocking signal.

[0063] Understandably, the arithmetic module 53 includes NAND gates.

[0064] The enable signal can be high, the monitoring signal can be low, and the block signal can be high.

[0065] Through the above technical solution, the logic circuit 50 can output a high-level blocking signal when a low-level monitoring signal and a high-level enable signal are input. The circuit structure is simple and reliable.

[0066] Figure 5 The illustration shows a partial example circuit structure of the switching transistor blocking circuit provided in an embodiment of the present invention. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0067] Inverting module 51 includes an inverter U1 and a first resistor R1;

[0068] The input terminal of inverter U1 and the first terminal of the first resistor R1 are connected and together form the input terminal of inverter module 51, which is connected to control circuit 10 to provide an enable signal when the supply voltage of control circuit is less than a preset voltage. The output terminal of inverter U1 forms the output terminal of inverter module 51 and is connected to arithmetic module 53 to output an enable level signal. The second terminal of the first resistor R1 forms the power supply terminal of inverter module 51 to provide the supply voltage VCC.

[0069] Understandably, the first resistor R1 pulls up the trigger signal.

[0070] Buffer module 52 includes buffer U2;

[0071] The input terminal of buffer U2 forms the input terminal of buffer module 52 and is connected to monitoring circuit 20 to receive monitoring signals; the output terminal of buffer U2 forms the output terminal of buffer module 52 and is connected to arithmetic module 53 to output monitoring level signals.

[0072] The circuit hardware design of the buffer module 52 is simple and the cost is low.

[0073] The arithmetic module 53 includes a NAND gate U3, a second resistor R2, and a third resistor R3;

[0074] The first input terminal of NAND gate U3 constitutes the first input terminal of arithmetic module 53 and is connected to inverting module 51 to receive an enable level signal; the second input terminal of NAND gate U3 is connected to the first terminal of second resistor R2 and together constitutes the second input terminal of arithmetic module 53, which is connected to buffer module 52 to receive a monitoring level signal; the output terminal of NAND gate U3 and the first terminal of third resistor R3 are connected to the first output terminal of arithmetic module 53 and together constitutes the output terminal of arithmetic module 53, which is connected to buffer circuit 30 to output a blocking level signal as a blocking signal; the second terminal of second resistor R2 and the second terminal of third resistor R3 are connected to the first power supply VAA.

[0075] Understandably, the second resistor R2 pulls up the monitoring level signal, and the third resistor R3 pulls up the blocking signal.

[0076] The monitoring circuit 20 includes a monitoring chip U5, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7;

[0077] The power supply terminal VCC of monitoring chip U5, the first end of the fourth resistor R4, and the first end of the seventh resistor R7 are connected and together form the power supply voltage VCC input terminal of monitoring circuit 20, so as to connect to the power supply voltage VCC; the second end of the fourth resistor R4 is connected to the manual reset trigger input terminal / MR and the power fault output terminal / PFO of monitoring chip U5; the first end of the fifth resistor R5 is connected to the first power supply VAA; the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the power fault input terminal PFI of monitoring chip U5; the second end of the sixth resistor R6 is connected to the power ground; the automatic low reset output terminal / RESET of monitoring chip U5 and the second end of the seventh resistor R7 are connected and together form the output terminal of monitoring circuit 20, which is connected to buffer circuit 30 to output monitoring signal.

[0078] In one embodiment, the monitoring circuit 20 further includes a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a seventh capacitor C7; the first terminal of the fourth capacitor C4 is connected to the first power supply VAA, the first terminal of the fifth capacitor C5 is connected to the second terminal of the fifth resistor R5 and the first terminal of the sixth resistor R6, the first terminal of the sixth capacitor C6 is connected to the power supply terminal VCC of the monitoring chip U5, the first terminal of the fourth resistor R4 and the first terminal of the seventh resistor R7, the first terminal of the seventh capacitor C7 is connected to the automatic low reset output terminal / RESET of the monitoring chip U5 and the second terminal of the seventh resistor R7, and the second terminals of the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are all connected to the power supply ground.

[0079] It is understandable that the monitoring circuit 20 described above monitors the supply voltage VCC and the voltage of the first power supply VAA, and outputs a monitoring signal based on the monitoring results.

[0080] The buffer circuit 30 includes a buffer chip U6, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12;

[0081] The first end of the eighth resistor R8 forms the blocking signal input terminal of the buffer circuit 30 and is connected to the monitoring circuit 20 to receive the blocking signal; the second end of the eighth resistor R8 is connected to the enable terminal EN of the buffer chip U6; the first input terminal I_0 and the second input terminal I_1 of the buffer chip U6, the first end of the ninth resistor R9 and the first end of the tenth resistor R10 together form the control signal input terminal of the buffer circuit 30 and are connected to the control circuit 10 to receive the control signal; the first output terminal O_0 and the second output terminal O_1 of the buffer chip U6, the first end of the eleventh resistor R11 and the first end of the twelfth resistor R12 together form the control signal output terminal of the buffer circuit 30 and are connected to the drive circuit 40 to output the buffered control signal; the second end of the ninth resistor R9 and the second end of the tenth resistor R10 are connected and together form the power supply voltage VCC input terminal of the buffer circuit 30 to receive the power supply voltage VCC; the second end of the eleventh resistor R11 and the second end of the twelfth resistor R12 are connected to the first power supply VAA.

[0082] Understandably, the eighth resistor R8 limits the current of the blocking signal.

[0083] In a specific implementation, a drive circuit 40 is provided between the buffer circuit 30 and the switching transistor 90. The drive circuit 40 includes a drive chip U7, a first Zener diode Z1, a second Zener diode Z2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, and a seventeenth resistor R17.

[0084] The first ends of the thirteenth resistor R13 and the fourteenth resistor R14 together form the input terminal of the drive circuit 40, which is connected to the buffer circuit 30 to receive the buffered control signal. The second end of the thirteenth resistor R13 is connected to the first end of the fifteenth resistor R15, the first end of the first capacitor C1, and the positive terminal ANODE of the drive chip U7. The second ends of the fourteenth resistor R14, the fifteenth resistor R15, the first capacitor C1, and the negative terminal CATHODE of the drive chip U7 are connected. The positive power supply terminal VCC of the drive chip U7 is connected to the first end of the second capacitor C2 and the positive power supply V+. The negative power supply terminal VEE of chip U7 is connected to the second terminal of the second capacitor C2 and the negative power supply V-. The output terminal VOUT of the driver chip U7 is connected to the first terminal of the sixteenth resistor R16. The second terminal of the sixteenth resistor R16, the first terminal of the seventeenth resistor R17, the first terminal of the third capacitor C3, and the negative terminal of the first Zener diode Z1 are connected and together form the output terminal of the driver circuit 40, which is connected to the switching transistor 90 to output a drive signal. The second terminal of the seventeenth resistor R17, the second terminal of the third capacitor C3, and the negative terminal of the second Zener diode Z2 are connected to the power supply ground. The positive terminal of the first Zener diode Z1 is connected to the positive terminal of the second Zener diode Z2.

[0085] It is understandable that the first Zener diode Z1 and the second Zener diode Z2 clamp the drive signal.

[0086] The control circuit 10 includes a microprocessor U4;

[0087] The power supply terminal VCC of the microprocessor U4 constitutes the power supply voltage VCC input terminal of the control circuit 10 and is connected to the monitoring circuit 20 to receive the power supply voltage VCC; the first general-purpose input / output terminal P1.0 and the second general-purpose input / output terminal P1.1 of the microprocessor U4 constitute the control signal output terminal of the control circuit 10 and are connected to the buffer circuit 30 to output the control signal; the third general-purpose input / output terminal P1.2 of the microprocessor U4 constitutes the enable signal output terminal of the control circuit 10 and is connected to the logic circuit 50 to output the enable signal.

[0088] The control circuit is simple and reliable.

[0089] The following is based on the working principle. Figure 5 Further explanation is provided below:

[0090] During the establishment of the power supply voltage VCC (i.e., when the power supply voltage VCC is less than the preset voltage), the control signals output from the first general-purpose input / output terminal P1.0 and the second general-purpose input / output terminal P1.1 of the microprocessor U4 are in an uncontrollable state. The microprocessor U4 also outputs a low-level enable signal from the third general-purpose input / output terminal P1.2.

[0091] Simultaneously, the power supply voltage VCC is connected to the button reset input terminal / MR and the power failure output terminal / PFO of the monitoring chip U5. In response to the power supply voltage VCC being less than the preset voltage, the monitoring chip U5 outputs a low-level monitoring signal from the automatic low reset output terminal / RESET of the monitoring chip U5.

[0092] Inverter U1 inverts the enable signal to output an enable level signal (indeterminate state); buffer U2 buffers the monitoring signal to output a monitoring level signal (low level); NAND gate U3 performs a NAND operation on the enable level signal (indeterminate state) and the monitoring level signal (low level) to output a block signal (high level).

[0093] The enable terminal EN of the buffer chip U6 is connected to a blocking signal (high level), and the first input terminal I_0 and the second input terminal I_1 of the buffer chip U6 are connected to the control signal of the uncontrollable state. In response to the blocking signal, the buffer chip U6 stops buffering the control signal and disconnects the output of the buffered control signal.

[0094] Since the positive terminal ANODE and the negative terminal CATHODE of the driver chip U7 stop receiving the buffered control signal, the output terminal VOUT of the driver chip U7 disconnects the output of the drive signal, blocking the conduction of the switch 90; thus, the drive signal of the switch 90 is blocked when the MCU output signal is in an uncontrollable state.

[0095] In another embodiment, when the microprocessor U4 disconnects the output of the control signal from the first general-purpose input / output terminal P1.0 and the second general-purpose input / output terminal P1.1 of the microprocessor U4, the microprocessor U4 outputs a high-level enable signal from the third general-purpose input / output terminal P1.2 of the microprocessor U4; the inverter U1 inverts the enable signal to output an enable level signal (low level); the buffer U2 buffers the monitoring signal to output a monitoring level signal (high level or low level); the NAND gate U3 performs a NAND operation on the enable level signal (low level) and the monitoring level signal (high level or low level) to output a block signal (high level).

[0096] The enable terminal EN of the buffer chip U6 is connected to a blocking signal (high level), and the first input terminal I_0 and the second input terminal I_1 of the buffer chip U6 are connected to the control signal of the uncontrollable state. In response to the blocking signal, the output terminal of the buffer chip U6 becomes high impedance, that is, the buffering of the control signal stops and the output of the buffered control signal is disconnected, so as to block the drive signal of the switching transistor 90. This prevents the switching transistor 90 from being accidentally turned on due to external interference when the microprocessor U4 disconnects the control signal output, and further improves the reliability and flexibility of the switching transistor blocking circuit.

[0097] This utility model embodiment also provides an electronic device, which includes the above-described switching transistor blocking circuit.

[0098] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0099] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A switching transistor blocking circuit, characterized in that, The switching transistor blocking circuit is located between the control circuit and the buffer circuit. The buffer circuit is connected to the switching transistor. The switching transistor blocking circuit includes: A logic circuit is provided to output a blocking signal to the buffer circuit when the power supply voltage of the control circuit is less than a preset voltage, so that the buffer circuit stops buffering the control signal of the control circuit and blocks the switching transistor from conducting.

2. The switching transistor blocking circuit as described in claim 1, characterized in that, The switching transistor blocking circuit further includes a monitoring circuit connected to the logic circuit. The monitoring circuit monitors the power supply voltage of the control circuit. When the power supply voltage is less than a preset voltage, it outputs a monitoring signal to the logic circuit so that the logic circuit outputs the blocking signal.

3. The switching transistor blocking circuit as described in claim 2, characterized in that, The logic circuit includes: An inverting module, connected to the control circuit, is used to invert the enable signal of the control circuit when the power supply voltage of the control circuit is less than a preset voltage, so as to output an enable level signal. A buffer module, connected to the monitoring circuit, is used to buffer the monitoring signal so as to output a monitoring level signal; The arithmetic module, connected to the inverting module, the buffer module, and the buffer circuit, is used to perform NAND operations based on the enable level signal and the monitoring level signal to output a blocking level signal as the blocking signal.

4. The switching transistor blocking circuit as described in claim 3, characterized in that, The inverting module includes an inverter and a first resistor; The input terminal of the inverter and the first terminal of the first resistor are connected to form the input terminal of the inverter module, which is connected to the control circuit and is used to receive the enable signal when the power supply voltage of the control circuit is less than the preset voltage. The output terminal of the inverter constitutes the output terminal of the inverting module and is connected to the arithmetic module to output the enable level signal; The second end of the first resistor constitutes the power supply terminal of the inverting module, so as to be connected to the supply voltage.

5. The switching transistor blocking circuit as described in claim 3, characterized in that, The buffer module includes a buffer; The input terminal of the buffer constitutes the input terminal of the buffer module and is connected to the monitoring circuit to receive the monitoring signal; The output terminal of the buffer constitutes the output terminal of the buffer module, and is connected to the arithmetic module to output the monitoring level signal.

6. The switching transistor blocking circuit as described in claim 3, characterized in that, The arithmetic module includes a NAND gate, a second resistor, and a third resistor; The first input terminal of the NAND gate constitutes the first input terminal of the arithmetic module and is connected to the inverting module to receive the enable level signal; The second input terminal of the NAND gate and the first terminal of the second resistor are connected and together form the second input terminal of the arithmetic module, which is connected to the buffer module to receive the monitoring level signal; The output terminal of the NAND gate and the first terminal of the third resistor are connected together to form the output terminal of the arithmetic module, which is connected to the buffer circuit to output a blocking level signal as the blocking signal. The second end of the second resistor and the second end of the third resistor are both connected to the first power supply.

7. The switching transistor blocking circuit as described in any one of claims 2 to 6, characterized in that, The monitoring circuit includes a monitoring chip, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; The power supply terminal of the monitoring chip, the first terminal of the fourth resistor, and the first terminal of the seventh resistor are connected and together constitute the power supply voltage input terminal of the monitoring circuit, so as to be connected to the power supply voltage; The second end of the fourth resistor is connected to the manual reset trigger input terminal and the power fault output terminal of the monitoring chip; the first end of the fifth resistor is connected to the first power supply; the second end of the fifth resistor is connected to the first end of the sixth resistor and the power fault input terminal of the monitoring chip; and the second end of the sixth resistor is connected to the power ground. The automatic low-reset output terminal of the monitoring chip and the second terminal of the seventh resistor are connected to form the output terminal of the monitoring circuit, which is connected to the buffer circuit to output the monitoring signal.

8. The switching transistor blocking circuit as described in any one of claims 2 to 6, characterized in that, The buffer circuit includes a buffer chip, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor; The first end of the eighth resistor constitutes the blocking signal input terminal of the buffer circuit and is connected to the monitoring circuit to receive the blocking signal; The second end of the eighth resistor is connected to the enable terminal of the buffer chip; The first input terminal of the buffer chip, the second input terminal of the buffer chip, the first terminal of the ninth resistor, and the first terminal of the tenth resistor together constitute the control signal input terminal of the buffer circuit, which is connected to the control circuit to receive the control signal. The first output terminal of the buffer chip, the second output terminal of the buffer chip, the first terminal of the eleventh resistor, and the first terminal of the twelfth resistor together constitute the control signal output terminal of the buffer circuit to output the buffered control signal. The second end of the ninth resistor and the second end of the tenth resistor are connected and together form the power supply voltage input terminal of the buffer circuit, so as to connect the power supply voltage; The second terminal of the eleventh resistor and the second terminal of the twelfth resistor are both connected to the first power supply.

9. The switching transistor blocking circuit as described in claim 1, characterized in that, The control circuit includes a microprocessor; The power supply terminal of the microprocessor constitutes the power supply voltage input terminal of the control circuit and is connected to the monitoring circuit to receive the power supply voltage. The first general-purpose input / output terminal and the second general-purpose input / output terminal of the microprocessor constitute the control signal output terminal of the control circuit, which is connected to the buffer circuit to output the control signal; The third general-purpose input / output terminal of the microprocessor constitutes the enable signal output terminal of the control circuit, and is connected to the logic circuit to output an enable signal.

10. An electronic device, characterized in that, The electronic device includes a switching transistor blocking circuit as described in any one of claims 1 to 9.

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