A printed board and an electronic device using the same

Abstract

The utility model relates to printed circuit board technical field especially, relates to a kind of printed board and electronic equipment using the printed board.The electronic equipment of the utility model improves the via structure on the existing printed board, the size of the back pad is specially designed, the dielectric capacity on the printed board is better reduced, the impedance of the two signal vias of the same pair of differential signals is separately controlled respectively, the local impedance of the two vias is guaranteed, the impedance of the same pair of differential signals at via is reduced as a whole, reaches better impedance matching effect, optimizes return loss index, finally makes the signal transmission quality of electronic equipment higher.

Description

Technical Field

[0001] This utility model relates to the field of printed circuit board technology, and in particular to a printed circuit board and an electronic device using the printed circuit board. Background Technology

[0002] With the increasing application of 100G and 400G Ethernet and 25Gbps processing chips in some specialized fields, the number of 25Gbps high-speed backplanes and function boards based on the VITA architecture is growing. Currently, VITA-based backplanes and function boards primarily use RT3 connectors. Compared to RT2 connectors, while maintaining the same via arrangement and relative positions, the via size on the printed circuit board is reduced from 0.56mm to 0.37mm. This results in a locally high via impedance of 112Ω, far exceeding the nominal impedance of a 25Gbps link (92Ω), leading to poor link return loss. Therefore, designing the via structure on the printed circuit board to optimize the impedance and return loss at the connector vias is a current research direction.

[0003] Regarding the via structure design on printed circuit boards, Chinese utility model patent CN215835591U discloses a printed circuit board and electronic device, which provides a via structure on the printed circuit board for the purpose of reducing signal crosstalk. This printed circuit board has two pairs of ground vias on both sides of the grounding crimp hole between two adjacent differential signal crimp holes, and a pair of shielding vias in the middle of the same pair of differential signal crimp holes, thus achieving better signal shielding at the vias.

[0004] While the aforementioned via structures disclose some structural features that facilitate signal impedance matching, their primary design purpose is to reduce signal crosstalk, not to optimize via impedance. Therefore, they do not disclose specific via structure designs for optimizing via impedance. Furthermore, the factors affecting via impedance are different from those affecting signal crosstalk. Improperly placed vias not only fail to optimize impedance but may also introduce additional capacitor-inductor resonant points, leading to signal reflection or attenuation. Thus, the actual optimization effect of via structures in existing technologies on via impedance is limited. Utility Model Content

[0005] The purpose of this invention is to provide a printed circuit board (PCB) that solves the problem of high impedance in the via structure of existing PCBs, which is detrimental to signal transmission. Another purpose of this invention is to provide an electronic device using this PCB that solves the problem of high impedance in existing electronic devices at the PCB location, which is detrimental to signal transmission.

[0006] The printed circuit board of the present utility model includes a board body and a via structure provided on the board body. The via structure includes signal vias arranged in rows and main shielding ground vias. The signal vias are arranged in pairs, and the main shielding ground vias are located between adjacent pairs of signal vias. Impedance matching ground vias are provided between two signal vias in the same pair and between the main shielding ground via and the adjacent signal via. The impedance matching ground vias are arranged in pairs and in a columnar layout. The impedance matching ground vias surrounding each signal via form a rectangular area that surrounds the corresponding signal via. Anti-pads are provided on the printed circuit board corresponding to each signal via within the rectangular area. The size of the anti-pad satisfies: L1 = L5 - D1, and 0.9mm < L2 < L5 - (2 * W + H + 0.2mm); where L1 is the dimension in the length direction of the anti-pad, L5 is the center distance between the signal via corresponding to the anti-pad and the main shielding ground via adjacent to the signal via, D1 is the diameter of the impedance matching ground via, L2 is the dimension in the width direction of the anti-pad, W is the differential line width, and H is the differential line pitch.

[0007] Further, the impedance matching ground vias between the signal via and the adjacent main shielding ground via are located at the middle position between the two.

[0008] Further, the impedance matching ground vias between two signal vias in the same pair are located at the middle position between the two.

[0009] Further, the center distance between two impedance matching ground vias in the same pair is not greater than 0.9mm - D1 and not less than D1 + 0.2mm.

[0010] Further, the anti-pad is rectangular or oval.

[0011] The printed circuit board of the present utility model improves the via structure on the existing printed circuit board. Through a unique design of the size of the anti-pad, the dielectric capacitance on the printed circuit board is better reduced. By separately controlling the impedance at two signal vias of the same pair of differential signals, the local impedance at the two vias is ensured, and the impedance of the same pair of differential signals at the via is reduced as a whole, achieving a better impedance matching effect and optimizing the return loss index.

[0012] The electronic device of the present utility model includes a printed circuit board and a high-speed connector connected to the printed circuit board. The printed circuit board includes a board body and a via structure provided on the board body. The via structure includes signal vias arranged in rows and a main shielding ground via. The signal vias are arranged in pairs, and the main shielding ground via is located between two adjacent pairs of signal vias. Impedance matching ground vias are provided between two signal vias in the same pair and between the main shielding ground via and the adjacent signal via. The impedance matching ground vias are arranged in pairs and in a columnar layout. The impedance matching ground vias surrounding each signal via form a rectangular area surrounding the corresponding signal via. Anti-pads are provided on the printed circuit board corresponding to each signal via within the rectangular area, and the size of the anti-pad satisfies: L1 = L5 - D1, and 0.9mm < L2 < L5 - (2*W + H + 0.2mm); where L1 is the dimension in the length direction of the anti-pad, L5 is the center-to-center distance between the signal via corresponding to the anti-pad and the main shielding ground via adjacent to the signal via, D1 is the diameter of the impedance matching ground via, L2 is the dimension in the width direction of the anti-pad, W is the differential line width, and H is the differential line pitch.

[0013] Further, the impedance matching ground vias between the signal via and the adjacent main shielding ground via are located at the middle position between the two.

[0014] Further, the impedance matching ground vias between two signal vias in a pair are located at the middle position between the two.

[0015] Further, the center-to-center distance between two impedance matching ground vias in a pair is not greater than 0.9mm - D1 and not less than D1 + 0.2mm.

[0016] Further, the anti-pad is rectangular or oval.

[0017] The electronic device of the present utility model improves the via structure on the existing printed circuit board. Through a unique design of the size of the anti-pad, the dielectric capacitance on the printed circuit board is better reduced. By separately controlling the impedance at two signal vias of the same pair of differential signals, the local impedance at the two vias is ensured, and the impedance of the same pair of differential signals at the via is reduced as a whole, achieving a better impedance matching effect and optimizing the return loss index. Finally, the signal transmission quality of the electronic device is higher. Moreover, the via insertion loss can also be reduced and the crosstalk can be optimized. Description of the Drawings

[0018] Figure 1 It is a schematic structural diagram showing the area where a certain pair of signal vias and an adjacent main shielding ground via are located in an embodiment of the printed circuit board of the present utility model;

[0019] Figure 2 It is the impedance experimental data of the printed circuit board of the present utility model;

[0020] Figure 3The return loss test data for the printed circuit board of this utility model;

[0021] Figure 4 This is the crosstalk experimental data for the printed circuit board of this utility model;

[0022] Figure 5 This is the insertion loss test data for the printed circuit board of this utility model;

[0023] Figure 6 for Figure 1 The diagram shows a via encapsulation of the area shown.

[0024] In the diagram: 1. Signal via; 2. Main shielding ground via; 3. Impedance matching ground via; 4. Anti-solder pad; 5. Outgoing line; 50. Widened section. Detailed Implementation

[0025] The features and performance of this utility model will be further described in detail below with reference to the embodiments.

[0026] This invention mainly relates to high-speed communication electronic devices such as high-speed backplanes and function boards. These electronic devices often include printed circuit boards (PCBs) and high-speed differential connectors connected to the PCBs. The PCBs have signal vias for the differential signal pins of the high-speed differential connectors to insert and connection, and main shielding ground holes for the ground pins to insert and connection. This invention improves upon the PCBs of existing electronic devices, and is particularly suitable for electronic devices containing RT3 connectors. The spacing between the paired differential signals of this high-speed connector is 1.8mm, and the via diameter on the PCB is 0.37mm. By optimizing the via structure, and by optimizing the relative positions and dimensions of the signal vias, anti-solder pads, main shielding ground holes, and impedance matching ground holes, good shielding of the signal loop is achieved while optimizing the impedance at the via locations, reducing return loss, and improving the transmission quality of high-speed signals throughout the entire signal transmission loop.

[0027] Specifically, the following provides various embodiments of this utility model for illustration.

[0028] In a basic embodiment of a printed circuit board, the printed circuit board includes a board body, on which a via structure is provided, combined with... Figure 1, the via structure includes signal vias 1 arranged in rows and main shielding ground vias 2. Depending on the different high-speed connectors connected on the printed circuit board, the signal vias 1 and the main shielding ground vias 2 may be single-row or multi-row. Each row of signal vias 1 is arranged in pairs, and the main shielding ground vias 2 are arranged between two adjacent pairs of signal vias 1 in each row. Moreover, impedance matching ground vias 3 are provided between two signal vias 1 in the same pair, and between the main shielding ground via 2 and the adjacent signal via 1. The impedance matching ground vias 3 at these positions are arranged in pairs, and the two impedance matching vias in the same pair are arranged in the column direction, that is, arranged in the direction perpendicular to the same row of signal vias 1. Thus, on both sides of each signal via 1 in the row direction, there is a pair of impedance matching ground vias 3, and the two pairs of impedance matching ground vias 3 enclose a rectangular area that encloses the corresponding signal via 1. On the printed circuit board, anti-pads 4 are provided in the formed rectangular area corresponding to each signal via 1. Of course, it should be noted that Figure 1 only shows the structure of the area where a pair of signal vias 1 and an adjacent main shielding ground via 2 on the printed circuit board of the present invention are located. It should be known that the structures of the areas where other pairs of signal vias 1 and an adjacent main shielding ground via 2 on the printed circuit board are the same as this.

[0029] The difference between the impedance matching ground via ۳ and the main shielding ground via ۲ is that the main shielding ground via ۲ is used for the grounding pin on the high-speed connector to insert and connect, while the impedance matching ground via ۳ is an "idle hole" opened on the printed circuit board, that is, no pin of the high-speed connector is inserted into it. Although there are such differences between the two, because they are both grounded and the potential points are equal, they can both play a role in shielding the signal loop at the signal via ۱ and reducing crosstalk.

[0030] The main improvement means of the present invention is that the size of the anti-pad 4 satisfies: L1 = L5 - D1, and 0.9mm < L2 < L5 - (2 * W + H + 0.2mm); where L1 is the dimension of the anti-pad 4 in the length direction, L5 is the center distance between the signal via 1 corresponding to the anti-pad 4 and the main shielding ground via 2 adjacent to this signal via 1, D1 is the diameter of the impedance matching ground via 3, L2 is the dimension of the anti-pad 4 in the width direction, W is the differential line width, and H is the differential line pitch. It should be noted that the differential line width and the differential line pitch are determined as specific values or range values according to the characteristic impedance and the printed circuit board stack-up. The anti-pad 4 with such a size can change the dielectric capacitance at the signal via ۱ and reduce the via impedance.

[0031] In addition, since the setting of the impedance matching ground via 3 can also change the equivalent capacitance of the signal via 1, in a preferred embodiment based on the above embodiment, the impedance matching ground via 3 between the signal via 1 and the adjacent main shielding ground via 2 is at the middle position between the two, which can reduce the equivalent capacitance, is beneficial to impedance matching, and improves the working frequency.

[0032] Based on the same considerations, in a preferred embodiment, the impedance matching ground hole 3 between the two paired signal vias 1 is located in the middle of the two, which can improve the shielding performance of the vias 1, reduce common-mode noise, and optimize crosstalk.

[0033] Based on the above embodiments, in an optimized embodiment, the center-to-center distance between the paired impedance matching ground holes 3 is not greater than 0.9mm-D1 and not less than D1+0.2mm, so as to balance the dielectric capacitance around the signal via 1 by setting the relative position of the impedance matching ground holes 3.

[0034] The above embodiment, through the design of the dimensions of the anti-pad 4 and the position and spacing of the impedance matching ground via 3, balances the shielding of the signal and the control of the dielectric capacitance at the signal via 1, thus optimizing the via impedance while ensuring signal shielding effectiveness. Combined with... Figure 2-3 The simulation data shown indicates that the via structure of the printed circuit board of this invention optimizes the impedance of signal via 1 to 87-98Ω, which is very close to the nominal impedance value of a 25Gbps link. Moreover, the return loss index at 12.5GHz is optimized from 13.7dB to 25dB. Compared with the 25Gbps link return loss index, the return loss index has a large margin (the index requirement is 10dB), which better meets the usage requirements.

[0035] Of course, since the size design of the antipad 4 and the position and spacing design of the impedance matching ground via 3 will affect the dielectric capacitance, the position of the impedance matching ground via 3 between the signal via 1 and its adjacent main shielding ground via 2 can also be appropriately adjusted when the size design and shape of the antipad 4 change. Furthermore, as... Figure 1 In the embodiment shown, the anti-pad 4 is rectangular in shape. In other embodiments, it can also be elliptical. The major axis and minor axis of the elliptical anti-pad 4 satisfy the dimensions in the length direction and width direction of the anti-pad 4 when it is rectangular, as described above.

[0036] Figure 6 The diagram shows the output line 5 connected to the signal via 1 in the printed circuit board. The output lines 5 of the two paired signal vias extend out of anti-pads at an angle toward each other and are led out in a straight line along the interval between the two signal vias. The inclined section of the output line 5 avoids the impedance matching ground hole 3 between the two anti-pads, and the part in the anti-pad area has a widened section 50 to achieve better impedance control.

[0037] The printed circuit board of this invention adopts the above-mentioned via structure, which can also reduce via insertion loss and optimize crosstalk, such as Figure 4-5 As shown.

[0038] An embodiment of the electronic device of this utility model includes a printed circuit board and a high-speed connector mounted on the printed circuit board. The structure of the printed circuit board is the same as that of the embodiment described above, and will not be described again here.

[0039] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. The patent protection scope of the present utility model shall be determined by the claims. Similarly, any equivalent structural changes made based on the description and drawings of the present utility model shall also be included within the protection scope of the present utility model.

Claims

1. A printed circuit board, comprising a board body and a via structure disposed on the board body, the via structure comprising a row of signal vias (1) and a main shielding ground via (2), the signal vias (1) being arranged in pairs, the main shielding ground via (2) being located between two adjacent pairs of signal vias (1), impedance matching ground vias (3) being provided between the two signal vias (1) in the same pair and between the main shielding ground via (2) and the adjacent signal via (1), the impedance matching ground vias (3) being arranged in pairs and in the column direction, the impedance matching ground vias (3) surrounding each signal via (1) forming a rectangular area surrounding the corresponding signal via (1), and anti-pads (4) being provided on the printed circuit board corresponding to each signal via (1) within the rectangular area, characterized in that, The size of the anti-pad (4) satisfies: L1 = L5 - D1, and 0.9mm < L2 < L5 - (2*W + H + 0.2mm); where L1 is the size of the anti-pad (4) in the length direction, L5 is the center-to-center distance between the signal via (1) corresponding to the anti-pad (4) and the main shielding ground via (2) adjacent to the signal via (1), D1 is the diameter of the impedance-matching ground via (3), L2 is the size of the anti-pad (4) in the width direction, W is the differential line width, and H is the differential line pitch.

2. The printed circuit board according to claim 1, characterized in that, The impedance-matching ground via (3) between the signal via (1) and the main shielding ground via (2) adjacent to it is located at the middle position between the two.

3. The printed circuit board according to claim 1, characterized in that, The impedance-matching ground via (3) between two paired signal vias (1) is located at the middle position between the two.

4. The printed circuit board according to any one of claims 1-3, characterized in that, The center-to-center distance between paired impedance-matching ground vias (3) is not greater than 0.9mm - D1 and not less than D1 + 0.2mm.

5. The printed circuit board according to any one of claims 1-3, characterized in that, The anti-pad (4) is rectangular or oval.

6. An electronic device, including a printed circuit board and a high-speed connector connected to the printed circuit board, the printed circuit board including a board body and a via structure disposed on the board body, the via structure including a row of signal vias (1) and a main shielding ground via (2), the signal vias (1) being arranged in pairs, the main shielding ground via (2) being located between two adjacent pairs of signal vias (1), impedance matching ground vias (3) being provided between the two signal vias (1) in the same pair and between the main shielding ground via (2) and the adjacent signal via (1), the impedance matching ground vias (3) being arranged in pairs and in the column direction, the impedance matching ground vias (3) surrounding each signal via (1) forming a rectangular area surrounding the corresponding signal via (1), and anti-pads (4) being provided on the printed circuit board corresponding to each signal via (1) within the rectangular area, characterized in that, The size of the anti-pad (4) satisfies: L1 = L5 - D1, and 0.9mm < L2 < L5 - (2*W + H + 0.2mm); where L1 is the size of the anti-pad (4) in the length direction, L5 is the center-to-center distance between the signal via (1) corresponding to the anti-pad (4) and the main shielding ground via (2) adjacent to the signal via (1), D1 is the diameter of the impedance-matching ground via (3), L2 is the size of the anti-pad (4) in the width direction, W is the differential line width, and H is the differential line pitch.

7. The electronic device according to claim 6, characterized in that, The impedance-matching ground via (3) between the signal via (1) and the main shielding ground via (2) adjacent to it is located at the middle position between the two.

8. The electronic device according to claim 6, characterized in that, The impedance-matching ground via (3) between two paired signal vias (1) is located at the middle position between the two.

9. The electronic device according to any one of claims 6-8, characterized in that, The center-to-center distance between paired impedance-matching ground vias (3) is not greater than 0.9mm - D1 and not less than D1 + 0.2mm.

10. The electronic device according to any one of claims 6-8, characterized in that, The anti-pad (4) is rectangular or oval.

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