A double-sided circuit board
By introducing stress-barrier meshes and filling them with low-modulus conductive materials in a ceramic substrate double-sided circuit board, the problems of warping and delamination are solved, and a double-sided circuit board design with small thermal deformation and high reliability is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- JIANGXI DING WAA SAM TAI TECH CO LTD
- Filing Date
- 2025-08-18
- Publication Date
- 2026-07-14
AI Technical Summary
During the manufacturing process, double-sided circuit boards with ceramic substrates are prone to warping due to excessive stress caused by the difference in thermal expansion coefficients. Furthermore, the circuit layer and the ceramic substrate are prone to delamination, which affects product reliability and performance.
A stress barrier mesh is introduced between the circuit layer and the ceramic substrate. The mesh is filled with a conductive material with a low elastic modulus. The circuit layer is bonded to the substrate through a bonding layer. Conductive material is placed in the mesh trenches to absorb thermal stress and release the stress of the circuit layer.
It effectively reduces thermal deformation of the circuit board, prevents warping, and reduces the risk of delamination between the circuit layer and the ceramic substrate, thereby improving the reliability and performance of the product.
Smart Images
Figure CN224503619U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to printed circuit boards, and more particularly to a double-sided circuit board. Background Technology
[0002] Double-sided circuit boards with ceramic substrates are high-performance circuit boards widely used in electronic manufacturing. Their main feature is that they use ceramic materials as substrates and have conductive lines designed on both sides.
[0003] Ceramic-based double-sided circuit boards (CPCBs) are widely used in high-power electronic devices due to their excellent thermal conductivity, insulation, and mechanical strength. However, during manufacturing, CPCBs are prone to warping due to excessive stress caused by differences in thermal expansion coefficients. Furthermore, delamination can easily occur between the circuit layers and the ceramic substrate, affecting product reliability and performance. Traditional processes mitigate these problems by adjusting materials or optimizing soldering parameters, but with limited effectiveness. Summary of the Invention
[0004] The technical problem to be solved by this utility model is to provide a double-sided circuit board with less thermal deformation.
[0005] The technical problem to be solved by this utility model is to provide a double-sided circuit board that is not easily delaminated between the circuit layer and the ceramic substrate.
[0006] To solve the above-mentioned technical problems, the present invention adopts a double-sided circuit board, comprising a ceramic substrate and two circuit layers made of copper foil, the circuit layers comprising conductive lines; the two circuit layers are respectively bonded to the top and bottom surfaces of the ceramic substrate through bonding layers, the bonding surfaces of the circuit layers comprising stress barrier grids formed by trenches.
[0007] The double-sided circuit board described above has stress-barrier mesh grooves filled with a conductive material with a low elastic modulus, wherein the low elastic modulus is less than half the elastic modulus of the copper foil material.
[0008] The double-sided circuit board described above includes a bonding layer comprising a solder layer, an adhesive layer, or an interface modification layer. The interface modification layer includes a metallization layer, an active metal layer, a nano-coating, a chemical plating layer, a diffusion bonding layer, an oxide bonding layer, a laser-assisted bonding layer, or an ion exchange bonding layer.
[0009] The depth of the trenches in the double-sided circuit board described above is one-quarter to one-half the thickness of the copper foil; the lateral width of the trenches is 0.05-0.1mm.
[0010] The stress barrier grid in the double-sided circuit board described above is an orthogonal grid, a hexagonal grid, or a triangular grid.
[0011] The double-sided circuit board described above has a total area of 3%-5% of the total area of the circuit layer stress barrier mesh trenches. The stress barrier mesh includes multiple mesh units arranged in an array, and the area of each mesh unit is 0.1%-3% of the total area of the circuit layer.
[0012] The double-sided circuit board described above has a low elastic modulus of less than 50 GPa.
[0013] In the double-sided circuit board described above, the distance between the edge of the stress barrier mesh and the edge of the conductive line is greater than 0.5 mm.
[0014] The double-sided circuit board described above has a beveled edge on the side of the conductive line edge near the ceramic substrate.
[0015] The double-sided circuit board described above has a bevel height of 0.01-0.1mm and a bevel width of 0.01-0.1m.
[0016] The grooves in the stress-barrier grid of this invention can release the stress in the copper foil of the circuit layer, so that the double-sided circuit board will not warp due to excessive thermal stress of the copper foil of the circuit layer. Attached Figure Description
[0017] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0018] Figure 1 This is a top view of the double-sided circuit board according to an embodiment of this utility model.
[0019] Figure 2 Figure 1 AA section view in the image.
[0020] Figure 3 yes Figure 2 BB section view in the middle.
[0021] Figure 4 yes Figure 2 A magnified view of part I in the middle section.
[0022] Figure 5 yes Figure 3 A magnified view of part II in the middle section. Detailed Implementation
[0023] The structure of the double-sided circuit board in this embodiment of the utility model is as follows: Figures 1 to 5As shown, the system includes a ceramic substrate 10 and two circuit layers 20 made of copper foil, each circuit layer 20 including conductive lines 20A. The two circuit layers 20 are bonded to the top and bottom surfaces of the ceramic substrate 10 via bonding layers 30, respectively. The bonding surfaces of the circuit layers 20 include stress-barrier meshes 21 formed by trenches 21A. The stress-barrier meshes 21 trenches 21A are filled with a conductive material 22 with a low elastic modulus, the low elastic modulus being less than half the elastic modulus of the copper foil material. If the area of the copper foil bonding surfaces of the circuit layers 20 is sufficiently thermally and electrically conductive, the stress-barrier meshes 21 trenches 21A may not need to be filled with conductive material.
[0024] The bonding layer can be a welding layer, an adhesive layer, or an interface modification layer. The interface modification layer can be a metallization layer, an active metal layer, a nano-coating, a chemical plating layer, a diffusion bonding layer, an oxide bonding layer, a laser-assisted bonding layer, or an ion exchange bonding layer.
[0025] The elastic modulus of copper foil on a PCB (Printed Circuit Board) is typically 100 GPa - 120 GPa. In this embodiment, the low-elastic-modulus conductive material 22 filling the trench 21A can be conductive adhesive or soft solder. The substrate of the conductive adhesive can be silicone resin. The elastic modulus of conductive adhesive filled with conductive particles is generally 1 GPa - 10 GPa. The elastic modulus of soft solder Sn63Pb37 (eutectic solder) is 30 - 50 GPa, SAC305 (Sn96.5Ag3.0Cu0.5) is 40 - 55 GPa, and pure tin (Sn) is 40 - 50 GPa. In this embodiment, the low-elastic-modulus conductive material 22 is selected with an elastic modulus less than 50 GPa.
[0026] The depth h1 of trench 21A is one-quarter to one-half of the copper foil thickness H. The lateral width b1 of trench 21A is 0.05-0.1 mm.
[0027] The stress barrier grid 21 can be an orthogonal grid, a hexagonal grid, or a triangular grid. The stress barrier grid 21 comprises multiple grid cells arranged in an array. The grid cells of the orthogonal grid are rectangular, the grid cells of the hexagonal grid are regular hexagons, and the grid cells of the triangular grid are equilateral triangles. The area of each grid cell is 0.1%-3% of the total area of the line layer 20. The smaller the area of the grid cell, the more grid cells are on the line layer 20.
[0028] The total area of the stress barrier mesh 21 trench 21A on the line layer 20 is 3%-5% of the total area of the line layer 20.
[0029] The stress barrier mesh 21 groove 21A should not be connected to the edge of the conductive line 20A on the vertical surface 23, and the distance s between the edge of the stress barrier mesh 21 and the edge of the conductive line 20A should be greater than 0.5mm.
[0030] In the double-sided circuit board of the above embodiments of this utility model, the bonding surface of the circuit layer 20 is etched to form a stress barrier mesh 21 composed of trenches 21A. The trenches 21A of the stress barrier mesh 21 are filled with a conductive material 22 with a low elastic modulus. The conductive material 22 with a low elastic modulus in the trenches 21A can undergo elastic deformation when thermally expanded, thereby absorbing the thermal stress between the copper foil and the ceramic substrate and releasing part of the stress in the copper foil of the circuit layer 20. This prevents the double-sided circuit board from warping due to excessive thermal stress on the copper foil of the circuit layer 20 during subsequent production and operation.
[0031] The edge of the conductive line 20A has a beveled foot 24 at one end near the ceramic substrate 10. The height h2 of the beveled foot 24 is 0.01-0.1 mm, and the lateral width b2 of the beveled foot 24 is 0.01-0.1 m.
[0032] The bevel foot 24 provided at one end of the edge facade 23 of the conductive line 20A near the ceramic substrate 10 forms a buffer layer at the edge where the line layer 20 and the ceramic substrate 10 are joined. This is equivalent to forming a buffer barrier on the side of the line layer 20, which disperses the stress between the line layer 20 and the ceramic substrate 10 through the geometric transition of the bevel foot, reduces the local stress gradient, and reduces the risk of delamination between the line layer 20 and the ceramic substrate 10.
Claims
1. A double-sided circuit board, comprising a ceramic substrate and two circuit layers made of copper foil, the circuit layers including conductive lines; the two circuit layers are respectively bonded to the top and bottom surfaces of the ceramic substrate via bonding layers, characterized in that, The bonding surface of the circuit layer includes a stress-barrier mesh formed by trenches.
2. The double-sided circuit board according to claim 1, characterized in that, The stress-barrier mesh trenches are filled with a conductive material with a low elastic modulus, which is less than half the elastic modulus of the copper foil material.
3. The double-sided circuit board according to claim 1, characterized in that, The bonding layer includes a welding layer, an adhesive layer, or an interface modification layer. The interface modification layer includes a metallization layer, an active metal layer, a nano-coating, a chemical plating layer, a diffusion bonding layer, an oxide bonding layer, a laser-assisted bonding layer, or an ion exchange bonding layer.
4. The double-sided circuit board according to claim 1, characterized in that, The depth of the trench is one-quarter to one-half the thickness of the copper foil; the lateral width of the trench is 0.05-0.1 mm.
5. The double-sided circuit board according to claim 1, characterized in that, The stress-barrier mesh is an orthogonal mesh, a hexagonal mesh, or a triangular mesh.
6. The double-sided circuit board according to claim 1, characterized in that, The total area of the stress barrier mesh trench in the line layer is 3%-5% of the total area of the line layer. The stress barrier mesh consists of multiple mesh cells arranged in an array, and the area of each mesh cell is 0.1%-3% of the total area of the line layer.
7. The double-sided circuit board according to claim 2, characterized in that, The low elastic modulus is less than 50 GPa.
8. The double-sided circuit board according to claim 1, characterized in that, The distance between the edge of the stress-barrier mesh and the edge of the conductive line is greater than 0.5 mm.
9. The double-sided circuit board according to claim 1, characterized in that, The facade of the conductive line edge includes a bevel at the end closest to the ceramic substrate.
10. The double-sided circuit board according to claim 9, characterized in that, The height of the slope toe is 0.01-0.1mm, and the lateral width of the slope toe is 0.01-0.1m.