Solar cell
By setting a microcrystalline amorphous silicon layer with a crystallinity of 1% to 5% as a transition layer in the solar cell, the problem of increased series resistance in traditional solar cells is solved, the fill factor and photoelectric conversion efficiency are improved, and the passivation performance is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TONGWEI SOLAR ENERGY (CHENGDU) CO LID
- Filing Date
- 2025-06-12
- Publication Date
- 2026-07-14
AI Technical Summary
The increased series resistance caused by the doping of microcrystalline silicon transition layers in traditional heterojunction solar cells reduces the fill factor of the solar cells.
An amorphous silicon layer containing microcrystals with a crystallinity of 1% to 5% is set as a transition layer between the first microcrystalline silicon layer and the first intrinsic amorphous silicon layer to replace the traditional P0 layer. Its thickness is controlled between 1.3 nm and 2.5 nm to enhance the contact effect with the microcrystalline silicon layer and reduce the series resistance of the battery.
By optimizing the crystallinity and thickness of the transition layer, the fill factor and photoelectric conversion efficiency of the solar cell were improved, the series resistance of the cell was reduced, and the passivation performance was improved.
Smart Images
Figure CN224503855U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of photovoltaic technology, and in particular to a solar cell. Background Technology
[0002] In traditional heterojunction solar cells, an intrinsic amorphous silicon layer is typically deposited on the back side as a passivation layer, followed by a doped microcrystalline silicon layer. In conventional techniques, a transition layer (hereinafter referred to as the P0 layer) is formed on the side where the doped microcrystalline silicon layer meets the intrinsic amorphous silicon layer. This transition layer involves the phase transformation from amorphous to microcrystalline. Typically, the transition layer has a high oxygen content, which significantly increases the series resistance of the solar cell and reduces its fill factor. Utility Model Content
[0003] Therefore, it is necessary to provide a solar cell that solves the problem of increased series resistance caused by the doped microcrystalline silicon transition layer.
[0004] A solar cell includes a monocrystalline silicon wafer of a first doping type and a first intrinsic amorphous silicon layer and a first microcrystalline silicon layer of a second doping type stacked on the monocrystalline silicon wafer;
[0005] The first intrinsic amorphous silicon layer includes a first sublayer and a second sublayer, with the first sublayer located between the second sublayer and the first microcrystalline silicon layer; the second sublayer contains microcrystals, the crystallinity of the second sublayer is 1% to 5%, and the thickness of the second sublayer is 1.3 nm to 2.5 nm.
[0006] In some embodiments, the first intrinsic amorphous silicon layer further includes a third sublayer and / or a fourth sublayer located between the monocrystalline silicon wafer and the first sublayer;
[0007] The third sublayer is an oxygen-containing amorphous silicon layer with a crystallinity of less than 1%, and the fourth sublayer is an oxygen-free amorphous silicon layer with a crystallinity less than that of the first sublayer.
[0008] When the first intrinsic amorphous silicon layer further includes the third sub-layer and the fourth sub-layer, the third sub-layer is located between the monocrystalline silicon wafer and the fourth sub-layer.
[0009] In some embodiments, the thickness of the first sublayer is 2nm to 6nm.
[0010] In some embodiments, the thickness of the third sublayer is 1 nm to 3 nm.
[0011] In some embodiments, the thickness of the fourth sublayer is 0.5 nm to 2 nm.
[0012] In some embodiments, the solar cell further includes a second intrinsic amorphous silicon layer and a second microcrystalline silicon layer of a first doping type, wherein the second intrinsic amorphous silicon layer is located on the side of the monocrystalline silicon wafer away from the first intrinsic amorphous silicon layer, and the second microcrystalline silicon layer is located on the side of the second intrinsic amorphous silicon layer away from the monocrystalline silicon wafer.
[0013] In some embodiments, the crystallinity of the first microcrystalline silicon layer is 40% to 60%.
[0014] In some embodiments, the crystallinity of the second microcrystalline silicon layer is 20% to 40%.
[0015] In some embodiments, the solar cell further includes a transition layer located between the second intrinsic amorphous silicon layer and the second microcrystalline silicon layer, wherein the transition layer is an oxygen-containing microcrystalline silicon layer.
[0016] In some embodiments, the second intrinsic amorphous silicon layer includes a fifth sublayer and a sixth sublayer, the fifth sublayer being located between the sixth sublayer and the second microcrystalline silicon layer, the crystallinity of the sixth sublayer being less than 1%, and the crystallinity of the sixth sublayer being greater than that of the fifth sublayer.
[0017] In some embodiments, the second intrinsic amorphous silicon layer further includes a seventh sublayer and / or an eighth sublayer located between the monocrystalline silicon wafer and the fifth sublayer; wherein the seventh sublayer is an oxygen-containing amorphous silicon layer with a crystallinity of less than 1%, and the eighth sublayer is an oxygen-free amorphous silicon layer with a crystallinity less than that of the fifth sublayer.
[0018] When the second intrinsic amorphous silicon layer includes the seventh sublayer and the eighth sublayer, the seventh sublayer is located between the monocrystalline silicon wafer and the eighth sublayer.
[0019] In some embodiments, the thickness of the fifth sublayer is 2nm to 6nm.
[0020] In some embodiments, the thickness of the sixth sublayer is 0.5 nm to 1.5 nm.
[0021] In some embodiments, the thickness of the seventh sublayer is 1 nm to 3 nm.
[0022] In some embodiments, the thickness of the eighth sublayer is 2nm to 4nm.
[0023] In some embodiments, the solar cell further includes a first transparent conductive layer disposed on the side of the first microcrystalline silicon layer away from the first intrinsic amorphous silicon layer.
[0024] In some embodiments, the solar cell further includes a second transparent conductive layer disposed on the side of the second microcrystalline silicon layer away from the second intrinsic amorphous silicon layer.
[0025] Compared with traditional technologies, the above-mentioned solar cells have the following advantages:
[0026] The aforementioned solar cell replaces the traditional PO layer with a second sublayer between the first sublayer and the first microcrystalline silicon layer. This second sublayer is an amorphous silicon layer containing microcrystals, and its crystallinity is controlled between 1% and 5%. This enhances the contact with the first microcrystalline silicon layer, reduces the cell's series resistance, and improves performance parameters such as the fill factor. If the crystallinity of the second sublayer is below this range, it cannot effectively enhance the contact with the first microcrystalline silicon layer and will affect the crystallization of the first microcrystalline silicon layer, leading to a decrease in the overall crystallinity of the first microcrystalline silicon layer. Conversely, if the crystallinity of the second sublayer is above this range, a high hydrogen dilution ratio, high power, and high pressure are required to achieve a high crystallinity. However, this cannot effectively improve cell performance because a high hydrogen dilution ratio will etch the first sublayer, affecting the cell's open-circuit voltage; high power will bombard the first sublayer significantly, affecting the open-circuit voltage; and high pressure will lead to poor film uniformity, affecting various electrical properties of the cell. Therefore, an excessively high crystallinity of the second sublayer 122 is also detrimental to improving cell performance. The second sublayer needs to reach a certain thickness, specifically controlled between 1.3nm and 2.5nm, to improve the minority carrier lifetime of the silicon wafer, significantly improve the passivation performance of the battery, enhance photoelectric conversion efficiency, and compensate for the negative impact of removing the traditional P0 layer. However, it cannot be too thick, as excessive thickness will lead to excessively high film series resistance, thus affecting the battery's fill factor. If the thickness of the second sublayer is less than the above range, it cannot effectively enhance the contact effect with the first microcrystalline silicon layer, and will generate a large amount of recombination at the interface with the first microcrystalline silicon layer, affecting carrier transport and thus reducing the battery's open-circuit voltage. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of the structure of a solar cell according to one embodiment.
[0028] Explanation of reference numerals in the attached figures:
[0029] 100. Solar cell; 110. Monocrystalline silicon wafer; 120. First intrinsic amorphous silicon layer; 121. First sublayer; 122. Second sublayer; 123. Third sublayer; 124. Fourth sublayer; 130. First microcrystalline silicon layer; 140. Second intrinsic amorphous silicon layer; 141. Fifth sublayer; 142. Sixth sublayer; 143. Seventh sublayer; 144. Eighth sublayer; 150. Second microcrystalline silicon layer; 160. Transition layer; 170. First transparent conductive layer; 180. Second transparent conductive layer; 190. First electrode; 200. Second electrode. Detailed Implementation
[0030] To make the above-mentioned objects, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a full understanding of this utility model. However, this utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this utility model. Therefore, this utility model is not limited to the specific embodiments disclosed below.
[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0032] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.
[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0034] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.
[0035] like Figure 1 As shown, a solar cell 100 according to an embodiment of the present invention includes a first doped monocrystalline silicon wafer 110, a first intrinsic amorphous silicon layer 120, and a second doped first microcrystalline silicon layer 130.
[0036] A first intrinsic amorphous silicon layer 120 and a first microcrystalline silicon layer 130 are stacked on a monocrystalline silicon wafer 110, with the first intrinsic amorphous silicon layer 120 located between the monocrystalline silicon wafer 110 and the first microcrystalline silicon layer 130.
[0037] The first intrinsic amorphous silicon layer 120 includes a first sublayer 121 and a second sublayer 122. The first sublayer 121 is located between the second sublayer 122 and the first microcrystalline silicon layer 130.
[0038] The second sublayer 122 is an amorphous silicon layer containing microcrystals. The crystallinity of the second sublayer 122 is 1% to 5%, specifically, for example, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, etc. The thickness of the second sublayer 122 is 1.3nm to 2.5nm, specifically, for example, 1.3nm, 1.5nm, 1.7nm, 1.9nm, 2.1nm, 2.3nm, 2.5nm, etc.
[0039] The aforementioned solar cell 100 replaces the traditional PO layer by providing a second sublayer 122 between the first sublayer 121 and the first microcrystalline silicon layer 130. The second sublayer 122 is an amorphous silicon layer containing microcrystals, and its crystallinity is controlled within 1% to 5%. This enhances the contact effect with the first microcrystalline silicon layer 130, reduces the series resistance of the cell, and improves the fill factor. If the crystallinity of the second sublayer 122 is lower than the above range, it cannot effectively enhance the contact effect with the first microcrystalline silicon layer 130 and will affect the crystallization of the first microcrystalline silicon layer 130, resulting in a decrease in the overall crystallinity of the first microcrystalline silicon layer 130. If the crystallinity of the second sublayer 122 exceeds the aforementioned range, a high hydrogen dilution ratio, high power, and high pressure are required to achieve a high crystallinity. However, this cannot effectively improve battery performance because a high hydrogen dilution ratio will cause etching of the first sublayer 121, affecting the battery's open-circuit voltage; high power will bombard the first sublayer 121 significantly, affecting the open-circuit voltage; and high pressure will lead to poor film uniformity, affecting various electrical properties of the battery. Therefore, an excessively high crystallinity of the second sublayer 122 is also detrimental to improving battery performance.
[0040] Research has found that the second sublayer 122 needs to reach a certain thickness, specifically controlled between 1.3nm and 2.5nm, to improve the minority carrier lifetime of the silicon wafer, significantly improve the passivation performance of the battery, enhance photoelectric conversion efficiency, and compensate for the negative impact of removing the traditional PO layer. However, it cannot be too thick, as excessive thickness will lead to excessively high film series resistance, thereby affecting the battery's fill factor and other performance parameters. If the thickness of the second sublayer 122 is less than the above range, it cannot effectively enhance the contact effect with the first microcrystalline silicon layer 130, and will generate a large amount of recombination at the interface with the first microcrystalline silicon layer 130, affecting carrier transport and thus reducing the battery's open-circuit voltage.
[0041] The first sublayer 121 serves as the main passivation layer, playing a primary passivation role. The crystallinity of the first sublayer 121 is lower than that of the second sublayer 122. For example, the crystallinity of the first sublayer 121 is less than 1%, specifically 0%, 0.1%, 0.3%, 0.5%, 0.7%, 0.9%, etc. The thickness of the first sublayer 121 can be set relatively large. In some examples, the thickness of the first sublayer 121 is 2nm~6nm, specifically 2nm, 3nm, 4nm, 5nm, 6nm, etc.
[0042] like Figure 1 As shown, in some examples, the first intrinsic amorphous silicon layer 120 further includes a third sublayer 123 and / or a fourth sublayer 124 located between the monocrystalline silicon wafer 110 and the first sublayer 121. The third sublayer 123 is an oxygen-containing amorphous silicon layer. The crystallinity of the third sublayer 123 is less than that of the first sublayer 121. The crystallinity of the third sublayer 123 is less than 1%, and further, the crystallinity of the third sublayer 123 is not greater than 0.6%, specifically, for example, 0, 0.2%, 0.4%, 0.6%, etc. The fourth sublayer 124 is an oxygen-free amorphous silicon layer. The crystallinity of the fourth sublayer 124 is less than that of the first sublayer 121. The crystallinity of the fourth sublayer 124 is less than 1%, and further, the crystallinity of the fourth sublayer 124 is not greater than 0.6%, specifically, for example, 0, 0.2%, 0.4%, 0.6%, etc.
[0043] Depositing the third sublayer 123 before depositing the first sublayer 121 can prevent the epitaxy of the monocrystalline silicon wafer 110.
[0044] The thickness of the third sublayer 123 should not be too high. The thickness of the third sublayer 123 should be less than 3nm, such as 1nm~3nm, specifically 1nm, 1.5nm, 2nm, 2.5nm, 3nm, etc. If the thickness is too high, it will not play a significant role, but will instead increase the series resistance.
[0045] In some examples, the thickness of the third sublayer 123 is less than the thickness of the first sublayer 121.
[0046] Depositing the fourth sublayer 124 before depositing the first sublayer 121 can prevent the formation of yellow powder and avoid excessive yellow powder affecting the passivation performance of the silicon wafer.
[0047] In some examples, the thickness of the fourth sublayer 124 is 2nm to 4nm, specifically 2nm, 2.5nm, 3nm, 3.5nm, 4nm, etc.
[0048] In some examples, the thickness of the fourth sublayer 124 is less than the thickness of the first sublayer 121.
[0049] When the first intrinsic amorphous silicon layer 120 includes a third sublayer 123 and a fourth sublayer 124, the third sublayer 123 is located between the monocrystalline silicon wafer 110 and the fourth sublayer 124.
[0050] The doping type of the first microcrystalline silicon layer 130 is opposite to that of the monocrystalline silicon wafer 110. For example, in some examples, the monocrystalline silicon wafer 110 is N-type doped, such as phosphorus doping, and the first microcrystalline silicon layer 130 is P-type doped, such as boron doping. In other examples, the monocrystalline silicon wafer 110 is P-type doped and the first microcrystalline silicon layer 130 is N-type doped.
[0051] In some examples, the thickness of the first microcrystalline silicon layer 130 is 15nm to 40nm, specifically 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, etc.
[0052] Depositing a first microcrystalline silicon layer 130 in the second sub-layer 122 is beneficial for achieving a high crystallinity of the first microcrystalline silicon layer 130. In some examples, the crystallinity of the first microcrystalline silicon layer 130 is approximately 40% to 60%, specifically, for example, 40%, 43%, 45%, 48%, 50%, 53%, 55%, 58%, 60%, etc. The aforementioned first microcrystalline silicon layer 130 has a high crystallinity and a thin thickness, which can improve the photoelectric performance and conversion efficiency of the solar cell 100.
[0053] like Figure 1 As shown, in some examples, the solar cell 100 further includes a second intrinsic amorphous silicon layer 140 and a second microcrystalline silicon layer 150 of a first doped type. The second intrinsic amorphous silicon layer 140 is located on the side of the monocrystalline silicon wafer 110 away from the first intrinsic amorphous silicon layer 120. The second microcrystalline silicon layer 150 is located on the side of the second intrinsic amorphous silicon layer 140 away from the monocrystalline silicon wafer 110.
[0054] The second intrinsic amorphous silicon layer 140 includes a fifth sublayer 141 and a sixth sublayer 142. The fifth sublayer 141 is located between the sixth sublayer 142 and the second microcrystalline silicon layer 150. The sixth sublayer 142 is an amorphous silicon layer containing microcrystals. The crystallinity of the sixth sublayer 142 is less than 1%, specifically, for example, 0.1%, 0.3%, 0.5%, 0.7%, or 0.9%. The crystallinity of the sixth sublayer 142 is greater than that of the fifth sublayer 141.
[0055] The fifth sublayer 141 serves as the main passivation layer, with a crystallinity of less than 1%, specifically 0%, 0.2%, 0.4%, 0.6%, 0.8%, etc. The fifth sublayer 141 plays a primary passivation role, and its thickness can be set relatively large. In some examples, the thickness of the fifth sublayer 141 is 2nm~6nm, specifically 2nm, 3nm, 4nm, 5nm, 6nm, etc.
[0056] Compared to the fifth sublayer 141, the sixth sublayer 142 has a higher crystallinity. Its main function is to enhance the contact with the microcrystalline layer, reduce the series resistance of the battery, and improve the fill factor of the battery. In some examples, the thickness of the sixth sublayer 142 is 0.5nm~1.5nm, specifically 0.5nm, 0.7nm, 0.9nm, 1.1nm, 1.3nm, etc.
[0057] In some examples, the thickness of the fifth sublayer 141 is greater than the thickness of the sixth sublayer 142.
[0058] like Figure 1 As shown, in some examples, the second intrinsic amorphous silicon layer 140 further includes a seventh sublayer 143 and / or an eighth sublayer 144 located between the monocrystalline silicon wafer 110 and the fifth sublayer 141. The seventh sublayer 143 is an oxygen-containing amorphous silicon layer. The crystallinity of the seventh sublayer 143 is less than 1%, and further, the crystallinity of the seventh sublayer 143 is not greater than 0.6%, specifically, for example, 0, 0.2%, 0.4%, 0.6%, etc. The crystallinity of the seventh sublayer 143 is less than the crystallinity of the fifth sublayer 141. The eighth sublayer 144 is an oxygen-free amorphous silicon layer. The crystallinity of the eighth sublayer 144 is less than the crystallinity of the fifth sublayer 141. For example, the crystallinity of the eighth sublayer 144 is less than 1%, and further, the crystallinity of the eighth sublayer 144 is not greater than 0.6%, specifically, for example, 0, 0.2%, 0.4%, 0.6%, etc.
[0059] Depositing the seventh sublayer 143 before depositing the fifth sublayer 141 can prevent the epitaxy of the single-crystal silicon wafer 110.
[0060] The thickness of the seventh sublayer 143 should not be too high. The thickness of the seventh sublayer 143 should be less than 3nm, such as 1nm~3nm, specifically 1nm, 1.5nm, 2nm, 2.5nm, 3nm, etc. If the thickness is too high, it will not play a significant role, but will increase the series resistance.
[0061] In some examples, the thickness of the seventh sublayer 143 is less than the thickness of the fifth sublayer 141.
[0062] Depositing the eighth sublayer 144 before depositing the fifth sublayer 141 can prevent the formation of yellow powder and avoid excessive yellow powder affecting the passivation performance of the silicon wafer.
[0063] In some examples, the thickness of the eighth sublayer 144 is 2nm to 4nm, specifically 2nm, 2.5nm, 3nm, 3.5nm, 4nm, etc.
[0064] In some examples, the thickness of the eighth sublayer 144 is less than the thickness of the fifth sublayer 141.
[0065] When the second intrinsic amorphous silicon layer 140 includes a seventh sublayer 143 and an eighth sublayer 144, the seventh sublayer 143 is located between the monocrystalline silicon wafer 110 and the eighth sublayer 144.
[0066] In some examples, the thickness of the second microcrystalline silicon layer 150 is 15nm to 40nm, specifically 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, etc.
[0067] In some examples, the crystallinity of the second microcrystalline silicon layer 150 is 20% to 40%, specifically 20%, 23%, 25%, 28%, 30%, 33%, 35%, 38%, 40%, etc.
[0068] like Figure 1 As shown, in some examples, the solar cell 100 further includes a transition layer 160. The transition layer 160 is located between the second intrinsic amorphous silicon layer 140 and the second microcrystalline silicon layer 150. The transition layer 160 is an oxygen-containing microcrystalline silicon layer.
[0069] By providing a transition layer with high oxygen content between the second intrinsic amorphous silicon layer 140 and the second microcrystalline silicon layer 150, it is beneficial to improve the short-circuit current of the battery.
[0070] In some examples, the solar cell 100 also includes a first transparent conductive layer 170. The first transparent conductive layer 170 is disposed on the side of the first microcrystalline silicon layer 130 away from the first intrinsic amorphous silicon layer 120.
[0071] In some examples, the solar cell 100 also includes a second transparent conductive layer 180. The second transparent conductive layer 180 is disposed on the side of the second microcrystalline silicon layer 150 away from the second intrinsic amorphous silicon layer 140.
[0072] The first transparent conductive layer 170 and the second transparent conductive layer 180 can be, for example, transparent conductive metal oxides such as indium tin oxide (ITO).
[0073] In some examples, the solar cell 100 also includes a first electrode 190 disposed on the first transparent conductive layer 170.
[0074] In some examples, the solar cell 100 also includes a second electrode 200 disposed on the second transparent conductive layer 180.
[0075] The first electrode 190 and the second electrode 200 can be, for example, silver electrodes, copper electrodes, etc.
[0076] The method for preparing the aforementioned solar cell 100 includes the following steps:
[0077] Step S110: A first intrinsic amorphous silicon layer 120 is deposited on a first doped type single crystal silicon wafer 110 using a CVD process.
[0078] Step S120: Deposit a first microcrystalline silicon layer 130 of the second doping type on the first intrinsic amorphous silicon layer 120.
[0079] Step S120 includes:
[0080] Step S121: Deposit the first sublayer 121 on the single-crystal silicon wafer 110. During the deposition of the first sublayer 121, the process gases are SiH4 and H2, the flow ratio of SiH4 to H2 is 1:(1~1.5), the gas pressure is 0.5 Torr~0.57 Torr, and the ignition power is 600W~800W.
[0081] In step S122, a second sublayer 122 is deposited on the first sublayer 121. During the deposition of the second sublayer 122, the process gases are SiH4 and H2, the flow ratio of SiH4 to H2 is 1:(5~50), the gas pressure is 0.5 Torr~0.6 Torr, and the ignition power is 2000W~2500W.
[0082] The first sublayer 121 prepared by the above process parameters serves as the main passivation layer and plays the main passivation role.
[0083] In the above preparation method, the second sub-layer 122, compared with the outermost layer of the traditional intrinsic amorphous silicon layer, has adjusted the chamber pressure, increased the ignition power, and increased the hydrogen dilution ratio. The properties of the film layer are different from those of the outermost layer of the traditional intrinsic amorphous silicon layer. It is a mixed phase of amorphous and microcrystalline, which can enhance the contact effect with the first microcrystalline silicon layer 130, reduce the series resistance of the battery, and improve the fill factor of the battery.
[0084] By replacing the doped microcrystalline silicon transition layer with the aforementioned second sublayer 122, the increased series resistance caused by the high oxygen content in conventional transition layers is avoided, thus improving the fill factor. Furthermore, it avoids the need for extremely high hydrogen content required to prepare the doped microcrystalline silicon transition layer, thereby reducing the etching effect of hydrogen on the intrinsic amorphous silicon layer. The interface between the outermost layer of the intrinsic amorphous silicon layer and the microcrystalline layer has a high defect state density; however, the above preparation method, by increasing the hydrogen dilution ratio during the preparation of the second sublayer 122, enhances the bonding between hydrogen atoms and dangling bonds, resulting in strong hydrogen passivation.
[0085] In step S110, the CVD process can be, but is not limited to, PECVD (plasma-enhanced chemical vapor deposition), CAT-CVD (catalytic chemical vapor deposition), ECRCVD (electron cyclotron resonance chemical vapor deposition), etc.
[0086] In some examples, in step S121, the ignition time of depositing the first sublayer 121 is 20s to 35s, specifically 25s, 27s, 29s, 31s, 33s, etc.
[0087] The second sublayer 122 is a mixed phase of amorphous and microcrystalline silicon. The crystallinity of this film is improved compared to the conventional structure, but the proportion of amorphous phase is still very high. The main function of the second sublayer 122 is to enhance the contact effect with the first microcrystalline silicon layer 130, reduce the series resistance of the battery, and improve the battery's fill factor and other performance parameters.
[0088] When preparing the second sublayer 122, the specific gas pressure is, for example, 0.5 Torr, 0.51 Torr, 0.52 Torr, 0.53 Torr, 0.54 Torr, 0.55 Torr, 0.56 Torr, 0.57 Torr, 0.58 Torr, 0.59 Torr, 0.6 Torr, etc.
[0089] When fabricating the second sublayer 122, the ignition power is higher than that of conventional amorphous silicon layers, which can improve the crystallinity. In some examples, the ignition power is 2200W~2400W. Specific ignition powers include 2000W, 2050W, 2100W, 2150W, 2200W, 2250W, 2300W, 2350W, 2400W, 2450W, and 2500W.
[0090] When preparing the second sublayer 122, the hydrogen dilution ratio is higher than that used in conventional methods for preparing amorphous silicon layers, which enhances the bonding between hydrogen atoms and dangling bonds and improves hydrogen passivation. In some examples, the flow ratio of SiH4 to H2 is 1:(25~50). Further, the flow ratio of SiH4 to H2 is 1:(25~35). Specific examples of the flow ratio of SiH4 to H2 include 1:5, 1:10, 1:15, 1:20, 1:25, 1:30, 1:35, 1:40, 1:45, and 1:50.
[0091] When preparing the second sublayer 122, the hydrogen dilution ratio should not be too high. An excessively high hydrogen dilution ratio will cause etching of the intrinsic amorphous silicon layer and affect the passivation performance.
[0092] The thickness of the second sublayer 122 can be controlled by the ignition time. In some examples, the ignition time for depositing the second sublayer 122 in step S122 is 1s to 16s. Further, in some examples, the ignition time for depositing the second sublayer 122 in step S122 is 8s to 12s, specifically 8s, 9s, 10s, 11s, 12s, etc.
[0093] In some examples, step S120 further includes the following steps before depositing the first sublayer 121 (step S121):
[0094] Step S123, deposit the third sublayer 123, and / or, step S124, deposit the fourth sublayer 124.
[0095] In some examples, in step S123, the process gas for depositing the third sublayer 123 is SiH4 and CO2, the flow ratio of SiH4 to CO2 is 1:(1~1.5), the gas pressure is 0.5 Torr~0.57 Torr, and the ignition power is 800W~1000W.
[0096] The third sublayer 123 formed by the above process can prevent the epitaxy of the single crystal silicon wafer 110. The thickness of the third sublayer 123 should not be too high. For example, the thickness of the third sublayer 123 should be less than 3nm, specifically 1nm, 1.5nm, 2nm, 2.5nm, 3nm, etc. If the thickness is too high, it will not play a significant role, but will instead increase the series resistance.
[0097] The thickness of the third sublayer 123 can be controlled by the ignition time. In some examples, the ignition time for depositing the third sublayer 123 in step S123 is 4s to 6s, specifically 4s, 4.5s, 5s, 5.5s, 6s, etc.
[0098] In some examples, in step S124, the process gas for depositing the fourth sublayer 124 is SiH4 and H2, the flow ratio of SiH4 to H2 is 1:(0.5~1), the gas pressure is 0.5 Torr~0.57 Torr, and the ignition power is 600W~800W.
[0099] The fourth sublayer 124 formed by the above process can prevent the formation of yellow powder and avoid excessive yellow powder from affecting the passivation performance of the silicon wafer.
[0100] In some examples, the thickness of the fourth sublayer 124 is 2nm to 4nm, specifically 2nm, 2.5nm, 3nm, 3.5nm, 4nm, etc.
[0101] The thickness of the fourth sublayer 124 can be controlled by the ignition time. In some examples, the ignition time for depositing the fourth sublayer 124 in step S124 is 5s to 8s, specifically 5s, 5.5s, 6s, 6.5s, 7s, 7.5s, 8s, etc.
[0102] When both the third sublayer 123 and the fourth sublayer 124 are deposited, step S123 is performed first, followed by step S124. That is, the third sublayer 123 is deposited first, and then the fourth sublayer 124 is deposited on the third sublayer 123.
[0103] In some examples, when depositing the first intrinsic amorphous silicon layer 120, the deposition temperature is 180℃~240℃. The deposition temperature should not be too low or too high. If it is too low, it will cause a decrease in iVoc and fail to achieve the expected passivation effect. If the deposition temperature is too high, it will damage the amorphous silicon layer and cause poor PL.
[0104] In some examples, the process for depositing the first microcrystalline silicon layer 130 in step S120 is a CVD process. The CVD process can be, but is not limited to, PECVD, CAT-CVD, ECRCVD, etc.
[0105] Furthermore, the gas pressure for depositing the first microcrystalline silicon layer 130 is 4 Torr~6 Torr, the process gases are SiH4, CO2, the first dopant source gas and H2, the flow rate ratio is 1:(0.08~0.16):(0.5~1):(200~300), and the ignition power is 5000W~7000W.
[0106] The ignition time for depositing the first microcrystalline silicon layer is, for example, 120s to 170s.
[0107] In some examples, the fabrication method of solar cell 100 also includes:
[0108] In step S130, a second intrinsic amorphous silicon layer 140 is deposited on the monocrystalline silicon wafer 110 using a CVD process. The second intrinsic amorphous silicon layer 140 and the first intrinsic amorphous silicon layer 120 are located on opposite sides of the monocrystalline silicon wafer 110.
[0109] In step S130, the CVD process can be, but is not limited to, PECVD, CAT-CVD, ECRCVD, etc.
[0110] In some examples, step S130 includes:
[0111] Step S131: Deposit a fifth sublayer 141 on the single-crystal silicon wafer 110. The process gases for depositing the fifth sublayer 141 are SiH4 and H2, with a SiH4 to H2 flow rate ratio of 1:(1~1.5), a gas pressure of 0.5 Torr~0.57 Torr, and an ignition power of 600W~800W.
[0112] Step S132: Deposit a sixth sublayer 142 on the fifth sublayer 141. The process gas for depositing the sixth sublayer 142 is SiH4 and H2, with a SiH4 to H2 flow rate ratio of 1:(1~2), and the H2 ratio is greater than that when depositing the fifth sublayer 141. The gas pressure is 0.5 Torr~0.57 Torr, and the ignition power is 600W~800W.
[0113] In some examples, in step S131, the ignition time of depositing the fifth sublayer 141 is 20s to 35s, specifically 25s, 27s, 29s, 31s, 33s, etc.
[0114] In some examples, in step S132, the ignition time for depositing the sixth sublayer 142 is 4s to 6s, specifically 4s, 4.5s, 5s, 5.5s, 6s, etc.
[0115] In some examples, step S130 further includes the following steps before depositing the fifth sublayer 141 (step S131):
[0116] Step S133, deposit the seventh sublayer 143, and / or, step S134, deposit the eighth sublayer 144.
[0117] In some examples, in step S133, the process gas for depositing the seventh sublayer 143 is SiH4 and CO2, with a flow rate ratio of SiH4 to CO2 of 1:(1~1.5), a gas pressure of 0.5 Torr~0.57 Torr, and an ignition power of 800W~1000W.
[0118] In some examples, in step S123, the ignition time for depositing the seventh sublayer 143 is 4s to 6s, specifically 4s, 4.5s, 5s, 5.5s, 6s, etc.
[0119] In some examples, in step S134, the process gas for depositing the eighth sublayer 144 is SiH4 and H2, the flow ratio of SiH4 to H2 is 1:(0.5~1), and the proportion of H2 is less than the proportion of H2 when depositing the fifth sublayer 141. The gas pressure is 0.5 Torr~0.57 Torr, and the ignition power is 600W~800W.
[0120] The eighth sublayer 144 formed by the above process can prevent the formation of yellow powder and avoid excessive yellow powder affecting the passivation performance of the silicon wafer.
[0121] In some examples, the thickness of the eighth sublayer 144 is 2nm to 4nm, specifically 2nm, 2.5nm, 3nm, 3.5nm, 4nm, etc.
[0122] In some examples, in step S134, the ignition time for depositing the eighth sublayer 144 is 5s to 8s, specifically 5s, 5.5s, 6s, 6.5s, 7s, 7.5s, 8s, etc.
[0123] When both the seventh sublayer 143 and the eighth sublayer 144 are deposited, step S133 is performed first, followed by step S134, that is, the seventh sublayer 143 is deposited first, and then the eighth sublayer 144 is deposited on the seventh sublayer 143.
[0124] In some examples, the deposition temperature for the second intrinsic amorphous silicon layer 140 is 180℃~240℃, and the power is 400W~2000W. Too low a temperature results in poor film quality, hindering light transmission. Too high a temperature also leads to poor film quality, manifested as blackening of the photopolymer layer (PL) and decreased passivation performance. Too low a power results in a slow deposition rate, reducing production efficiency and hindering mass production. Too high a power damages the intrinsic amorphous silicon layer, reducing the battery's electrical performance, primarily through a loss of open-circuit voltage.
[0125] In some examples, the fabrication method of solar cell 100 also includes:
[0126] Step S140: Deposit a second microcrystalline silicon layer 150 of the first doped type on the second intrinsic amorphous silicon layer 140.
[0127] In some examples, the process for depositing the second microcrystalline silicon layer 150 in step S140 is a CVD process. The CVD process can be, but is not limited to, PECVD, CAT-CVD, ECRCVD, etc.
[0128] Furthermore, the process gases for depositing the second microcrystalline silicon layer 150 are SiH4, CO2, the second doping source gas, and H2, with a flow ratio of 1:(0.5~8):(0.5~1):(200~300), a gas pressure of 3 Torr~5 Torr, and an ignition power of 6000W~8000W.
[0129] The ignition time for depositing the second microcrystalline silicon layer 150 is, for example, 150s to 200s.
[0130] In some examples, prior to the step of depositing the second microcrystalline silicon layer 150 of the first doped type (step S140), the method for fabricating the solar cell 100 further includes the following steps:
[0131] A transition layer 160 is deposited on the second intrinsic amorphous silicon layer 140.
[0132] In some examples, the deposition process for the transition layer 160 is a CVD process. CVD processes can be, but are not limited to, PECVD, CAT-CVD, ECRCVD, etc.
[0133] Furthermore, the gas pressure of the deposition transition layer 160 is 3 Torr~5 Torr, the process gas is SiH4 and CO2, the flow ratio is 1:(1~8), and the ignition power is 5000W~8000W.
[0134] The ignition time of the depositional transition layer 160 is, for example, 5s to 15s.
[0135] By providing a transition layer with high oxygen content between the second intrinsic amorphous silicon layer 140 and the second microcrystalline silicon layer 150, it is beneficial to improve the short-circuit current of the battery.
[0136] In some examples, the fabrication method of solar cell 100 also includes:
[0137] Step S150: Prepare a first transparent conductive layer 170 on the first microcrystalline silicon layer 130.
[0138] In some examples, the fabrication method of solar cell 100 also includes:
[0139] Step S160: Prepare a second transparent conductive layer 180 on the second microcrystalline silicon layer 150.
[0140] The first transparent conductive layer 170 and the second transparent conductive layer 180 can be, for example, transparent conductive metal oxides such as indium tin oxide (ITO), and the preparation process can be, for example, PVD (physical vapor deposition).
[0141] In some examples, the fabrication method of solar cell 100 also includes:
[0142] Step S170: Prepare a first electrode 190 on the first transparent conductive layer 170.
[0143] In some examples, the fabrication method of solar cell 100 also includes:
[0144] Step S180: Prepare a second electrode 200 on the second transparent conductive layer 180.
[0145] The first electrode 190 and the second electrode 200 can be, for example, silver electrodes or copper electrodes, and can be prepared by processes such as screen printing and electroplating. When the electrode is a silver electrode, it is generally prepared by screen printing. When the electrode is a copper electrode, it is generally prepared by electroplating.
[0146] In the above preparation method, the second sublayer 122 differs from the outermost layer of the traditional intrinsic amorphous silicon layer in that it has adjusted the chamber pressure, increased the ignition power, and increased the hydrogen dilution ratio. The film properties are different from the outermost layer of the traditional intrinsic amorphous silicon layer, being a mixed phase of amorphous and microcrystalline phases. Using the above-mentioned second sublayer 122 to replace the transition layer of the microcrystalline silicon layer avoids the increased series resistance caused by the high oxygen content of conventional transition layers, and improves performance parameters such as the fill factor. Furthermore, it avoids the need for extremely high hydrogen content required for preparing the transition layer of the microcrystalline silicon layer, thereby reducing the etching effect of hydrogen on the intrinsic amorphous silicon layer. The interface between the outermost layer of the intrinsic amorphous silicon layer and the microcrystalline layer has a large number of defect state densities. The above preparation method, by increasing the hydrogen dilution ratio during the preparation of the second sublayer 122, enhances the bonding effect between hydrogen atoms and dangling bonds, resulting in a strong hydrogen passivation effect.
[0147] The following specific embodiments further illustrate this utility model. These specific embodiments are provided to better understand this utility model, but are not limited to the specific implementation methods and do not constitute a limitation on the scope of protection of this utility model.
[0148] Example 1
[0149] This embodiment provides a method for fabricating a solar cell, including the following steps:
[0150] (1) Obtain an N-type doped single crystal silicon wafer and texturize the front and back sides of the single crystal silicon wafer.
[0151] (2) A first intrinsic amorphous silicon layer is deposited on the back side of an N-type monocrystalline silicon wafer using PECVD, and a second intrinsic amorphous silicon layer is deposited on the front side. The first and second intrinsic amorphous silicon layers consist of, in sequence:
[0152] Deposition of sublayer 1 on both sides: The process gases are SiH4 and CO2, the gas pressure is 0.55 Torr, the ignition power is 900W, the flow ratio of SiH4 to CO2 is 1:1, the ignition time is 5s, the crystallinity of sublayer 1 is 0.4%, and the thickness is 1.2nm.
[0153] Deposition of sublayer 2 on both sides: The process gases are SiH4 and H2, the gas pressure is 0.55 Torr, the ignition power is 600W, the flow ratio of SiH4 to H2 is 1:0.5, the ignition time is 7s, the crystallinity of sublayer 2 is 0.6%, and the thickness is 1.3nm.
[0154] Deposition of sublayer 3 on both sides: The process gases are SiH4 and H2, the gas pressure is 0.55 Torr, the ignition power is 700W, the flow ratio of SiH4 to H2 is 1:1.2, the ignition time is 25s, the crystallinity of sublayer 3 is 0.8%, and the thickness is 3.9nm.
[0155] Deposition of sublayer 4 on the back side: The process gases are SiH4 and H2, the gas pressure is 0.58 Torr, the ignition power is 2200W, the flow ratio of SiH4 to H2 is 1:25, the ignition time is 9s, the crystallinity of sublayer 4 is 4%, and the thickness is 2nm.
[0156] Deposition of sublayer 4 on the front side: The process gases are SiH4 and H2, the gas pressure is 0.55 Torr, the ignition power is 700W, the flow ratio of SiH4 to H2 is 1:1.5, the ignition time is 5s, the crystallinity of sublayer 4 is 0.7%, and the thickness is 1.1nm.
[0157] (3) A transition layer and an N-type doped microcrystalline silicon layer are sequentially deposited on the side of the second intrinsic amorphous silicon layer on the front side away from the single-crystal silicon wafer using PECVD technology. Specifically:
[0158] Deposition of the transition layer: The process gases are SiH4 and CO2, the gas pressure is 4 Torr, the ignition power is 6000W, the flow ratio of SiH4 to CO2 is 1:4, and the ignition time is 10s.
[0159] Deposition of N-type doped microcrystalline silicon layer: The process gases are SiH4, CO2, PH3, and H2, with a flow ratio of 1:4:1:280, a gas pressure of 4 Torr, an ignition power of 7500 W, and an ignition time of 150 s. The thickness of the N-type doped microcrystalline silicon layer is 35 nm.
[0160] (4) A P-type doped microcrystalline silicon layer is deposited on the side of the first intrinsic amorphous silicon layer on the back side away from the single crystal silicon wafer using the PECVD process. The process gases are SiH4, CO2, B2H6 and H2, with a flow ratio of 1:0.12:1:290, a gas pressure of 5 Torr, an ignition power of 6500W, and an ignition time of 160s.
[0161] (5) ITO is deposited on the back side using magnetron sputtering to form a first transparent conductive layer with a thickness of 100 nm, and ITO is deposited on the front side to form a second transparent conductive layer with a thickness of 95 nm.
[0162] (6) Silver grid lines are prepared on the front and back sides respectively using screen printing process.
[0163] Example 2
[0164] The steps in this embodiment are basically the same as those in Embodiment 1, except that the process parameters of the fourth sublayer in the first intrinsic amorphous silicon layer on the back side are different. The process parameters of the fourth sublayer are: process gases are SiH4 and H2, gas pressure is 0.55 Torr, ignition power is 2000W, SiH4 and H2 flow ratio is 1:25, ignition time is 8s, crystallinity of the fourth sublayer is 3.5%, and thickness is 1.5nm.
[0165] Example 3
[0166] The steps in this embodiment are basically the same as those in Embodiment 1, except that the process parameters of the fourth sublayer in the first intrinsic amorphous silicon layer on the back side are different. The process parameters of the fourth sublayer are: process gases are SiH4 and H2, gas pressure is 0.55 Torr, ignition power is 2500W, SiH4 and H2 flow ratio is 1:25, ignition time is 10s, crystallinity of the fourth sublayer is 4.5%, and thickness is 2.5nm.
[0167] Example 4
[0168] The steps in this embodiment are basically the same as those in Embodiment 1, except that the process parameters of the fourth sublayer in the first intrinsic amorphous silicon layer on the back side are different. The process parameters of the fourth sublayer are: process gases are SiH4 and H2, gas pressure is 0.6 Torr, ignition power is 2200W, SiH4 and H2 flow ratio is 1:25, ignition time is 8s, crystallinity of the fourth sublayer is 4.2%, and thickness is 2.5nm.
[0169] Example 5
[0170] The steps in this embodiment are basically the same as those in Embodiment 1, except that the process parameters of the fourth sublayer in the first intrinsic amorphous silicon layer on the back side are different. The process parameters of the fourth sublayer are: process gases are SiH4 and H2, gas pressure is 0.5 Torr, ignition power is 2200W, SiH4 and H2 flow ratio is 1:35, ignition time is 8s, crystallinity of the fourth sublayer is 5%, and thickness is 1.3nm.
[0171] Example 6
[0172] The steps in this embodiment are basically the same as those in Embodiment 1, except that the process parameters of the fourth sublayer in the first intrinsic amorphous silicon layer on the back side are different. The process parameters of the fourth sublayer are: process gases are SiH4 and H2, gas pressure is 0.58 Torr, ignition power is 2200W, SiH4 and H2 flow ratio is 1:5, ignition time is 1.6s, crystallinity of the fourth sublayer is 2%, and thickness is 2nm.
[0173] Example 7
[0174] The steps in this embodiment are basically the same as those in Embodiment 1, except that the process parameters of the fourth sublayer in the first intrinsic amorphous silicon layer on the back side are different. The process parameters of the fourth sublayer are: process gases are SiH4 and H2, gas pressure is 0.58 Torr, ignition power is 2200W, SiH4 and H2 flow ratio is 1:50, ignition time is 16s, crystallinity of the fourth sublayer is 5%, and thickness is 2nm.
[0175] Comparative Example 1
[0176] The difference between this comparative example and Example 1 is that the process parameters of the fourth sublayer in the first intrinsic amorphous silicon layer on the back side are different. The process gases are SiH4 and H2, the gas pressure is 0.52 Torr, the ignition power is 700 W, the flow ratio of SiH4 to H2 is 1:1.5, the ignition time is 12 s, the crystallinity of the fourth sublayer is 0.8%, and the thickness is 2 nm.
[0177] Comparative Example 2
[0178] The difference between this comparative example and Example 1 is that the process parameters of the fourth sublayer in the first intrinsic amorphous silicon layer on the back side are different. The process gases are SiH4 and H2, the gas pressure is 0.55 Torr, the ignition power is 2200W, the flow ratio of SiH4 to H2 is 1:200, the ignition time is 25s, the crystallinity of the fourth sublayer is 15%, and the thickness is 2nm.
[0179] Comparative Example 3
[0180] The difference between this comparative example and Example 1 is that the process parameters of the fourth sublayer in the first intrinsic amorphous silicon layer on the back side are different. The process gases are SiH4 and H2, the gas pressure is 0.55 Torr, the ignition power is 2200W, the flow ratio of SiH4 to H2 is 1:300, the ignition time is 60s, the crystallinity of the fourth sublayer is 18%, and the thickness is 2nm.
[0181] Comparative Example 4
[0182] The difference between this comparative example and Example 1 is as follows:
[0183] (1) The process parameters of the fourth sublayer in the first intrinsic amorphous silicon layer on the back side are different. The process gases are SiH4 and H2, the gas pressure is 0.55 Torr, the ignition power is 700W, the flow ratio of SiH4 and H2 is 1:1.5, the ignition time is 5s, the crystallinity of the fourth sublayer is 0.7%, and the thickness is 1.1nm.
[0184] (2) Before depositing the P-type doped microcrystalline silicon layer in step (4), a PO layer is deposited on the neutron layer 4 of the first intrinsic amorphous silicon layer on the back side. The process parameters are: the process gases are SiH4, CO2, B2H6 and H2, the flow ratio is 1:0.25:0.6:320, the gas pressure is 6 Torr, the ignition power is 7500W, and the ignition time is 5s.
[0185] The solar cells prepared in the above embodiments and comparative examples were tested as follows, and the test results are shown in Table 1 below.
[0186] Table 1. Electrical performance of solar cells prepared in the examples and comparative examples.
[0187]
[0188] As shown in Table 1, the open-circuit voltage, fill factor, and conversion efficiency of the solar cells prepared in Examples 1-7 are all improved compared to Comparative Examples 1-4. Specifically, in Comparative Example 1, the process parameters of the first intrinsic amorphous silicon neutron layer 4 on the back side and the second intrinsic amorphous silicon neutron layer 4 on the front side are basically the same, both being amorphous phases. This results in poor contact with the microcrystalline silicon layer, leading to a decrease in parameters such as open-circuit voltage, short-circuit current, fill factor, and conversion efficiency. Comparative Examples 2 and 3 use a higher hydrogen dilution ratio, resulting in excessively high film crystallinity, approaching that of a microcrystalline layer. This increases the series resistance, and the excessively high hydrogen dilution ratio etches the intrinsic amorphous silicon layer, affecting passivation performance and causing a decrease in parameters such as open-circuit voltage, fill factor, and conversion efficiency. Comparative Example 4 uses a traditional P0 layer setup. Compared to Comparative Example 4, Example 1 shows improved overall electrical performance, indicating that this solution can overcome the negative effects of removing the P0 layer and further improve cell performance.
[0189] Compared with Example 1, Example 6 has a lower hydrogen dilution ratio and a slightly higher open-circuit voltage. However, the contact effect between the back sublayer four and the P-type doped microcrystalline silicon layer is relatively poor, resulting in a decrease in conversion efficiency, short-circuit current, and fill factor. Compared with Example 1, Example 7 has an increased hydrogen dilution ratio. Although this improves the contact efficiency between the back sublayer four and the P-type doped microcrystalline silicon layer, the higher crystallinity of sublayer four leads to a decrease in open-circuit voltage and short-circuit current, resulting in a decrease in conversion efficiency.
[0190] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0191] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims, and the specification can be used to interpret the content of the claims.
Claims
1. A solar cell (100), characterized in that, It includes a first doped type monocrystalline silicon wafer (110) and a first intrinsic amorphous silicon layer (120) and a second doped type first microcrystalline silicon layer (130) stacked on the monocrystalline silicon wafer (110). The first intrinsic amorphous silicon layer (120) includes a first sublayer (121) and a second sublayer (122). The first sublayer (121) is located between the second sublayer (122) and the first microcrystalline silicon layer (130). The second sublayer (122) contains microcrystals. The crystallinity of the second sublayer (122) is 1% to 5%, and the thickness of the second sublayer (122) is 1.3 nm to 2.5 nm.
2. The solar cell (100) as described in claim 1, characterized in that, The first intrinsic amorphous silicon layer (120) further includes a third sublayer (123) and / or a fourth sublayer (124) located between the monocrystalline silicon wafer (110) and the first sublayer (121). The third sublayer (123) is an oxygen-containing amorphous silicon layer, and the crystallinity of the third sublayer (123) is less than 1%. The fourth sublayer (124) is an oxygen-free amorphous silicon layer, and the crystallinity of the fourth sublayer (124) is less than that of the first sublayer (121). When the first intrinsic amorphous silicon layer (120) further includes the third sublayer (123) and the fourth sublayer (124), the third sublayer (123) is located between the monocrystalline silicon wafer (110) and the fourth sublayer (124).
3. The solar cell (100) as described in claim 2, characterized in that, The solar cell (100) meets at least one of the following characteristics (1) to (3): (1) The thickness of the first sublayer (121) is 2nm~6nm; (2) The thickness of the third sublayer (123) is 1nm~3nm; (3) The thickness of the fourth sublayer (124) is 0.5nm~2nm.
4. The solar cell (100) as described in any one of claims 1 to 3, characterized in that, The solar cell (100) further includes a second intrinsic amorphous silicon layer (140) and a second microcrystalline silicon layer (150) of a first doping type. The second intrinsic amorphous silicon layer (140) is located on the side of the monocrystalline silicon wafer (110) away from the first intrinsic amorphous silicon layer (120), and the second microcrystalline silicon layer (150) is located on the side of the second intrinsic amorphous silicon layer (140) away from the monocrystalline silicon wafer (110).
5. The solar cell (100) as described in claim 4, characterized in that, The solar cell (100) meets at least one of the following characteristics (1) to (2): (1) The crystallinity of the first microcrystalline silicon layer (130) is 40%~60%; (2) The crystallinity of the second microcrystalline silicon layer (150) is 20%~40%.
6. The solar cell (100) as described in claim 4, characterized in that, The solar cell (100) further includes a transition layer (160), which is located between the second intrinsic amorphous silicon layer (140) and the second microcrystalline silicon layer (150), and the transition layer (160) is an oxygen-containing microcrystalline silicon layer.
7. The solar cell (100) as described in claim 4, characterized in that, The second intrinsic amorphous silicon layer (140) includes a fifth sublayer (141) and a sixth sublayer (142), wherein the fifth sublayer (141) is located between the sixth sublayer (142) and the second microcrystalline silicon layer (150), and the crystallinity of the sixth sublayer (142) is less than 1%, and the crystallinity of the sixth sublayer (142) is greater than that of the fifth sublayer (141).
8. The solar cell (100) as described in claim 7, characterized in that, The second intrinsic amorphous silicon layer (140) further includes a seventh sublayer (143) and / or an eighth sublayer (144) located between the monocrystalline silicon wafer (110) and the fifth sublayer (141); wherein the seventh sublayer (143) is an oxygen-containing amorphous silicon layer with a crystallinity of less than 1%, and the eighth sublayer (144) is an oxygen-free amorphous silicon layer with a crystallinity of less than that of the fifth sublayer (141); When the second intrinsic amorphous silicon layer (140) includes the seventh sublayer (143) and the eighth sublayer (144), the seventh sublayer (143) is located between the monocrystalline silicon wafer (110) and the eighth sublayer (144).
9. The solar cell (100) as described in claim 8, characterized in that, The solar cell (100) meets at least one of the following characteristics (1) to (4): (1) The thickness of the fifth sublayer (141) is 2nm~6nm; (2) The thickness of the sixth sublayer (142) is 0.5 nm to 1.5 nm; (3) The thickness of the seventh sublayer (143) is 1nm~3nm; (4) The thickness of the eighth sublayer (144) is 2nm~4nm.
10. The solar cell (100) as claimed in claim 9, characterized in that, The solar cell (100) meets at least one of the following characteristics (1) to (2): (1) The solar cell (100) further includes a first transparent conductive layer (170), which is disposed on the side of the first microcrystalline silicon layer (130) away from the first intrinsic amorphous silicon layer (120); (2) The solar cell (100) further includes a second transparent conductive layer (180), which is disposed on the side of the second microcrystalline silicon layer (150) away from the second intrinsic amorphous silicon layer (140).