一种高密度型竖直全环栅晶体管
By using the common-source, common-drain design of high-density vertical full-ring gate transistors and through-silicon via (TSV) technology, the problem of space occupation by independent source/drain electrodes and isolation layers is solved, thereby increasing the number of devices and integration density and meeting the high-speed switching and low-power consumption requirements of high-performance computing chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HUIZHOU LIMAI ELECTRONICS CO LTD
- Filing Date
- 2025-09-01
- Publication Date
- 2026-07-17
AI Technical Summary
Existing vertical channel devices occupy additional space due to their independent source/drain electrode design and independent isolation layer interconnect structure, resulting in limited improvement in integration density.
By employing a common-source, common-drain design with adjacent layers sharing the drain electrode, and through-silicon via (TSV) technology, combined with a low-dielectric-constant isolation layer, a high-density vertical full-ring gate transistor is formed, optimizing space utilization through vertical stacking and three-dimensional layout.
Within the same chip area, it significantly increases the number of devices and integration density, reduces inter-layer signal transmission delay, reduces space waste, and meets the high-density logic circuits' requirements for high-speed switching and low power consumption.
Smart Images
Figure CN224521484U_ABST
Abstract
Claims
1. A high-density vertical all-around gate transistor, characterized by: Includes substrate (1); The substrate (1) is a silicon-on-insulator substrate with a shallow trench isolation structure formed on its surface; The substrate (1) is provided with a plurality of semiconductor nanowire channels (2), each of the semiconductor nanowire channels (2) being perpendicular to the substrate (1); A gate (201) is disposed on the surface of each of the semiconductor nanowire channels (2), and an insulating film (202) is disposed between the gate (201) and each of the semiconductor nanowire channels (2); Each of the semiconductor nanowire channels (2) has a source (203) and a drain (204) respectively at both ends; The surface of the semiconductor nanowire channel (2) is treated with low-temperature ozone at the quasi-atomic level to form a clean interface free of germanium atoms.
2. The high-density vertical gate-all-around transistor of claim 1, wherein: The semiconductor nanowire channels (2) are arranged in a ring array, and each semiconductor nanowire channel (2) adopts an alternating superimposed silicon / silicon germanium / silicon three-layer structure.
3. The high-density vertical gate-all-around transistor of claim 1, wherein: The source (203) and drain (204) are graphene source and graphene drain, respectively, the gate (201) is titanium nitride metal gate, and the insulating film (202) is hafnium oxide insulating film.
4. The high-density vertical gate-all-around transistor of claim 1, wherein: The source (203) and drain (204) are disposed at both ends of the semiconductor nanowire channel (2) by chemical vapor deposition.
5. The high-density vertical gate-all-around transistor of claim 1, wherein: The gate (201) is formed by an atomic layer deposition process to create a continuous, seamless structure surrounding the semiconductor nanowire channel (2).
6. The high-density vertical gate-all-around transistor of claim 1, wherein: The insulating film (202) is formed by plasma-enhanced atomic layer deposition.
7. The high-density vertical gate-all-around transistor of claim 1, wherein: At least two vertically stacked semiconductor nanowire channel (2) arrays are provided on the substrate (1), and adjacent layers share a drain electrode (204) to form a common source and common drain three-dimensional device structure.
8. The high-density vertical gate-all-around transistor of claim 7, wherein: The three-dimensional device structure achieves interlayer interconnection through through-silicon via (TSV) technology.