Power semiconductor device and packaging structure
By setting a through-conductive structure on the substrate to achieve vertical coupling integration of the power chip and the tunnel magnetoresistive structure, the problem of poor compatibility of power semiconductor devices in different package housings is solved, improving versatility and integration efficiency, and reducing design complexity and cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG CHINT ELECTRIC CO LTD
- Filing Date
- 2025-07-16
- Publication Date
- 2026-07-17
AI Technical Summary
Existing power semiconductor devices suffer from poor packaging compatibility in different package housings, leading to high design complexity, increased costs, and extended development cycles.
By setting a through conductive structure on the first substrate, the power chip and the tunnel magnetoresistive structure are vertically coupled and integrated, a unified substrate platform is built to adapt to various package types, avoiding the need to design sensor wiring and support structures separately for each package.
It improves the versatility and integration efficiency of power semiconductor devices in different packages, reduces design complexity and cost, and enhances design flexibility and reliability.
Smart Images
Figure CN224521531U_ABST
Abstract
Claims
1. A power semiconductor device, characterized in that, include: A first substrate, wherein the first substrate has a plurality of conductive structures; A power chip is located on one side surface of the first substrate and is coupled to the conductive structure; The tunnel magnetoresistive structure is located on the side of the first substrate facing away from the power chip and is coupled to the conductive structure.
2. The power semiconductor device according to claim 1, characterized in that, The projection of the tunnel magnetoresistive structure onto the surface of the first substrate does not overlap with the projection of the power chip onto the surface of the first substrate.
3. The power semiconductor device of claim 1, wherein, The tunnel magnetoresistive structure includes multiple tunnel magnetoresistive units arranged in an array. The tunnel magnetoresistive unit includes a first metal layer, an insulating layer, and a second metal layer sequentially stacked on the surface of the first substrate away from the power chip. Adjacent tunnel magnetoresistive units are interconnected by an electrical interconnection structure, which is composed of at least one of the first metal layer and the second metal layer.
4. The power semiconductor device of claim 1, wherein, The power chip has a heat dissipation layer covering the side of its surface facing the first substrate.
5. The power semiconductor device of claim 1, wherein, The power chip has a heat dissipation structure on the side surface facing away from the first substrate; The heat dissipation structure includes a liquid-cooled substrate and a heat dissipation pipe. The liquid-cooled substrate covers the side surface of the power chip away from the first substrate. The liquid-cooled substrate has a flow channel, and the flow channel of the liquid-cooled substrate is connected to the heat dissipation pipe. Coolant flows through the flow channel of the liquid-cooled substrate and the heat dissipation pipe.
6. The power semiconductor device of claim 1, wherein, A temperature sensor is also provided between the power chip and the first substrate; The temperature sensor is used to detect the junction temperature of the power chip and output a temperature signal. The temperature signal is used for external circuitry to perform temperature compensation on the output of the tunnel magnetoresistive structure and / or to perform over-temperature protection on the power semiconductor device.
7. The power semiconductor device of claim 1, wherein, The first substrate has a plurality of through-holes that pass through it. The inner wall of the through-holes is covered with a dielectric layer, the surface of the dielectric layer is covered with a conductive layer, and the conductive layer fills the through-holes. The conductive layer and the dielectric layer together constitute the conductive structure.
8. A package structure, characterized by, include: The encapsulation housing has a receiving cavity; The power semiconductor device according to any one of claims 1-7 is located within the accommodating cavity.
9. The packaging structure according to claim 8, characterized in that, It also includes a shielding structure, the shielding structure comprising: A metal shielding mesh is connected to the inner wall of the encapsulation housing; A shielding and absorption layer is connected to the side of the metal shielding mesh that is away from the encapsulation housing; A composite metal film layer covers the side of the shielding and absorption layer that is away from the metal shielding mesh.
10. The packaging structure according to claim 8, characterized in that, The encapsulation housing has a first dimension L1 in a first direction and a second dimension L2 in a second direction. The diameter D of the conductive structure is related to the first dimension or the second dimension by the following condition: D = k * max(L1, L2), where k is a proportionality constant. Wherein, both the first direction and the second direction are perpendicular to the thickness direction of the first substrate, and the first direction and the second direction intersect.