Display panel and display device

Abstract

The utility model provides a kind of display panel and display device, to improve the ESD bearing capacity of display panel.Display panel includes: substrate, multiple data lines being set on substrate, multiple first power lines, multiple subpixels and multiple compensation structures.Multiple data lines and multiple subpixels are connected, configured to provide data signal for multiple subpixels, multiple first power lines are connected with multiple subpixels, configured to provide first power signal for multiple subpixels.Compensation structure includes: first compensation block and second compensation block located in different conductive layers.First compensation block is connected with data line by first transfer electrode, second compensation block is connected with first power line by second transfer electrode, the film layer where first transfer electrode, second transfer electrode, data line and first power line are located is located on the side of compensation structure film layer away from substrate.

Description

Technical Field

[0001] This utility model relates to, but is not limited to, the field of display technology, and particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Utility Model Content

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This utility model provides a display panel and display device to improve the ESD resistance of the display panel.

[0005] On one hand, this embodiment provides a display panel, including: a substrate, multiple data lines, multiple first power lines, multiple sub-pixels, and multiple compensation structures disposed on the substrate. The substrate includes a display area and a border area located on at least one side of the display area. The multiple data lines, multiple first power lines, and multiple sub-pixels are located in the display area; the multiple data lines and the multiple sub-pixels are connected and configured to provide data signals to the multiple sub-pixels, and the multiple first power lines are connected to the multiple sub-pixels and configured to provide first power signals to the multiple sub-pixels. The multiple compensation structures are located in the border area, and the compensation structures include: a first compensation block and a second compensation block located in different conductive layers, the first compensation block being connected to the data lines through a first adapter electrode, and the second compensation block being connected to the first power lines through a second adapter electrode; the film layers containing the first adapter electrode, the second adapter electrode, the data lines, and the first power lines are located on the side of the film layer containing the compensation structures away from the substrate.

[0006] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element, the pixel circuit being connected to the light-emitting element, the pixel circuit including a plurality of transistors; the orthographic projections of the first compensation block and the second compensation block on the substrate do not overlap with the orthographic projections of the active layer of the plurality of transistors of the pixel circuit on the substrate.

[0007] In some exemplary embodiments, the first compensation block has a first main block and a first connecting segment, and the second compensation block has a second main block and a second connecting segment; the size of the first connecting segment is smaller than the size of the first main block, and the size of the second connecting segment is smaller than the size of the second main block; the orthographic projection of the first main block on the substrate and the orthographic projection of the second main block on the substrate at least partially overlap, the first connecting segment is connected to the data line through the first adapter electrode, and the second connecting segment is connected to the first power line through the second adapter electrode.

[0008] In some exemplary embodiments, the first compensation block is located on the side of the second compensation block away from the substrate.

[0009] In some exemplary embodiments, the compensation structure further includes: a third compensation block located on the side of the first compensation block away from the substrate; the third compensation block having a third main block and a third connecting segment, the size of the third connecting segment being smaller than the size of the third main block; the orthographic projection of the third main block on the substrate at least partially overlapping the orthographic projection of the first main block on the substrate, and the third connecting segment of the third compensation block being connected to the second connecting segment of the second compensation block via the second adapter electrode.

[0010] In some exemplary embodiments, the second compensation block is located in the first gate metal layer, the first compensation block is located in the second gate metal layer, and the third compensation block is located in the third gate metal layer.

[0011] In some exemplary embodiments, the second connecting segment of the second compensation block of at least one of the plurality of compensation structures is a serpentine winding.

[0012] In some exemplary embodiments, the minimum width of the end of the second connecting segment of the second compensation block of at least one of the plurality of compensation structures is greater than or equal to 3 micrometers.

[0013] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element. The pixel circuit is connected to the light-emitting element. The pixel circuit includes at least a driving transistor and a threshold compensation transistor. A first terminal of the threshold compensation transistor is connected to a second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor. The active layer of the threshold compensation transistor includes a first channel region, a second channel region, and a conductive region connected between the first channel region and the second channel region. The orthographic projection of the second connection segment of the second compensation block on the substrate at least partially overlaps with the orthographic projection of the conductive region of the active layer of the threshold compensation transistor on the substrate.

[0014] In some exemplary embodiments, the first compensation block is located on the side of the second compensation block closer to the substrate.

[0015] In some exemplary embodiments, the display panel further includes: a first frame power line located in the frame area, wherein any corner of the first frame power line is chamfered.

[0016] In some exemplary embodiments, the display panel further includes: a second frame power line located in the frame area, the second frame power line being located on the side of the first frame power line away from the display area, and a chamfer being formed at any corner of the second frame power line.

[0017] In some exemplary embodiments, the display panel further includes a bottom shielding metal layer located on the side of the plurality of sub-pixels near the substrate. The bottom shielding metal layer comprises a first structure located in the display area and a second structure located in the border area, the first structure and the second structure being connected to form a mesh structure, the second structure surrounding the display area.

[0018] In some exemplary embodiments, the display panel further includes a composite insulating layer and a plurality of auxiliary semiconductor blocks located on the side of the bottom shielding metal layer away from the substrate. The composite insulating layer has a plurality of auxiliary vias in the frame region, and the auxiliary vias are configured to expose the surface of the auxiliary semiconductor blocks. The orthographic projections of the plurality of auxiliary vias and the plurality of auxiliary semiconductor blocks onto the substrate do not overlap with the orthographic projection of the second structure onto the substrate.

[0019] In some exemplary embodiments, the display panel further includes: a plurality of connecting lines located in the frame area, wherein the orthographic projection of the plurality of connecting lines on the substrate overlaps with the orthographic projection of the second structure on the substrate, and a plurality of inorganic insulating layers are disposed between the film layer containing the plurality of connecting lines and the second structure.

[0020] In some exemplary embodiments, the plurality of connection lines are located in the source / drain metal layer.

[0021] In some exemplary embodiments, the display panel further includes: panel crack detection traces located in the bezel area; the panel crack detection traces include: at least two detection line segments connected in sequence, the detection line segments being serpentine windings.

[0022] In some exemplary embodiments, the panel crack detection trace further includes a detection connection segment, which connects two adjacent detection segments, and the film layer on which the detection connection segment is located is located on the side of the film layer on which the detection segment is located away from the substrate.

[0023] On the other hand, this embodiment provides a display device, including the display panel as described above.

[0024] On the other hand, this embodiment also provides a display panel, including: a substrate, multiple data lines, multiple first power lines, multiple sub-pixels, and multiple compensation structures disposed on the substrate. The substrate includes a display area and a border area located on at least one side of the display area. The multiple data lines, multiple first power lines, and multiple sub-pixels are located in the display area; the multiple data lines and the multiple sub-pixels are connected and configured to provide data signals to the multiple sub-pixels, and the multiple first power lines are connected to the multiple sub-pixels and configured to provide first power signals to the multiple sub-pixels. The multiple compensation structures are located in the border area, and the compensation structures include: a first compensation block and a second compensation block located in different conductive layers; the first compensation block has a first main block and a first connecting segment, and the second compensation block has a second main block and a second connecting segment; the size of the first connecting segment is smaller than the size of the first main block, and the size of the second connecting segment is smaller than the size of the second main block; the orthographic projection of the first main block on the substrate and the orthographic projection of the second main block on the substrate at least partially overlap, the first connecting segment is connected to the data lines, and the second connecting segment is connected to the first power lines. The minimum width of the end of the second compensation block of at least one of the plurality of compensation structures is greater than or equal to 3 micrometers.

[0025] In some exemplary embodiments, the minimum width of the end of the second compensation block of at least one of the plurality of compensation structures is 8 micrometers.

[0026] In some exemplary embodiments, the second connecting segment of the second compensation block of at least one of the plurality of compensation structures is a serpentine winding.

[0027] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element. The pixel circuit is connected to the light-emitting element. The pixel circuit includes at least a driving transistor and a threshold compensation transistor. A first terminal of the threshold compensation transistor is connected to a second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor. The active layer of the threshold compensation transistor includes a first channel region, a second channel region, and a conductive region connecting the first channel region and the second channel region. The orthographic projection of the second connection segment of the second compensation block onto the substrate at least partially overlaps with the orthographic projection of the conductive region of the active layer of the threshold compensation transistor onto the substrate.

[0028] In some exemplary embodiments, the first compensation block is located on the side of the second compensation block closer to the substrate.

[0029] The display panel provided in this embodiment improves the compensation structure, thereby reducing the discharge capacity of the compensation structure, thus reducing the possibility of ESD generation, preventing the static electricity released by the compensation structure from damaging other film layers, and thus improving the ESD resistance of the display panel.

[0030] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0031] The accompanying drawings are provided to further understand the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this utility model to explain the technical solution of this utility model, and do not constitute a limitation on the technical solution of this utility model.

[0032] Figure 1 This is a schematic diagram of a display panel according to at least one embodiment of the present invention; Figure 2 This is an equivalent circuit diagram of the pixel circuit of at least one embodiment of the present invention; Figure 3 This is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present invention; Figure 4 This is an example diagram illustrating the configuration of the gate drive circuit in at least one embodiment of the present invention; Figure 5 for Figure 1 A schematic diagram of the local structure of the central region S1; Figure 6 for Figure 1 A schematic diagram of a local membrane layer in the central region S1; Figure 7A for Figure 6 A schematic diagram of the first gate metal layer in the diagram; Figure 7B for Figure 6 A schematic diagram of the first and second gate metal layers in the diagram; Figure 7C for Figure 6 A schematic diagram of the first gate metal layer, the second gate metal layer, and the third gate metal layer in the diagram; Figure 7D for Figure 6 A schematic diagram of the first gate metal layer, the second gate metal layer, the third gate metal layer, and the first source / drain metal layer; Figure 8 This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present invention; Figure 9 This is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present invention; Figure 10 for Figure 1Another partial schematic diagram of the central region S2; Figure 11A for Figure 10 A schematic diagram of the first semiconductor layer; Figure 11B for Figure 10 A schematic diagram of the first gate metal layer and the first semiconductor layer; Figure 12 for Figure 1 Another partial schematic diagram of the central region S1; Figure 13 for Figure 1 A schematic diagram of the local structure of the central region S2; Figure 14 for Figure 1 A schematic diagram of the local structure of the central region S3; Figure 15 for Figure 1 Another partial structural diagram of the central region S3; Figure 16 This is another schematic diagram of the display panel of at least one embodiment of the present invention; Figure 17 for Figure 16 A schematic diagram of the local structure of the central region S4; Figure 18 for Figure 16 Another partial structural diagram of the central region S4; Figure 19 This is a schematic diagram of a display device according to at least one embodiment of the present invention. Detailed Implementation

[0033] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings. The embodiments can be implemented in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this utility model. Therefore, this utility model should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this utility model can be arbitrarily combined with each other.

[0034] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, one aspect of the invention is not necessarily limited to these dimensions, and the shape and size of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of the invention is not limited to the shapes or values ​​shown in the drawings.

[0035] The ordinal numbers "first," "second," and "third" used in this specification are provided to avoid confusion among the constituent elements, not to limit the quantity. In this utility model, "multiple" refers to two or more items.

[0036] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this utility model. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as needed.

[0037] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this invention according to the specific circumstances.

[0038] In this specification, "connection" includes "electrical connection." "Electrical connection" includes situations where components are connected together by elements that have some electrical function. There are no particular limitations on the "elements that have some electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0039] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0040] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0041] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0042] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0043] In this invention, "approximately" and "about" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this invention, "same" can include cases where the index values ​​differ by no more than 10%.

[0044] In this invention, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this invention, "A extends along direction B" refers to "the main part of A extends along direction B".

[0045] In this specification, "A and B are of the same layer structure" and "A and B are arranged in the same layer" mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are at approximately the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. "Same layer" does not always mean that the layer thickness or height is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B. The "shape of A" in this invention refers to the shape of the orthographic projection of A onto the substrate. The "size of A" refers to the area of ​​the orthographic projection of A onto the substrate.

[0046] Electrostatic discharge (ESD) is a persistent defect in the display technology field. Static electricity is generated when objects of different materials come into contact and then separate, resulting in electron transfer and both becoming charged. When a display panel becomes charged upon contact with a device, the conductive layers in the panel's circuitry generate induced charges, creating a potential difference between the layers. When this potential difference exceeds the layer's tolerance, damage or even breakdown can occur. Within a display panel, ESD damage can take many forms, such as metal layers damaging semiconductor layers, metal and semiconductor layers damaging the insulating layer between them, and adjacent metal layers damaging the insulating layer between them. ESD damage to display panels manifests in various ways, and is often irreversible. Defects caused by ESD mainly include poor line and dot defects, abnormal display, and growing dark spots (GDS) resulting from reliability testing. Furthermore, because the detection of ESD-related defects is often delayed, they are frequently only discovered during the electrical testing (ET) stage, potentially leading to significant losses. With the continuous development of display technology, the proportion of defects caused by ESD in display products is getting higher and higher. How to reduce display defects caused by ESD is an urgent problem to be solved.

[0047] This embodiment provides a display panel and a display device that can improve the ESD resistance of the display panel.

[0048] This embodiment provides a display panel, including: a substrate, multiple data lines, multiple first power lines, multiple sub-pixels, and multiple compensation structures disposed on the substrate. The substrate includes a display area and a border area located on at least one side of the display area. The multiple data lines, multiple first power lines, and multiple sub-pixels are located in the display area; the multiple data lines and the multiple sub-pixels are connected and configured to provide data signals to the multiple sub-pixels, and the multiple first power lines are connected to the multiple sub-pixels and configured to provide first power signals to the multiple sub-pixels. The multiple compensation structures are located in the border area, and each compensation structure includes: a first compensation block and a second compensation block located in different conductive layers; the first compensation block is connected to the data lines through a first adapter electrode, and the second compensation block is connected to the first power lines through a second adapter electrode; the film layers containing the first adapter electrode, the second adapter electrode, the data lines, and the first power lines are located on the side of the film layer containing the compensation structures away from the substrate.

[0049] The display panel provided in this embodiment improves the compensation structure, thereby reducing the discharge capacity of the compensation structure, thus reducing the possibility of ESD generation, preventing the static electricity released by the compensation structure from damaging other film layers, and thus improving the ESD resistance of the display panel.

[0050] In some exemplary embodiments, the first compensation block may have a first main block and a first connecting segment, and the second compensation block may have a second main block and a second connecting segment; the size of the first connecting segment is smaller than the size of the first main block, and the size of the second connecting segment is smaller than the size of the second main block; the orthographic projection of the first main block on the substrate and the orthographic projection of the second main block on the substrate at least partially overlap, the first connecting segment is connected to the data line through a first adapter electrode, and the second connecting segment is connected to the first power line through a second adapter electrode.

[0051] In some exemplary embodiments, the compensation structure may further include: a third compensation block located on the side of the first compensation block away from the substrate; the third compensation block has a third main block and a third connecting segment, the size of the third connecting segment being smaller than the size of the third main block. The orthographic projection of the third main block onto the substrate at least partially overlaps with the orthographic projection of the first main block onto the substrate, and the third connecting segment of the third compensation block is connected to the second connecting segment of the second compensation block via a second transition electrode. In some examples, the second compensation block may be located on the first gate metal layer, the first compensation block may be located on the second gate metal layer, and the third compensation block may be located on the third gate metal layer. The compensation structure in this example is connected to the data line via a first transition circuit and to the first power line via a second transition electrode. Moreover, the film layers containing the first transition electrode, the second transition electrode, the data line, and the first power line are all located on the side of the film layer containing the compensation structure away from the substrate, which can prevent the static electricity released by the compensation structure from damaging other film layers (e.g., semiconductor layers).

[0052] In some exemplary embodiments, the second connecting segment of the second compensation block of at least one of the multiple compensation structures can be a serpentine winding. Here, a serpentine winding is a bent curve. For example, one end of the trace extends a distance in one direction, then bends and extends a distance in the opposite direction, then bends and extends in the same direction again, repeating this bending and twisting several times to form a serpentine winding. This example can reduce the tip discharge capability at the end of the second connecting segment by adding multiple sharp bends, thereby reducing the possibility of ESD generation.

[0053] In some exemplary embodiments, the minimum width of the end of the second connection segment of the second compensation block of at least one of the plurality of compensation structures can be greater than or equal to 3 micrometers. This example can avoid the formation of tip discharge at the end of the second connection segment, and can disrupt the tip discharge environment between the second connection segment and the remaining film layers (such as semiconductor layers), thereby reducing the likelihood of ESD generation.

[0054] In some exemplary embodiments, at least one of the plurality of sub-pixels may include a pixel circuit and a light-emitting element. The pixel circuit is connected to the light-emitting element and includes at least a driving transistor and a threshold compensation transistor. The first terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor. The active layer of the threshold compensation transistor includes a first channel region, a second channel region, and a conductive region connected between the first channel region and the second channel region. The orthographic projection of the second connection segment of the second compensation block onto the substrate and the orthographic projection of the conductive region of the active layer of the threshold compensation transistor onto the substrate may at least partially overlap. In some examples, the first compensation block may be located on the side of the second compensation block closer to the substrate. In this example, the second compensation block may be configured to protect the channel region of the threshold compensation transistor from interference and may shield other signals (such as data voltage transitions) from affecting the threshold compensation transistor, thereby avoiding affecting the normal operation of the pixel circuit and improving the display effect.

[0055] In some exemplary embodiments, the display panel may further include a first bezel power line located in the bezel area, with a chamfer formed at any corner of the first bezel power line. The first bezel power line may employ a smooth transition design, wherein the first bezel power line may include a plurality of sequentially connected line segments, at least two adjacent line segments having different line widths, and the included angle between adjacent line segments forming an obtuse angle rather than an acute or right angle. The design of this example can avoid the accumulation of charge at sharp points on the first bezel power line, which can help reduce the occurrence of ESD.

[0056] In some exemplary embodiments, the display panel may further include a second bezel power line located in the bezel area, the second bezel power line being located on the side of the first bezel power line away from the display area, and a chamfer being formed at any corner of the second bezel power line. The first bezel power line may be configured to transmit a first power signal, and the second bezel power line may be configured to transmit a second power signal, wherein the first power signal may be greater than the second power signal. The second bezel power line in this example may employ a smooth transition design, wherein the second bezel power line may include multiple line segments connected sequentially, at least two adjacent line segments having different line widths, and the included angle between adjacent line segments forming an obtuse angle rather than an acute or right angle. This design in this example can avoid the formation of sharp points on the second bezel power line that could accumulate charge, which can help reduce the occurrence of ESD.

[0057] In some exemplary embodiments, the display panel may further include a bottom shielding metal layer located on the side of a plurality of sub-pixels near the substrate. The bottom shielding metal layer may include a first structure located in the display area and a second structure located in the bezel area, the first structure and the second structure being connected to form a mesh structure, the second structure surrounding the display area. The mesh structure of the bottom shielding metal layer in this example has an ESD dispersion effect, providing electrostatic protection for the pixel circuitry of the display area.

[0058] In some exemplary embodiments, the display panel may further include a composite insulating layer located on the side of the bottom shielding metal layer away from the substrate and a plurality of auxiliary semiconductor blocks. The composite insulating layer has a plurality of auxiliary vias in the bezel region, the plurality of auxiliary vias being configured to expose the surfaces of the corresponding auxiliary semiconductor blocks. The orthographic projections of the plurality of auxiliary vias and the plurality of auxiliary semiconductor blocks onto the substrate do not overlap with the orthographic projection of the second structure onto the substrate. This example, by providing a plurality of auxiliary vias and a plurality of auxiliary semiconductor blocks in the bezel region, ensures the uniformity of the etching environment between the bezel region and the display region. By ensuring that the orthographic projections of the auxiliary vias and the auxiliary semiconductor blocks onto the substrate do not overlap with the orthographic projection of the second structure onto the substrate, it avoids the formation of an electric field breakdown due to accumulated charges between the auxiliary vias and the second structure, effectively preventing ESD between the bottom shielding metal layer and the auxiliary semiconductor blocks.

[0059] In some exemplary embodiments, the display panel may further include: a plurality of connecting lines located in the bezel region, wherein the orthographic projection of the plurality of connecting lines onto the substrate overlaps with the orthographic projection of the second structure onto the substrate, and a plurality of inorganic insulating layers are disposed between the film layer containing the plurality of connecting lines and the second structure. In some examples, the plurality of connecting lines may be located in the source / drain metal layer. This example can effectively improve ESD by increasing the distance between the second structure and the overlapping connecting lines in a direction perpendicular to the substrate.

[0060] In some exemplary embodiments, the display panel may further include: panel crack detection (PCD) traces located in the bezel area; the panel crack detection traces include: at least two detection segments connected in sequence, the detection segments being serpentine loops. In some examples, the panel crack detection traces may further include: detection connection segments, the detection connection segments connecting two adjacent detection segments, the film layer containing the detection connection segments being located on the side of the film layer containing the detection segments away from the substrate. This example can avoid ESD generation by the panel crack detection traces.

[0061] The following examples illustrate the solution of this embodiment.

[0062] Figure 1 This is a schematic diagram of a display panel provided in at least one embodiment of the present invention. Figure 1 The image shows the display panel in its unbent state. In some examples, such as... Figure 1 As shown, the display panel may include a display area AA and a border area BB surrounding the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. The first border area B1 may be located on one side of the display area AA along a first direction D1. The first border area B1 may be connected to the second border area B2. For example, the first border area B1 may be the bottom border area of ​​the display panel; the second border area B2 may include the left border area, the right border area, and the top border area of ​​the display panel.

[0063] In some examples, such as Figure 1 As shown, the display area AA can be a flat area comprising multiple sub-pixels PX that make up a pixel array. These sub-pixels PX can be configured to display moving or still images. The display area AA can be referred to as the active area. In some examples, the display area AA can be circular or elliptical. However, this embodiment is not limited to this. For example, the display area can be rectangular or other shapes. In some examples, the display panel can be a flexible panel, and therefore the display panel can be deformable, such as rolling, bending, folding, or curling up.

[0064] In some examples, the display area AA may include multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a second direction D2, and the multiple data lines DL may extend along a first direction D1. The orthographic projections of the multiple gate lines GL and the multiple data lines DL onto the substrate may intersect to form multiple sub-pixel regions. A sub-pixel PX may be disposed within one sub-pixel region. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals or test data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide pixel control signals to the multiple sub-pixels PX. For example, the pixel control signals may include scan signals, or may include scan signals and emission control signals, or may include scan signals, reset control signals, and emission control signals. In some examples, the second border area B2 may be provided with multiple gate driving circuits, which may be connected to the multiple gate lines GL and configured to provide pixel control signals.

[0065] In some examples, such as Figure 1As shown, the second direction D2 can be the extension direction of the grid line GL in the display area AA (e.g., the row direction), and the first direction D1 can be the extension direction of the data line DL in the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 can be parallel to the plane of the substrate and intersect each other, for example, they can be perpendicular to each other.

[0066] In some examples, a pixel unit of the display area AA may include three sub-pixels, which may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For example, a pixel unit may include four sub-pixels, which may include one sub-pixel emitting red light, one sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0067] In some examples, a sub-pixel PX may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel, and improves the product yield.

[0068] In some examples, the shape of the light-emitting element of the sub-pixel PX can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0069] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0070] In some examples, such as Figure 1 As shown, the first border region B1 may include a first sub-region B11, a bent region B12, and a second sub-region B13 sequentially arranged along the first direction D1. The first sub-region B11 is connected to the second border region B2, and the bent region B12 is connected between the first sub-region B11 and the second sub-region B13. The bent region B12 may be configured to bend the second sub-region B13 to the back of the display region AA. The second sub-region B13 may include a signal access region B131. The signal access region B131 may be configured to be bonded to an external circuit board.

[0071] Figure 2 This is an equivalent circuit diagram of the pixel circuit of at least one embodiment of the present invention. In some examples, such as... Figure 2 As shown, the pixel circuit may include eight transistors (e.g., first transistor T1 to eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be called the first reset transistor, the second transistor T2 may also be called the threshold compensation transistor, the third transistor T3 may also be called the driving transistor, the fourth transistor T4 may also be called the data writing transistor, the fifth transistor T5 may also be called the first light-emitting control transistor, the sixth transistor T6 may also be called the second light-emitting control transistor, the seventh transistor T7 may also be called the second reset transistor, and the eighth transistor T8 may also be called the third reset transistor.

[0072] In some examples, the first transistor T1, the third transistor T3 through the eighth transistor T4 can be type I transistors, such as P-type transistors, and the second transistor T2 can be type II transistors, such as N-type transistors. The type I transistors can also be low-temperature polycrystalline silicon thin-film transistors, and the type II transistors can also be oxide thin-film transistors.

[0073] In some examples, such as Figure 2 As shown, the pixel circuit can be electrically connected to the first scan line GL1, the second scan line GL2, the data line DL, the first power line VDD, the light emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the first reset control line RST1, and the second reset control line RST2. The first electrode (e.g., the anode) of the light-emitting element EL can be electrically connected to the pixel circuit, and the second electrode (e.g., the cathode) can be electrically connected to the second power line VSS.

[0074] In some examples, the first power line VDD can be configured to provide a constant first power signal Vdd to the pixel circuit, and the second power line VSS can be configured to provide a constant second power signal Vss, wherein the first power signal Vdd is greater than the second power signal Vss. The first scan line GL1 can be configured to provide a first scan signal to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The light emission control line EML can be configured to provide a light emission control signal to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal to the pixel circuit. The second reset control line RST2 can be configured to provide a second reset control signal to the pixel circuit.

[0075] In some examples, such as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the second pixel node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the second terminal of the second transistor T2 is electrically connected to the first node N1, and the first terminal of the second transistor T2 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the light emission control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the light emission control line EML, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line VDD.

[0076] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3; the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light-emitting element EL.

[0077] Figure 3 This is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present invention. Figure 3The diagram illustrates the structure of a sub-pixel in display area AA. In this example, the pixel circuitry includes both low-temperature polysilicon thin-film transistors (LTPTs) and oxide thin-film transistors (OTFTs). The pixel circuitry in this example... Figure 2 The pixel circuit shown is an example.

[0078] In some examples, such as Figure 3 As shown, in a direction perpendicular to the display panel, the display area of ​​the display panel may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially disposed on the substrate 10. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, and the pixel circuit for each sub-pixel may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.

[0079] In some examples, Figure 3 The illustration uses an example where each sub-pixel includes a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor, and the second-type transistor 22 can be an oxide thin-film transistor. The capacitor 23 can be the aforementioned storage capacitor, the first-type transistor 21 can be the aforementioned sixth or seventh transistor, and the second-type transistor 22 can be the aforementioned second transistor.

[0080] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarization layer) may be disposed between the first source / drain metal layer and the second source / drain metal layer, wherein the seventh insulating layer 107 may be located on the side of the sixth insulating layer 106 away from the substrate 10; and an eighth insulating layer 108 (also referred to as a second planarization layer) may be disposed on the side of the second source / drain metal layer away from the substrate 10. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 can be inorganic insulating layers, while the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, a buffer layer can also be provided on the side of the first semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating the interior of the display panel and can also increase the adhesion of the film layers in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can also be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistors in the pixel circuit to avoid external light affecting the performance of the transistors. In other examples, the sixth insulating layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the seventh insulating layer can be provided between the first source / drain metal layer and the second source / drain metal layer.

[0081] In some examples, such as Figure 3As shown, the first semiconductor layer of the display area may include at least: a first active layer 210 of a first type transistor 21. The first active layer 210 of the first type transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first type transistor 21, and a first electrode 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first type transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 onto the substrate 10. The second gate metal layer may include at least: a second electrode 232 of the capacitor 23, and a third gate 224 of the second type transistor 22. The orthographic projections of the second electrode 232 and the first electrode 231 of the capacitor 23 onto the substrate 10 may at least partially overlap, for example, they may coincide. The second semiconductor layer may include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer may include at least: a second gate 223 of the second type transistor 22. The orthographic projection of the second gate 223 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The orthographic projection of the third gate 224 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The third gate 224 may be the bottom gate of the second type transistor 22, and the second gate 223 may be the top gate of the second type transistor 22.

[0082] In some examples, such as Figure 3As shown, the first source-drain metal layer of the display area may include at least: a first source 211 and a first drain 212 of a first type transistor 21, and a second source 221 and a second drain 222 of a second type transistor 22. The fifth insulating layer 105 may have multiple pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104, and the third insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least a portion of the surface at both ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer may include at least an anode transition electrode 241. The anode transition electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 in the pixel circuit through a fifth pixel via formed by the sixth insulating layer 106 and the seventh insulating layer 107. This example demonstrates the electrical connection between the pixel circuitry and the light-emitting element via the anode adapter electrode 241.

[0083] In some examples, the gate lines of the display area (e.g., including a first scan line, a second scan line, an emission control line, a first reset control line, and a second reset control line) may be located, for example, in the first gate metal layer and the third gate metal layer, and the data lines and the first power lines of the display area may be located, for example, in the second source-drain metal layer. This embodiment is not limited in this respect. In other examples, the circuit structure layer of the display area may further include a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate.

[0084] In some examples, such as Figure 3As shown, the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on an eighth insulating layer 108 and electrically connected to an anode adapter electrode 241 through a sixth pixel via formed in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0085] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0086] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0087] In some examples, such as Figure 3 As shown, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display panel and relieve stress on the first encapsulation layer 141 and the third encapsulation layer 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0088] In some examples, the touch structure layer 15 may include: a touch barrier layer (TBL), a first touch conductive layer (TMA), a touch interlayer insulating layer (TLD), a second touch conductive layer (TMB), and a touch protective layer, sequentially disposed. For example, the first touch conductive layer may include multiple first touch electrodes, multiple second touch electrodes, and multiple first connecting portions; the multiple first touch electrodes, multiple second touch electrodes, and multiple first connecting portions may be formed in the same patterning process, and the first touch electrodes and first connecting portions may be an integral structure interconnected with each other. The second touch conductive layer may include multiple second connecting portions; the second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. In other examples, the first touch conductive layer may include multiple second connecting portions; the second touch conductive layer may include multiple first touch electrodes, multiple second touch electrodes, and multiple first connecting portions. This embodiment is not limited in this respect.

[0089] In some examples, the first touch electrode can be a driving (Tx) electrode and the second touch electrode can be a sensing (Rx) electrode. Alternatively, the first touch electrode can be a sensing (Rx) electrode and the second touch electrode can be a driving (Tx) electrode.

[0090] In some examples, the touch barrier layer and the touch insulating layer can be inorganic insulating layers. For example, the insulating layer between the touch barrier layer and the touch layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or composite layers. The touch protective layer can be an organic insulating layer. The first touch conductive layer and the second touch conductive layer can be made of any one or more of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, ITO / Ag / ITO, etc. In other examples, the touch barrier layer and the touch insulating layer can be organic insulating layers.

[0091] Figure 4 This is an example diagram illustrating the configuration of the gate drive circuit according to at least one embodiment of the present invention. In some examples, such as... Figure 1 and Figure 4 As shown, the second bezel area B2 of the display panel can be equipped with multiple gate driving circuits. These multiple gate driving circuits can be electrically connected to multiple sub-pixels PX within the display area AA via multiple gate lines. The multiple gate driving circuits can be configured to provide various pixel control signals to the multiple sub-pixels PX. In some examples, using... Figure 2Taking the pixel circuit shown as an example, various pixel control signals may include: a first scan signal, a second scan signal, an emissive control signal, a first reset control signal, and a second reset control signal.

[0092] In some examples, multiple gate driving circuits may include: a first scan driving circuit 431, a second scan driving circuit 432, a light-emitting driving circuit 433, a first reset driving circuit 434, and a second reset driving circuit 435. The first scan driving circuit 431 may be configured to provide a first scan signal to the multi-row pixel circuit of the display area AA. The second scan driving circuit 432 may be configured to provide a second scan signal to the multi-row pixel circuit of the display area AA. The light-emitting driving circuit 433 may be configured to provide a light-emitting control signal to the multi-row pixel circuit of the display area AA. The first reset driving circuit 434 may be configured to provide a first reset control signal to the multi-row pixel circuit of the display area AA. The second reset driving circuit 435 may be configured to provide a second reset control signal to the multi-row pixel circuit of the display area AA. Each gate driving circuit may include multiple cascaded driving units.

[0093] In some examples, the multiple gate driving circuits may include: a first group of gate driving circuits and a second group of gate driving circuits; the first group of gate driving circuits may be located in the left frame region of the second frame region B2, and the second group of gate driving circuits may be located in the right frame region of the second frame region B2. In some examples, the first group of gate driving circuits may include the following three gate driving circuits: a light-emitting driving circuit 433, a first reset driving circuit 434, and a second scan driving circuit 432; the second group of gate driving circuits may include the following two gate driving circuits: a first scan driving circuit 431 and a second reset driving circuit 435. For example, in the left frame region of the second frame region B2, the light-emitting driving circuit 433, the second reset driving circuit 434, and the second scan driving circuit 432 may be sequentially arranged along the direction closer to the display area AA in the second direction D2; in the right frame region of the second frame region B2, the first scan driving circuit 431 and the second reset driving circuit 435 may be sequentially arranged along the direction away from the display area AA in the second direction D2. However, this embodiment is not limited in this respect.

[0094] In some examples, the first scan driving circuit 431 may include multiple cascaded first scan driving units (e.g., GP(1) to GP(4)). Each stage of the first scan driving unit may be configured to provide a first scan signal to a row of pixel circuits in the display area AA. For example, the first stage of the first scan driving unit GP(1) may be configured to provide a first scan signal to the first row of pixel circuits in the display area AA.

[0095] In some examples, the second scan driving circuit 432 may include multiple cascaded second scan driving units (e.g., GN(1) to GN(4)). Each stage of the second scan driving unit may be configured to provide a second scan signal to at least one row of pixel circuitry in the display area AA. For example, the first stage of the second scan driving unit GN(1) may be configured to provide a second scan signal to the first row or the first and second rows of pixel circuitry in the display area AA.

[0096] In some examples, the light-emitting driving circuit 433 may include multiple cascaded light-emitting driving units (e.g., EM(1) to EM(4)). Each stage of the light-emitting driving unit may be configured to provide a light-emitting control signal to at least one row of pixel circuits in the display area AA. For example, the first stage of the light-emitting driving unit EM(1) may be configured to provide a light-emitting control signal to the first row or the first and second rows of pixel circuits in the display area AA.

[0097] In some examples, the first reset drive circuit 434 may include multiple cascaded first reset drive units (e.g., RP(1) to RP(4)). Each first reset drive unit may be configured to provide a first reset control signal to at least one row of pixel circuitry in the display area AA. For example, the first-stage first reset drive unit RP(1) may be configured to provide a first reset control signal to the first row or the first and second rows of pixel circuitry in the display area AA.

[0098] In some examples, the second reset drive circuit 435 may include multiple cascaded second reset drive units (e.g., RH(1) to RH(4)). Each stage of the second reset drive unit may be configured to provide a second reset control signal to at least one row of pixel circuits in the display area AA. For example, the first stage of the second reset drive unit RH(1) may be configured to provide a second reset control signal to the first row or the first and second rows of pixel circuits in the display area AA.

[0099] Figure 5 for Figure 1 A schematic diagram of the local structure of region S1. In some examples, such as... Figure 5 As shown, the multiple pixel circuits 41 of the display area AA can be arranged in an array along the first direction D1 and the second direction D2. Multiple pixel circuits 41 aligned along the first direction D1 form a column of pixel circuits, and multiple pixel circuits 41 aligned along the second direction D2 form a row of pixel circuits. Since the display area in this example is circular or elliptical, the multiple rows of pixel circuits can be arranged in a stepped pattern at the edge of the display area.

[0100] In some examples, such as Figure 5As shown, a row of pixel circuitry can be connected to a set of signal lines extending along the second direction D2 (including a first reset control line RST1, a second reset control line RST2, a first scan line GL1, a second scan line GL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, and a third initial signal line INIT3). At least a portion of the set of signal lines can extend to the left border region of the second border region B2 and be connected to multiple connecting lines (e.g., including first connecting lines 511 to sixth connecting lines 516). Specifically, the first reset control line RST1 can be connected to the first connecting line 511; the second initial signal line INIT2 can be connected to the second connecting line 512; the first initial signal line INIT1 can be connected to the third connecting line 513; the third initial signal line INIT3 can be connected to the fourth connecting line 514; the emission control line EML can be connected to the fifth connecting line 515; and the second scan line GL2 can be connected to the sixth connecting line 616.

[0101] In some examples, such as Figure 5 As shown, each column of pixel circuits can be connected to one data line DL and one first power line VDD. The data line DL and the first power line VDD can extend along a first direction D1. The data line DL and the first power line VDD connected to the same column of pixel circuits can be adjacent along a second direction D2. For example, multiple data lines DL and multiple first power lines VDD can be alternately arranged along the second direction D2.

[0102] In some examples, the edge of the display area AA has an arc or corner area, the number of pixel circuits 41 in the multiple columns of pixel circuits near the edge of the display area AA is different, and the number of pixel circuits 41 connected to each data line DL is different, so that the load of the multiple data lines DL near the edge of the display area AA is different from the load of the multiple data lines DL located in the middle of the display area AA. Therefore, multiple compensation structures 31 are set in the second border area B2 to compensate the load of the multiple data lines DL at the edge of the display area AA.

[0103] In some examples, such as Figure 5 As shown, multiple compensation structures 31 are located in the second border region B2 and are arranged adjacent to the pixel circuit 41. Multiple compensation structures 31 aligned along the first direction D1 form a column of compensation structures, while multiple compensation structures 31 aligned along the second direction D2 can form a row of compensation structures. Each column of pixel circuits can be connected to at least one compensation structure 31; for example, a column of pixel circuits can be connected to one or more compensation structures.

[0104] Figure 6 for Figure 1 A schematic diagram of a local membrane layer in the central region S1. Figure 6The diagram mainly illustrates the connection positions of the compensation structure 31 with the data line DL and the first power line VDD. Figure 6 The three compensation structures 31 arranged along the second direction D2 are illustrated as an example. Figure 6 The cross-sectional structure of the display area of ​​the display panel shown is as follows: Figure 3 As shown. Figure 7A for Figure 6 A schematic diagram of the first gate metal layer in the diagram; Figure 7B for Figure 6 A schematic diagram of the first and second gate metal layers in the diagram; Figure 7C for Figure 6 A schematic diagram of the first gate metal layer, the second gate metal layer, and the third gate metal layer in the diagram; Figure 7D for Figure 6 A schematic diagram of the first gate metal layer, the second gate metal layer, the third gate metal layer, and the first source / drain metal layer.

[0105] In some examples, such as Figure 6 and Figure 7A As shown, the first gate metal layer of the display panel may include at least: a first reset control line RST1, a second reset control line RST2, an emissive control line EML, a first electrode Cst-1 of the storage capacitor Cst of the pixel circuit, a first scan line GL1, and a second compensation block 312 of the compensation structure 31 located in the second border region B2. The second compensation block 312 may have a second main block 3121 and a second connecting segment 3122. The second main block 3121 and the second connecting segment 3122 are an integral structure, and the second connecting segment 3122 protrudes from the side of the second main block 3121 near the display region AA along the first direction D1. The second main blocks 3121 of multiple second compensation blocks 312 may be an integral structure interconnected with each other. Multiple second connecting segments 3122 may be aligned and arranged along the second direction D2.

[0106] In some examples, such as Figure 6 and Figure 7BAs shown, the second gate metal layer of the display panel may include at least: a second sub-line GL2-2 of the second scan line located in the display area AA, a first initial signal line INIT1, a second electrode Cst-2 of the storage capacitor Cst of the pixel circuit, and a first compensation block 311 of the compensation structure 31 located in the second border area B2. The first compensation blocks 311 of multiple compensation structures 31 may be independently configured. The first compensation block 311 may include: a first main block 3111 and a first connecting segment 3112. The first main block 3111 and the first connecting segment 3112 are an integral structure, with the first connecting segment 3111 protruding along the first direction D1 from the side of the first main block 3111 near the display area AA. The orthographic projection of the first main block 3111 onto the substrate may be located within the orthographic projection range of the second main block 3121 of the second compensation block 312 onto the substrate. The orthographic projections of the first connecting segment 3112 and the second connecting segment 3121 of a compensation structure 31 onto the substrate may be adjacent along the second direction D2, with the first connecting segment 3112 located on the side of the second connecting segment 3121 near the display area AA. The first connecting segment 3112 and the second connecting segment 3121 of the multiple compensation structures 31 can be alternately set along the second direction D2 on the substrate.

[0107] In some examples, such as Figure 6 and Figure 7C As shown, the third gate metal layer of the display panel may include at least: a first sub-line GL2-1 of the second scan line located in the display area AA, a third initial signal line INIT3, and a third compensation block 313 of the compensation structure 31 located in the second border area B3. The third compensation block 313 may include a third main block 3131 and a third connecting segment 3132. The third main block 3131 and the third connecting segment 3132 may be an integral structure. The third connecting segment 3132 may protrude along the first direction D1 from the side of the third main block 3131 near the display area AA. The third main block 3131 of the third compensation blocks 313 of multiple compensation structures 31 may be an integral structure interconnected with each other. The orthographic projection of the third compensation block 313 on the substrate may cover the orthographic projections of the first compensation block 311 and the second compensation block 312 on the substrate. For example, the orthographic projection of the third compensation block 313 on the substrate may coincide with the orthographic projection of the second compensation block 312 on the substrate, and the orthographic projection of the first compensation block 311 on the substrate may be located within the orthographic projection range of the third compensation block 313 on the substrate. The orthographic projection of the third connecting segment 3132 of a compensation structure 31 onto the substrate can be located between the orthographic projections of the first connecting segment 3112 and the second connecting segment 3122 onto the substrate.

[0108] In some examples, such as Figure 6 and Figure 7DAs shown, the first source / drain metal layer of the display panel may include at least: a second initial signal line INIT2 located in the display area AA, and multiple transition electrodes (e.g., a first transition electrode 531 and a second transition electrode 532) located in the second border area B2, as well as multiple border connection electrodes (e.g., a first border connection electrode 521 to a sixth border connection electrode 526). The second transition electrode 532 may be connected to the second connection segment 3122 and the third connection segment 3132 of the compensation structure 31, and the first transition electrode 531 may be connected to the first connection segment 3112 of the compensation structure 31. The first transition electrode 531 and the second transition electrode 532 may be adjacent to each other along the second direction D2.

[0109] In some examples, the first frame connection electrode 521 can be connected to the end of the first reset control line RST1 extending into the second frame region B2; the second frame connection electrode 522 can be connected to the second initial signal line INIT2, for example, the second frame connection electrode 522 and the second initial signal line INIT2 can be an integral structure; the third frame connection electrode 523 can be connected to the end of the first initial signal line INIT1 extending into the second frame region B2; the fourth frame connection electrode 524 can be connected to the end of the third initial signal line INIT3 extending into the second frame region B2; the fifth frame connection electrode 525 can be connected to the end of the light emission control line EML extending into the second frame region B2; and the sixth frame connection electrode 526 can be connected to the end of the first sub-line GL2-1 of the second scan line extending into the second frame region B2 and the end of the second sub-line GL2-2 extending into the second frame region B2. The overlapping portion of the first sub-line GL2-1 of the second scan line with the active layer of the second transistor can serve as the top gate of the second transistor, and the overlapping portion of the second sub-line GL2-2 with the active layer of the second transistor can serve as the bottom gate of the second transistor.

[0110] In some examples, such as Figure 6As shown, the second source-drain metal layer of the display panel may include at least: a data line DL and a first power line VDD located in the display area AA, and multiple connecting lines (e.g., including first connecting line 511 to sixth connecting line 516) located in the second border area B2. The data line DL can be connected to the first connecting segment 3112 of the first compensation block 311 of the compensation structure 31 via the first adapter electrode 531, and the first power line VDD can be connected to the second connecting segment 3122 of the second compensation block 312 and the third connecting segment 3132 of the third compensation block 313 of the compensation structure 31 via the second adapter electrode 532. The first compensation block 311 of the compensation structure 31 can serve as one plate of a capacitor, and the second compensation block 312 and the third compensation block 313 can serve as the other plate of a capacitor. The compensation structure 31 may include a capacitor structure sandwiched between three plates to provide capacitance compensation for the connected data line DL, so that the load of the data line DL at the edge of the display area AA is approximately the same as the load of the data line DL in the middle area.

[0111] In some examples, the end of the first compensation block 311 of the compensation structure 31 away from the display area AA along the first direction D1 can be connected to the test unit to be configured to receive test data signals and provide test data signals to the data line DL during the test phase. The test unit can be located in the second border area B2 and on the side of the compensation structure 31 away from the display area AA.

[0112] In some examples, the first main block 3111, the second main block 3121, and the third main block 3131 of the compensation structure 31 are all bulk metals, and the dimensions of the first connecting segment 3112, the second connecting segment 3122, and the third connecting segment 3132 are all smaller than the dimensions of the corresponding main blocks. Therefore, tip discharge is prone to occur at the connecting segment locations. In this example, the first compensation block 311 of the compensation structure 31 is connected to the data line DL located on the second source-drain metal layer via the first transition electrode 531 located on the first source-drain metal layer. The second compensation block 312 and the third compensation block 313 are connected to the first power line VDD located on the second source-drain metal layer via the second transition electrode 532 located on the first source-drain metal layer, and the connection is made through the first transition electrode 531 and the second transition electrode 532 located on the first source-drain metal layer. Moreover, the orthographic projections of the first compensation block 311, the second compensation block 312, and the third compensation block 313 of the compensation structure 31 onto the substrate do not overlap with the orthographic projections of the first semiconductor layer and the second semiconductor layer of the display area AA onto the substrate. In this way, the distance between the discharge position of the compensation structure 31 and the first and second semiconductor layers of the display area AA can be increased, which can avoid the impact of the tip discharge of the main block with a large area on the semiconductor layer, thereby improving the ESD resistance of the display panel.

[0113] Figure 8This is another equivalent circuit diagram of the pixel circuit of at least one embodiment of the present invention. In some examples, such as... Figure 8 As shown, the pixel circuit may include seven transistors (e.g., first transistor T1 through seventh transistor T7) and a storage capacitor Cst. The seven transistors in this example may be of the same type, such as all being P-type transistors.

[0114] In some examples, such as Figure 8 As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the second pixel node N2. The gate of the second transistor T2 is electrically connected to the first scan line GL1, the second terminal of the second transistor T2 is electrically connected to the first node N1, and the first terminal of the second transistor T2 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the light emission control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the light emission control line EML, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The first transistor T1 can be configured to reset the first node N1. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line VDD. Further descriptions of the pixel circuit in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0115] Figure 9 This is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present invention. The pixel circuit of this example uses... Figure 8 Taking the pixel circuit shown as an example, the multiple transistors in the pixel circuit can be of the same type, for example, they can all be low-temperature polycrystalline silicon thin-film transistors. Figure 9The illustration takes an example where each sub-pixel includes a first-type transistor 21 and a capacitor 23. The capacitor 23 can be the aforementioned storage capacitor, and the first-type transistor 21 can be the aforementioned sixth or seventh transistor.

[0116] In some examples, such as Figure 9 As shown, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 and a seventh insulating layer 107 may be disposed between the first source / drain metal layer and the second source / drain metal layer; and an eighth insulating layer 108 may be disposed on the side of the second source / drain metal layer away from the substrate 10. The seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers, while the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers. The remaining structure of the display area of ​​the display panel in this example can be found in [reference needed]. Figure 3 The description of the illustrated embodiment is omitted here.

[0117] Figure 10 for Figure 1 Another partial schematic diagram of the central region S2. Figure 10 The diagram illustrates the boundary between the compensation structure 31 and the pixel circuit. Figure 10 The following diagram illustrates three compensation structures 31 as an example. Figure 10 The cross-sectional structure of the display panel shown is as follows: Figure 9 As shown. Figure 11A for Figure 10 A schematic diagram of the first semiconductor layer; Figure 11B for Figure 10 A schematic diagram of the first gate metal layer and the first semiconductor layer.

[0118] In some examples, such as Figure 11A and Figure 11BAs shown, the first semiconductor layer of the display panel may include: an active layer of multiple transistors of multiple pixel circuits (e.g., an active layer T10 including the first transistor T1 to the active layer T70 including the seventh transistor T7). The active layers T10 of the first transistor T1, T20 of the second transistor T2, T30 of the third transistor T3, T40 of the fourth transistor T4, T50 of the fifth transistor T5, T60 of the sixth transistor T6, and T70 of the seventh transistor T7 of the pixel circuits can be an integrated structure interconnected. The active layers of multiple transistors of multiple pixel circuits arranged along the first direction D1 can be an integrated structure, wherein the active layer T70 of the seventh transistor T7 of one pixel circuit can be connected to the active layer T10 of the first transistor T1 of the previous row of pixel circuits, and the active layer T10 of the first transistor T1 of one pixel circuit can be connected to the active layer T70 of the seventh transistor T7 of the next row of pixel circuits.

[0119] In some examples, such as Figure 11A and Figure 11B As shown, the active layer T20 of the second transistor T2 may include: a first channel region T201, a second channel region T202, and a conductive region T203 connecting the first channel region T201 and the second channel region T202. For example, the integral structure of the conductive region T203 can be L-shaped when projected onto the substrate.

[0120] In some examples, such as Figure 11A As shown, the first gate metal layer of the display panel may include: multiple signal lines located in the display area AA (such as the first reset control line RST1(i), the second reset control line RST2(i), the light emission control line EML, and the first scan line GL1), the first electrode Cst-1 of the storage capacitor of the pixel circuit, and the first compensation block 311 of multiple compensation structures 31 located in the second border area B2. The first reset control line RST1(i), the second reset control line RST2(i), the light emission control line EML, and the first scan line GL1 may all extend along the second direction D2. The first reset control line RST1(i) connected to the pixel circuit of the i-th row may also serve as the second reset control line connected to the pixel circuit of the (i+1)-th row, where i is a positive integer.

[0121] In some examples, such as Figure 10As shown, the second gate metal layer of the display panel may include: a second electrode Cst-2 of the storage capacitor of the pixel circuit located in the display area AA, a first shielding electrode 421 and a second shielding electrode 422, and a second compensation block 312 of a plurality of compensation structures 31 located in the second border area B2. The orthographic projections of the first shielding electrode 421 and the second shielding electrode 422 onto the substrate may overlap with the orthographic projections of the conductor region of the corresponding second transistor of the pixel circuit onto the substrate. The first shielding electrode 421 may be independently disposed and connected to a first power line; the second shielding electrode 422 may be connected to the second electrode of the storage capacitor of the pixel circuit. In this example, the first shielding electrode 421 and the second shielding electrode 422 are configured to receive a first power signal.

[0122] In some examples, such as Figure 10 and Figure 11B As shown, the compensation structure 31 may include a first compensation block 311 located in the first gate metal layer and a second compensation block 312 located in the second gate metal layer. The first compensation block 311 may have a first main block 3111 and a first connecting segment 3112; the second compensation block 312 may have a second main block 3121 and a second connecting segment 3122. The orthographic projection of the first main block 3111 onto the substrate is within the orthographic projection range of the second main block 3121 onto the substrate. The second compensation blocks 312 of the plurality of compensation structures 31 may be an integral structure interconnected with each other. The first connecting segment 3112 of the first compensation block 311 may be connected to a data line; the second connecting segment 3122 of the second compensation block 312 may be connected to a first power line. The data line and the first power line may be located in the first source / drain metal layer or the second source / drain metal layer. For example, the first connection segment can be connected to the data line located in the second source-drain metal layer through the first transition electrode located in the first source-drain metal layer, and the second connection segment can be connected to the first power line located in the second source-drain metal layer through the second transition electrode located in the first source-drain metal layer; or, for example, the first connection segment can be directly connected to the data line located in the first source-drain metal layer, and the second connection segment can be directly connected to the first power line located in the first source-drain metal layer.

[0123] In some examples, such as Figure 10 and Figure 11BAs shown, the orthographic projection of the second connection segment 3122 of the second compensation block 312 closest to the display area AA among the plurality of compensation structures 31 arranged along the second direction D2 on the substrate can be L-shaped. This second connection segment 3122 may include: a first sub-segment 31221 extending along the first direction D1 and a second sub-segment 31222 extending along the second direction D2. The second sub-segment 31222 is the end of the second connection terminal 3122. The second sub-segment 31222 can extend to the display area AA, and the orthographic projection of the second sub-segment 31222 on the substrate may partially overlap with the orthographic projection of the first semiconductor layer of the display area on the substrate. The orthographic projection of the second sub-segment 31222 on the substrate may overlap with the orthographic projection of the conductive region T203 of the active layer T20 of the second transistor T2 on the substrate. The second connection segment 3122 of the second compensation block 312 can serve as a shielding electrode for the conductive region T203 of the second transistor in the pixel circuit at the edge of the display area. The shielding electrode in this example can be configured to protect the channel region of the second transistor from interference. It can shield other signals (such as data voltage transitions) from affecting the potential of the second transistor, thereby avoiding affecting the normal operation of the pixel circuit and improving the display effect.

[0124] In some examples, such as Figure 10 As shown, the minimum width L1 of the second sub-segment 31222 of the second connecting segment 3122 of the compensation structure 31 can be greater than the minimum width of the first sub-segment 31222. For example, the minimum width L1 of the second sub-segment 31222 can be greater than or equal to 3 micrometers, such as approximately 8 micrometers. In this example, the width of the line segment refers to the length of the trace in a plane parallel to the substrate, in a direction perpendicular to the trace extension direction.

[0125] In this example, the end of the second connection segment overlaps with the orthographic projection of the conductor region of the second transistor onto the substrate, and the width of the end of the second connection segment is greater than or equal to 3 micrometers. This can prevent the formation of tip discharge at the end of the second connection segment and can disrupt the tip discharge environment between the second connection segment and the first semiconductor layer, thereby reducing the possibility of ESD generation.

[0126] Figure 12 for Figure 1 Another partial schematic diagram of the central region S1. Figure 12 The diagram illustrates the boundary between the compensation structure 31 and the pixel circuit. Figure 12 The following diagram illustrates three compensation structures 31 as an example. Figure 12 The cross-sectional structure of the display panel shown can be as follows: Figure 9 As shown.

[0127] In some examples, such as Figure 12As shown, the compensation structure 31 may include a first compensation block 311 located in the first gate metal layer and a second compensation block 312 located in the second gate metal layer. The first compensation block 311 may have a first main block 3111 and a first connecting segment 3112; the second compensation block 312 may have a second main block 3121 and a second connecting segment 3122. The second compensation blocks 312 of the multiple compensation structures 31 may be an integral structure interconnected with each other. The first connecting segment 3112 of the first compensation block 311 may be connected to a data line; the second connecting segment 3122 of the second compensation block 312 may be connected to a first power line. The second connecting segment 3122 of the second compensation block 312 may be a serpentine winding.

[0128] In this example, the second connection segment of the second connection segment overlaps with the conductive region of the second transistor in the orthographic projection onto the substrate. Furthermore, the second connection segment of the second compensation block employs a serpentine winding design with multiple sharp bends, which reduces the tip discharge capability at the end of the second connection segment. Moreover, the serpentine winding has multiple segments extending in different directions, increasing the density of the second connection segment and disrupting the tip discharge environment between the second connection segment and the first semiconductor layer, thereby reducing the likelihood of ESD generation. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0129] In some examples, such as Figure 1 As shown, the display panel may further include: a first bezel power line 45 and a second bezel power line 46 located in the bezel area BB, wherein the second bezel power line 46 may be located on the side of the first bezel power line 45 away from the display area AA. The first bezel power line 45 may be configured to transmit a first power signal and may be connected to the first power line of the display area. The second bezel power line 46 may be configured to transmit a second power signal and may be connected to the second electrode of the light-emitting element in the display area.

[0130] In some examples, such as Figure 1 As shown, the first frame power line 45 can extend from the first sub-region B11 of the first frame region B1 to the left and right frame regions of the second frame region B2. The first frame power line 45 can extend to the corners of the left and right frame regions, or it can be connected into a single structure in the second frame region B2, forming a loop around the display area AA. The second frame power line 46 can be connected into a single structure in the second frame region B2 and extend from the left and right frame regions to the first sub-region B11, respectively. The first frame power line 45 and the second frame power line 46 can be connected to the contact pads that transmit corresponding signals within the signal access area B131.

[0131] Figure 13 for Figure 1A schematic diagram of the local structure of region S2. In some examples, such as... Figure 1 and Figure 13 As shown, at the corner of the border area B2 (e.g., where a straight edge turns into a corner), the first border power line 45 and the second border power line 46 may transition from narrow to wide or from wide to narrow. The first border power line 45 can employ a smooth transition design. Specifically, a chamfer is formed at any corner of the first border power line 45. For example, the first border power line 45 may include multiple sequentially connected line segments, at least two adjacent line segments may have different line widths, and the included angle between adjacent line segments may form an obtuse angle. The length of the chamfer of the first border power line 45 can be greater than or equal to 1 micrometer.

[0132] In some examples, such as Figure 13 As shown, the second frame power line 46 can adopt a smooth transition design. Specifically, a chamfer is formed at any corner of the second frame power line 46. For example, the second frame power line 46 can include multiple line segments connected sequentially, at least two adjacent line segments can have different line widths, and the included angle between adjacent line segments can form an obtuse angle. The length of the chamfer of the second frame power line 46 can be greater than or equal to 1 micrometer.

[0133] This example demonstrates how a smooth transition design for the first border power line 45 and the second border power line 46 can reduce charge accumulation caused by sharp points during the transition between thick and thin traces, as well as the resulting electrostatic discharge.

[0134] Figure 14 for Figure 1 A schematic diagram of the local structure of region S3. In some examples, such as... Figure 14 As shown, the display panel may further include a bottom shielding metal layer 48. The bottom shielding metal layer 48 may be located on the side of the plurality of pixel circuits 41 near the substrate. The bottom shielding metal layer 48 may include a first structure 481 located in the display area AA and a second structure 482 located in the bezel area. The first structure 481 and the second structure 482 may be connected to form a mesh structure, and the second structure 482 may surround the display area AA. For example, the second structure 482 may be a ring shape surrounding the display area AA. The second structure 428 may be located on the side of the gate driving circuit 43 near the display area AA. The orthographic projection of the first structure 481 in the display area AA onto the substrate may overlap with the orthographic projection of the active layer of the plurality of transistors of the pixel circuit 41 onto the substrate, for example, it may overlap with the orthographic projection of the active layer of the first type of transistor of the pixel circuit 41 onto the substrate. The bottom shielding metal layer configured in this example can have a dispersing effect on electrostatic discharge and can provide a certain electrostatic protection for the pixel circuits in the display area.

[0135] In some examples, such as Figure 14As shown, the display panel may further include: a composite insulating layer located on the side of the bottom shielding metal layer 48 away from the substrate, and a plurality of auxiliary semiconductor blocks 501. The composite insulating layer may have a plurality of auxiliary vias 500 in the second frame region B2, and the plurality of auxiliary vias 500 and the plurality of auxiliary semiconductor blocks 501 may correspond one-to-one; the auxiliary vias 500 may be configured to expose the surface of the corresponding auxiliary semiconductor block 501. The plurality of auxiliary semiconductor blocks 501 may be disposed on the same layer as the first semiconductor layer of the display area; in such a way... Figure 3 In the cross-sectional structure shown, the composite insulating layer may include: a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, and a fifth insulating layer 105 stacked sequentially; in such a way... Figure 9 In the cross-sectional structure shown, the composite insulating layer may include a first insulating layer 101, a second insulating layer 102, and a third insulating layer 103 stacked sequentially. This example, by providing multiple auxiliary semiconductor blocks and multiple auxiliary vias in the bezel area, helps to ensure the uniformity of the etching environment between the display area and the bezel area.

[0136] In some examples, such as Figure 14 As shown, the orthographic projections of the multiple auxiliary vias 500 and multiple auxiliary semiconductor blocks 501 onto the substrate and the orthographic projections of the second structure 482 of the bottom shielding metal layer 48 onto the substrate may not overlap. In other words, auxiliary semiconductor blocks and auxiliary vias may not be provided on the second structure 482. In this example, the locations of the auxiliary semiconductor blocks and auxiliary vias avoid the location of the second structure 482 of the bottom shielding metal layer, which can prevent the charge accumulated in the second structure 482 from forming an electric field breakdown with the auxiliary vias 500, and can effectively avoid ESD between the bottom shielding metal layer 48 and the first semiconductor layer.

[0137] In some examples, such as Figure 14 As shown, the second frame region B2 can be provided with multiple gate driving circuits 43, and each gate driving circuit 43 can include multiple cascaded driving units. Multiple gate lines (such as gate line 471) in the display region AA can be connected to the output terminals of the corresponding driving units of the gate driving circuit 43 via connecting lines (such as connecting lines 517 or 518). The orthographic projections of connecting lines 517 and 518 onto the substrate overlap with the orthographic projections of the second structure 482 onto the substrate. Multiple connecting lines can be located in the source / drain metal layers; for example, connecting line 517 can be located in the first source / drain metal layer, and connecting line 518 can be located in the second source / drain metal layer.

[0138] This example, by placing the overlapping connection lines with the second structure in the source and drain metal layers, and by placing multiple inorganic insulating layers (such as including the first to the third insulating layer, or including the first to the fifth insulating layer) between the film layer containing the connection lines and the second structure, can increase the distance between the second structure and the overlapping connection lines in the direction perpendicular to the substrate, which can effectively improve the ESD situation caused by the overlap between the second structure and the metal traces.

[0139] Figure 15 for Figure 1 Another schematic diagram of the partial structure of the central region S3. In some examples, such as... Figure 15 As shown, the second frame region B2 can be provided with multiple gate drive circuits 43 and multiple multiplexing circuits MUX. Each gate drive circuit 43 may include multiple cascaded drive units. The multiplexing circuit MUX can be configured to transmit one data signal to multiple data lines DL. For example, the data line DL of the display area AA can be connected to the multiplexing circuit MUX via connecting line 519. The gate line 471 of the display area can be connected to the drive unit of the gate drive circuit via connecting line 521. The initial signal line 472 of the display area can be connected to the frame initial line 491 of the frame region via connecting line 520. The orthographic projection of connecting lines 519, 520, and 521 onto the substrate may overlap with the orthographic projection of the second structure 482 of the bottom shielding metal layer 48 onto the substrate.

[0140] In some examples, multiple inorganic insulating layers may be disposed between the film layers containing the connecting lines 519, 520, and 521 and the second structure 482. For example, the connecting lines 519, 520, and 521 may be located in the source / drain metal layers. For instance, the connecting line 519 may be located in either the first or second source / drain metal layer.

[0141] This example, by placing the connecting lines of the data transmission signals that overlap with the second structure (such as connecting line 519) in the source and drain metal layers, and by providing multiple inorganic insulating layers (such as including the first to third insulating layers, or including the first to fifth insulating layers) between the film layer containing the connecting lines and the second structure, increases the distance between the second structure and the connecting lines of the overlapping data transmission signals in the direction perpendicular to the substrate, which can effectively improve the ESD situation caused by the overlap between the second structure and the metal traces. Further descriptions of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0142] Figure 16 This is another schematic diagram of a display panel according to at least one embodiment of the present invention. In some examples, such as... Figure 16As shown, the display panel may include a panel crack detection trace 61 located in the bezel area BB. The panel crack detection trace 61 may be arranged around the display area AA, and both ends of the panel crack trace 61 may extend to the signal access area B131 and connect with the corresponding contact pads in the signal access area B131. In the second bezel area B2, the panel crack detection trace 61 may be located on the side of the second bezel power line away from the display area AA.

[0143] In some examples, during the display panel inspection process, the presence of a crack in the display panel can be determined by measuring the resistance value of the panel crack detection trace 61. For instance, if the resistance value of the panel crack detection trace 61 is within a set range, the display panel is considered normal; if the resistance value of the panel crack detection trace 61 exceeds the set range, the panel crack detection trace 61 is considered broken, indicating that the display panel has a crack.

[0144] Figure 17 for Figure 16 A schematic diagram of the local structure of region S4. In some examples, such as... Figure 16 and Figure 17 As shown, the panel crack detection trace 61 may include at least two sequentially connected detection segments (e.g., detection segments 611 and 612), which may be serpentine. Detection segments 611 and 612 may be connected via a detection connection segment 613 in corner areas. For example, detection segments 611 and 612 and the detection connection segment 613 may be a single, integrated structure. For example, the panel crack detection trace 61 may be located in a gate metal layer, such as a second gate metal layer. This example improves crack detection accuracy and reduces ESD risk by using serpentine routing for multiple detection segments of the panel crack detection trace 61.

[0145] Figure 18 for Figure 16 Another schematic diagram of the partial structure of region S4 in the middle. In some examples, such as... Figure 16 and Figure 18 As shown, the panel crack detection trace 61 may include at least two sequentially connected detection segments (e.g., detection segments 611 and 612), which may be serpentine loops. Detection segments 611 and 612 may be connected in corner areas via detection connection segments 613. Detection connection segments 613 and detection segments 611 and 612 may be located on different conductive layers. For example, detection connection segment 613 may be located on the side of detection segments 611 and 612 away from the substrate. For example, detection segments 611 and 612 may be located in the second gate metal layer, and detection connection segment 613 may be located in the first source / drain metal layer. This example, by connecting multiple detection segments of the panel crack detection trace using detection connection segments, allows for electrostatic discharge before and after layer switching, thus optimizing ESD performance.

[0146] This embodiment also provides a display panel, including: a substrate, multiple data lines, multiple first power lines, multiple sub-pixels, and multiple compensation structures disposed on the substrate. The substrate includes a display area and a border area located on at least one side of the display area. The multiple data lines, multiple first power lines, and multiple sub-pixels are located in the display area; the multiple data lines are connected to the multiple sub-pixels and configured to provide data signals to the multiple sub-pixels, and the multiple first power lines are connected to the multiple sub-pixels and configured to provide first power signals to the multiple sub-pixels. The multiple compensation structures are located in the border area, and each compensation structure includes: a first compensation block and a second compensation block located on different conductive layers; the first compensation block has a first main block and a first connecting segment, and the second compensation block has a second main block and a second connecting segment; the size of the first connecting segment is smaller than the size of the first main block, and the size of the second connecting segment is smaller than the size of the second main block; the orthographic projection of the first main block on the substrate and the orthographic projection of the second main block on the substrate at least partially overlap; the first connecting segment is connected to the data lines, and the second connecting segment is connected to the first power lines. The minimum width of the end of the second compensation block of at least one of the plurality of compensation structures is greater than or equal to 3 micrometers.

[0147] The display panel provided in this embodiment improves the compensation structure to avoid the formation of tip discharge at the end of the second connection segment, thereby reducing the possibility of ESD generation and preventing the static electricity released by the compensation structure from damaging the remaining film layers, thus improving the ESD resistance of the display panel.

[0148] In some exemplary embodiments, the minimum width of the end of the second compensation block of at least one of the plurality of compensation structures is 8 micrometers. This example can avoid the formation of tip discharge at the end of the second connection segment, thereby reducing the likelihood of ESD generation.

[0149] In some exemplary embodiments, the second connecting segment of the second compensation block of at least one of the plurality of compensation structures is a serpentine winding. This example can reduce the likelihood of ESD by adding multiple sharp bends to decrease the tip discharge capability at the end of the second connecting segment.

[0150] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element. The pixel circuit is connected to the light-emitting element. The pixel circuit includes at least a driving transistor and a threshold compensation transistor. A first terminal of the threshold compensation transistor is connected to a second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor. The active layer of the threshold compensation transistor includes a first channel region, a second channel region, and a conductive region connecting the first channel region and the second channel region. The orthographic projection of the second connection segment of the second compensation block onto the substrate at least partially overlaps with the orthographic projection of the conductive region of the active layer of the threshold compensation transistor onto the substrate. In some examples, the first compensation block may be located on the side of the second compensation block closer to the substrate. In this example, the second compensation block may be configured to protect the channel region of the threshold compensation transistor from interference, shielding it from other signals (such as data voltage transitions) that could affect the threshold compensation transistor, thus avoiding interference with the normal operation of the pixel circuit and improving the display effect.

[0151] Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0152] Figure 19 This is a schematic diagram of a display device according to at least one embodiment of the present invention. In some examples, such as... Figure 19 As shown, the display device 91 may include a display panel 910. The display panel 910 may be an OLED display panel. The display device 91 may be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0153] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0154] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A display panel, characterized in that, include: The substrate includes a display area and a border area located on at least one side of the display area; Multiple data lines, multiple first power lines, and multiple sub-pixels are located in the display area; the multiple data lines and the multiple sub-pixels are connected and configured to provide data signals to the multiple sub-pixels; the multiple first power lines are connected to the multiple sub-pixels and configured to provide first power signals to the multiple sub-pixels. Multiple compensation structures are located in the border area. Each compensation structure includes a first compensation block and a second compensation block located in different conductive layers. The first compensation block is connected to the data line through a first adapter electrode, and the second compensation block is connected to the first power line through a second adapter electrode. The film containing the first adapter electrode, the second adapter electrode, the data line, and the first power line is located on the side of the film containing the compensation structure away from the substrate.

2. The display panel according to claim 1, characterized in that, At least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element, the pixel circuit being connected to the light-emitting element, the pixel circuit including a plurality of transistors; the orthographic projections of the first compensation block and the second compensation block on the substrate do not overlap with the orthographic projections of the active layer of the plurality of transistors of the pixel circuit on the substrate.

3. The display panel according to claim 1, characterized in that, The first compensation block has a first main block and a first connecting segment, and the second compensation block has a second main block and a second connecting segment; the size of the first connecting segment is smaller than the size of the first main block, and the size of the second connecting segment is smaller than the size of the second main block; The orthographic projection of the first main block on the substrate and the orthographic projection of the second main block on the substrate at least partially overlap. The first connecting segment is connected to the data line through the first adapter electrode, and the second connecting segment is connected to the first power line through the second adapter electrode.

4. The display panel according to claim 3, characterized in that, The first compensation block is located on the side of the second compensation block away from the substrate.

5. The display panel according to claim 4, characterized in that, The compensation structure further includes: a third compensation block located on the side of the first compensation block away from the substrate; the third compensation block having a third main block and a third connecting segment, the size of the third connecting segment being smaller than the size of the third main block; the orthographic projection of the third main block on the substrate at least partially overlapping the orthographic projection of the first main block on the substrate, and the third connecting segment of the third compensation block being connected to the second connecting segment of the second compensation block via the second adapter electrode.

6. The display panel according to claim 5, characterized in that, The second compensation block is located in the first gate metal layer, the first compensation block is located in the second gate metal layer, and the third compensation block is located in the third gate metal layer.

7. The display panel according to claim 3, characterized in that, The second connecting segment of the second compensation block of at least one of the plurality of compensation structures is a serpentine winding.

8. The display panel according to claim 3, characterized in that, The minimum width of the end of the second connecting segment of the second compensation block of at least one of the plurality of compensation structures is greater than or equal to 3 micrometers.

9. The display panel according to claim 7 or 8, characterized in that, At least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element. The pixel circuit is connected to the light-emitting element. The pixel circuit includes at least a driving transistor and a threshold compensation transistor. The first terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor. The active layer of the threshold compensation transistor includes a first channel region, a second channel region, and a conductive region connected between the first channel region and the second channel region. The orthographic projection of the second connection segment of the second compensation block on the substrate at least partially overlaps with the orthographic projection of the conductive region of the active layer of the threshold compensation transistor on the substrate.

10. The display panel according to claim 9, characterized in that, The first compensation block is located on the side of the second compensation block closer to the substrate.

11. The display panel according to claim 1, characterized in that, The display panel further includes: a first frame power line located in the frame area, wherein any corner of the first frame power line is chamfered.

12. The display panel according to claim 11, characterized in that, The display panel further includes: a second frame power line located in the frame area, the second frame power line being located on the side of the first frame power line away from the display area, and a chamfer being formed at any corner of the second frame power line.

13. The display panel according to claim 1, characterized in that, The display panel further includes: a bottom shielding metal layer located on the side of the plurality of sub-pixels close to the substrate; The bottom shielding metal layer includes: a first structure located in the display area and a second structure located in the border area, wherein the first structure and the second structure are connected to form a mesh structure, and the second structure surrounds the display area.

14. The display panel according to claim 13, characterized in that, The display panel further includes a composite insulating layer and a plurality of auxiliary semiconductor blocks located on the side of the bottom shielding metal layer away from the substrate. The composite insulating layer has a plurality of auxiliary vias in the frame area, and the auxiliary vias are configured to expose the surface of the auxiliary semiconductor blocks. The orthographic projections of the plurality of auxiliary vias and the plurality of auxiliary semiconductor blocks on the substrate do not overlap with the orthographic projection of the second structure on the substrate.

15. The display panel according to claim 13, characterized in that, The display panel further includes: multiple connecting lines located in the frame area, wherein the orthographic projection of the multiple connecting lines on the substrate overlaps with the orthographic projection of the second structure on the substrate, and multiple inorganic insulating layers are disposed between the film layer containing the multiple connecting lines and the second structure.

16. The display panel according to claim 15, characterized in that, The multiple connection lines are located in the source and drain metal layers.

17. The display panel according to claim 1, characterized in that, The display panel further includes: panel crack detection wiring located in the frame area; the panel crack detection wiring includes: at least two detection line segments connected in sequence, the detection line segments being serpentine windings.

18. The display panel according to claim 17, characterized in that, The panel crack detection trace further includes a detection connection segment, which connects two adjacent detection segments, and the film layer where the detection connection segment is located is located on the side of the film layer where the detection segment is located away from the substrate.

19. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 18.

20. A display panel, characterized in that, include: The substrate includes a display area and a border area located on at least one side of the display area; Multiple data lines, multiple first power lines, and multiple sub-pixels are located in the display area; the multiple data lines and the multiple sub-pixels are connected and configured to provide data signals to the multiple sub-pixels; the multiple first power lines are connected to the multiple sub-pixels and configured to provide first power signals to the multiple sub-pixels. Multiple compensation structures are located in the border area. Each compensation structure includes a first compensation block and a second compensation block located on different conductive layers. The first compensation block has a first main block and a first connecting segment, and the second compensation block has a second main block and a second connecting segment. The size of the first connecting segment is smaller than the size of the first main block, and the size of the second connecting segment is smaller than the size of the second main block. The orthographic projection of the first main block onto the substrate and the orthographic projection of the second main block onto the substrate at least partially overlap. The first connecting segment is connected to the data line, and the second connecting segment is connected to the first power line. The minimum width of the end of the second compensation block of at least one of the multiple compensation structures is greater than or equal to 3 micrometers.

21. The display panel according to claim 20, characterized in that, The minimum width of the end of the second compensation block of at least one of the plurality of compensation structures is 8 micrometers.

22. The display panel according to claim 20, characterized in that, The second connecting segment of the second compensation block of at least one of the plurality of compensation structures is a serpentine winding.

23. The display panel according to any one of claims 20 to 22, characterized in that, At least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element. The pixel circuit is connected to the light-emitting element. The pixel circuit includes at least a driving transistor and a threshold compensation transistor. The first terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor. The active layer of the threshold compensation transistor includes a first channel region, a second channel region, and a conductive region connected between the first channel region and the second channel region. The second connection segment of the second compensation block, in its orthographic projection onto the substrate, at least partially overlaps with the orthographic projection of the conductor region of the active layer of the threshold compensation transistor onto the substrate.

24. The display panel according to claim 23, characterized in that, The first compensation block is located on the side of the second compensation block closer to the substrate.

Images