An accelerator control system based on a RISC-V processor
By introducing vector and scalar extension interfaces into the RISC-V processor, efficient management of multiple accelerator groups is achieved, solving the problems of compilation complexity and resource waste in existing technologies, and improving the system's parallel computing capabilities and resource utilization efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WUXI MICRONANO CORE ELECTRONIC TECH CO LTD
- Filing Date
- 2025-07-18
- Publication Date
- 2026-07-24
AI Technical Summary
Existing RISC-V-based AI accelerator control systems face issues of compilation complexity and resource waste when scaling to multiple neural network accelerators, especially increasing the workload for developers in terms of parallelism and communication optimization.
By employing a RISC-V processor combined with vector extension interfaces and scalar extension interfaces, and through instruction dispatch units and group selectors, it achieves efficient management of multiple accelerator groups, and supports flexible dispatch and parallel execution of scalar and vector instructions.
It improves instruction distribution efficiency, reduces resource waste, enhances system flexibility and parallel computing capabilities, and adapts to more diverse computing needs.
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Figure CN224553771U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of artificial intelligence technology, specifically to an accelerator control system based on a RISC-V processor. Background Technology
[0002] With the rapid development of artificial intelligence algorithms, especially the rapid expansion of large language models, there are high requirements for the computing power, bandwidth, and energy efficiency of deployment platforms. Traditional hardware such as CPUs and GPUs cannot meet the needs of efficient AI model deployment in practical applications. Therefore, many domestic and foreign manufacturers have invested a lot of effort in promoting the research of dedicated AI hardware systems, attempting to break through the limitations of traditional hardware for deploying neural networks. They are committed to significantly accelerating key operations in deep learning algorithms such as multiplication-accumulation and vector computation through dedicated hardware, thereby greatly improving the computational energy efficiency (TOPS / W) of neural network deployment.
[0003] In recent years, with the rapid development of artificial intelligence technology, neural networks have been increasingly widely used in fields such as image recognition, speech processing, and natural language understanding. However, the training and inference processes of neural networks typically involve large-scale matrix operations and data processing, which places extremely high demands on computing resources. To address this challenge, neural networks usually need to be broken down into multiple workloads and deployed on distributed neural network kernels, such as... Figure 1 As shown, this distributed architecture can effectively accelerate the computation process of neural networks, making full use of hardware resources through parallel processing, thereby significantly improving processing efficiency and throughput, while shortening training and inference time.
[0004] However, the operation of neural network workloads relies not only on matrix operations but also involves a significant amount of scalar computation. For example, task load slicing requires loop operations, conditional checks, and address generation. These scalar computations play a crucial role in the control flow of neural networks, directly impacting the efficiency of task scheduling and data flow. To efficiently manage these scalar computations, the RISC-V instruction set architecture is an ideal choice due to its openness, flexibility, and efficiency. The RISC-V scalar instruction set enables precise control of neural network accelerators, including task allocation, data flow management, and exception handling. By adopting a heterogeneous RISC-V architecture, neural network accelerators can maintain high performance while possessing excellent programmability and adaptability.
[0005] Furthermore, the versatility of RISC-V further enhances the functional completeness of neural network accelerators. With the help of the RISC-V instruction set, developers can not only efficiently implement neural network-related computational tasks but also easily handle other general-purpose computing needs. This flexibility enables distributed neural network accelerators to be applied to a wider range of scenarios, such as edge computing, embedded systems, and high-performance computing, providing strong hardware support for the development of artificial intelligence technology.
[0006] In summary, the distributed neural network accelerator architecture achieves high-efficiency acceleration by decomposing the neural network into multiple workloads and deploying them on distributed cores; while the application of the RISC-V instruction set, through its scalar computing capabilities and versatility, further improves the control precision and application scope of the accelerator.
[0007] However, current solutions for AI extension based on RISC-V have certain limitations, especially when scaling to multiple neural network accelerators, which present significant challenges.
[0008] Existing solutions typically use a single neural network accelerator as the core, coupled with a single RISC-V processor. This architecture struggles when scaled to many-core (multi-core) systems, such as... Figure 2 As shown, this will bring the following difficulties:
[0009] Compilation complexity: The compiler needs to generate instructions for multiple RISC-V cores simultaneously and schedule their execution appropriately. Instruction communication between multiple RISC-V cores requires additional management mechanisms to ensure data consistency and task collaboration. These requirements significantly increase the workload for programmers and compiler developers, especially in terms of parallelism and communication optimization.
[0010] Resource waste: Neural network tasks, such as convolution computation and LLM, exhibit significant parallel computing characteristics, with a large portion of parallel computations potentially using identical instructions. Therefore, the above architecture suffers from wasted resources, including instruction memory, RISC-V hardware resources, and neural network accelerator hardware resources.
[0011] Therefore, it is necessary to improve the existing accelerator control system and the accelerator control method. Attached Figure Description
[0012] Figure 1 This is a schematic diagram of the architecture of a neural network model and an acceleration kernel in the existing technology.
[0013] Figure 2 This is a schematic diagram of the architecture of a RISC-V processor and its acceleration core in the existing technology.
[0014] Figure 3A schematic diagram of the control system architecture for a RISC-V processor-based accelerator provided for an embodiment of this utility model;
[0015] Figure 4 for Figure 3 A schematic diagram of the RISC-V processor architecture;
[0016] Figure 5 This is a schematic diagram of the control system architecture for the RISC-V processor-based accelerator provided in an embodiment of this utility model.
[0017] Figure 6 This is a schematic diagram of the cooperative architecture of the selector and accelerator group in an embodiment of this utility model;
[0018] Figure 7 This is a schematic diagram of the architecture of the acceleration core in an embodiment of this utility model;
[0019] Figure 8 A schematic diagram illustrating the steps of an accelerator control method provided for an embodiment of this utility model. Detailed Implementation
[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0021] like Figure 3 As shown, this embodiment provides an accelerator control system based on a RISC-V processor, including:
[0022] The RISC-V processor 100 includes a vector extension interface 110 and a scalar extension interface 120, and is capable of loading instructions and decoding them before sending them to multiple accelerator groups 200.
[0023] Multiple accelerator groups 200 are used to execute acceleration commands;
[0024] Instruction dispatch unit 300, connected to RISC-V processor 100, is used to dispatch instructions and operands of RISC-V processor 100 to each accelerator group 200; and
[0025] Group selector 400 is connected to instruction distribution unit 300 and each accelerator group 200 respectively, so as to select a specific accelerator group 200 to execute instructions.
[0026] The RISC-V processor-based accelerator control system provided in this embodiment can efficiently distribute instructions and operands to multiple accelerator cores through the setting of vector extension interface 110 and scalar extension interface 120, so that the RISC-V processor 100 can manage multiple accelerator cores, thereby meeting the needs of high-performance computing.
[0027] Optionally, refer to Figure 4 The RISC-V processor 100 also includes:
[0028] The instruction loading unit 130 is configured to connect to the instruction memory 500 and retrieve instructions stored in the instruction memory 500.
[0029] The instruction decoding unit 140 has its input end connected to the instruction loading unit 130 and its output end connected to the scalar extension interface 120 and the vector extension interface 110, respectively. It can decode and parse instructions and send the instructions to the extension interface corresponding to the type based on the parsing result.
[0030] Scalar register 150, connected to scalar extension interface 120 and vector extension interface 110, is used to send corresponding operands to scalar extension interface 120 and / or vector extension interface 110; and
[0031] Vector register 160, connected to vector extension interface 110, is used to send corresponding operands to vector extension interface 110.
[0032] In this embodiment, such as Figure 5 As shown, the instruction obtained by the RISC-V processor 100 is parsed by the instruction decoding unit 140 to determine the instruction type, specifically: scalar extension instruction, vector extension instruction, or standard RISC-V instruction. If the instruction decoding unit 110 determines that the instruction is a scalar extension instruction or a vector extension instruction, it further parses the opcode and operand fields in the instruction to determine the subsequent processing flow.
[0033] For scalar extension instructions or vector extension instructions, the instruction decoding unit 110 selects the corresponding register operand based on the operand field in the instruction. Specifically:
[0034] If the instruction is a scalar extension instruction, the operand is extracted from scalar register 150; if the instruction is a vector extension instruction, the operand is extracted from vector register 160. The extracted operand and the parsed extension instruction are sent together to the corresponding extension interface: scalar extension instructions and their operands are sent to scalar extension interface 120; vector extension instructions and their operands are sent to vector extension interface 110.
[0035] Optionally, the scalar extension interface 120 includes: a scalar source register 121, connected to the scalar register 150, and capable of obtaining and storing the required operands from the scalar register 150; a scalar destination register 122, used to store the execution result of the scalar extension instruction; and a scalar extension instruction register 123, used to store the scalar extension instruction parsed by the instruction decoding unit 140.
[0036] Optionally, the vector extension interface 110 includes a scalar source register 111, connected to the scalar register 150, which can obtain and store the required operands from the scalar register 150; a vector source register 112, connected to the vector register 160, which can obtain and store the required operands from the vector register 160; a vector destination register 113, which stores the execution result of the vector extension instruction; and a vector extension instruction register 114, which stores the vector extension instruction parsed by the instruction decoding unit 140.
[0037] In this embodiment, the data stored in the scalar register 150 can also be used as operands in the vector extension interface 110. This design enables the mixed execution of vector and scalar operations, supports the extraction of operands from scalar source registers and vector source registers, and realizes the mixed execution of scalar and vector operations. This enhances the versatility and flexibility of the system, enabling it to adapt to more diverse computing needs.
[0038] Optionally, the instruction dispatch unit 300 is responsible for distributing instructions and operands to multiple acceleration cores 210.
[0039] When multiple acceleration cores 210 require the same operands, the RISC-V processor 100 performs the following operations through the scalar extension interface 120: the instruction decoding unit 140 parses the instruction and confirms that the operands are scalar data; the instruction and the corresponding scalar data are broadcast to all acceleration cores 210 through the scalar extension interface 120; each acceleration core determines whether to receive the broadcast instruction and operands based on the value of its corresponding instruction mask register (also referred to as the instruction mask in this embodiment):
[0040] If the instruction mask register bit is set (e.g., "1"), the core receives and executes the instruction;
[0041] If the instruction mask register bit is not set (e.g., "0"), the core ignores the instruction.
[0042] When the number of operands required by each acceleration core 210 is different, the RISC-V processor 100 performs the following operations through the vector extension interface 110:
[0043] Instruction decoding unit 140 parses the instruction and confirms that the operand is vector data.
[0044] Vector data is decomposed into multiple scalar quantum sets.
[0045] The vector interface distributes these scalar quantum sets to the corresponding acceleration cores 210.
[0046] Each acceleration core selectively receives operands assigned to it and executes instructions based on the instruction mask register value:
[0047] If the instruction mask register bit is set (e.g., "1"), the core receives and executes the instruction;
[0048] If the instruction mask register bit is not set (e.g., "0"), the core ignores the instruction.
[0049] Optionally, such as Figure 6 As shown, in order to further save hardware resources and meet the length requirements of vector registers in RISC-V, this embodiment divides multiple acceleration cores 210 into multiple accelerator groups 200. Each accelerator group 200 includes multiple acceleration cores 210 and an instruction mask register 220. Each acceleration core 210 can independently execute acceleration instructions. The instruction mask register 220 includes multiple mask bits corresponding to the multiple acceleration cores 210 to control whether the corresponding acceleration core 210 receives and executes instructions.
[0050] The technical benefits of this design include enabling flexible parallel computing capabilities:
[0051] For scalar extension instructions, the system can broadcast the instruction and operands to each accelerator core in the active accelerator group, and each accelerator core selectively executes the instruction based on the state of the instruction mask register. This broadcasting mechanism enables fine-grained parallel control, allowing multiple accelerator cores in the accelerator group to process independent scalar operations simultaneously, thereby improving the throughput of scalar computation.
[0052] For vector expansion instructions, the system can decompose the vector into scalar subsets and distribute them directionally to designated acceleration cores within the activated accelerator group. This vector decomposition and directional distribution mechanism enables complex vector operations to be efficiently parallelized, with each acceleration core processing a subset of the vector data, greatly accelerating the execution of data-intensive tasks.
[0053] Optionally, the number of acceleration cores 210 in multiple accelerator groups 200 can be the same or different, and the maximum number can not exceed the bit width of the instruction mask register.
[0054] When sending instructions, the RISC-V processor 100 can select one of the accelerator groups 200 through the group selector 400, and send the corresponding vector expansion and scalar expansion to each acceleration core 210 in the corresponding accelerator group 200.
[0055] Optionally, the instruction dispatch unit 300 is configured to: when the operand is a scalar, broadcast the instruction and operand to each acceleration core 210 of the activated accelerator group 200 through the scalar extension interface 120, and each acceleration core 210 selectively executes the instruction according to the state of the instruction mask register 220; when the operand is a vector, decompose the vector into a scalar set and distribute it to the designated acceleration core 210 within the activated accelerator group 200 through the vector extension interface 110.
[0056] In particular, in this embodiment, the system is configured to include a fully parallel mode, in which instructions can be sent to all accelerator groups in parallel, which is equivalent to having 1 group. All accelerator cores 210 can receive instructions in parallel within the group. This design can enhance instruction sending efficiency.
[0057] Optionally, such as Figure 7 As shown, for each acceleration core 210, the acceleration core 210 includes: scalar source register 211, scalar source register 212, destination register 213, and instruction decoding unit 214. The scalar source register 211, scalar source register 212, and destination register 213 are connected to the instruction decoding unit 214, that is, its interface always appears as an extended form of scalars. Regardless of whether the input data is a scalar or a vector, the instruction dispatch unit 300 decomposes all operands and converts them into scalar form for transmission. The interface of each acceleration core 210 always appears as a scalar interface, that is, the instructions and operands received by the scalar interface are transmitted in scalar form. It can directly broadcast scalar extended instructions and distribute scalar quantum sets after vector extended instructions are decomposed. The technical effects of this design mainly include: 1) Consistency: All acceleration cores 210 receive instructions and operands through the same scalar extended interface 120, simplifying hardware design. 2) Compatibility: Supports unified processing of multiple instruction types (scalar instructions or scalar quantum sets after vector decomposition).
[0058] Optionally, such as Figure 8 As shown, this embodiment also provides a control method for an accelerator, which uses the RISC-V processor-based accelerator control system provided in this embodiment to control the accelerator / accelerator group, including the following steps:
[0059] The instruction parsing step resolves the instruction into scalar extended instructions and / or vector extended instructions;
[0060] The accelerator set selection step selects the corresponding accelerator set based on scalar expansion instructions and / or vector expansion instructions; and
[0061] In the instruction execution steps, the corresponding accelerator group executes scalar expansion instructions and / or vector expansion instructions.
[0062] The accelerator control method provided in this embodiment can achieve efficient instruction processing and distribution:
[0063] By parsing instructions into scalar extended instructions and / or vector extended instructions, the system can intelligently classify and process instructions based on their type. This allows different types of computational tasks to be precisely distributed to the accelerator groups or acceleration cores best suited to handle them.
[0064] After instruction parsing, the corresponding accelerator group can be selected based on the instruction type, avoiding unnecessary resource consumption and data transmission, and improving the efficiency of instruction distribution.
[0065] Optionally, the instruction execution steps include:
[0066] The mask register value based on the instruction mask register selectively receives operands and executes instructions.
[0067] This design enables flexible parallel computing capabilities:
[0068] For scalar extension instructions, the system can broadcast the instruction and operands to each accelerator core in the active accelerator group, and each accelerator core selectively executes the instruction based on the state of the instruction mask register. This broadcasting mechanism enables fine-grained parallel control, allowing multiple accelerator cores in the accelerator group to process independent scalar operations simultaneously, thereby improving the throughput of scalar computation.
[0069] For vector expansion instructions, the system can decompose the vector into scalar subsets and distribute them directionally to designated acceleration cores within the activated accelerator group. This vector decomposition and directional distribution mechanism enables complex vector operations to be efficiently parallelized, with each acceleration core processing a subset of the vector data, greatly accelerating the execution of data-intensive tasks.
[0070] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.
Claims
1. An accelerator control system based on a RISC-V processor, characterized in that, include: The RISC-V processor includes a vector extension interface and a scalar extension interface, which can load instructions and decode them into vector extension instructions and / or scalar extension instructions before sending them to multiple accelerator groups. Multiple accelerator groups are used to execute the instructions; The instruction dispatch unit, connected to the RISC-V processor, is used to distribute the instructions and operands of the RISC-V processor to each accelerator group; as well as Group selectors are connected to the instruction distribution unit and each of the accelerator groups respectively, to select a specific accelerator group to execute instructions.
2. The accelerator control system based on a RISC-V processor according to claim 1, characterized in that, The RISC-V processor includes: An instruction loading unit is configured to connect to an instruction memory and retrieve instructions stored in the instruction memory; The instruction decoding unit has an input end connected to the instruction loading unit and an output end connected to the scalar extension interface and the vector extension interface, respectively. It can decode and parse the instruction and send the instruction to the extension interface corresponding to the type based on the parsing result. A scalar register, connected to the scalar extension interface and the vector extension interface, is used to send corresponding operands to the scalar extension interface and / or the vector extension interface; and A vector register, connected to the vector extension interface, is used to send corresponding operands to the vector extension interface.
3. The accelerator control system based on a RISC-V processor according to claim 2, characterized in that, Each of the accelerator groups includes multiple acceleration cores and an instruction mask register. Each acceleration core can independently execute acceleration instructions. The instruction mask register includes multiple mask bits corresponding to the multiple acceleration cores to control whether the corresponding acceleration core receives and executes instructions.
4. The accelerator control system based on a RISC-V processor according to claim 2, characterized in that, The scalar extension interface includes: A scalar source register, connected to the scalar register, capable of obtaining and storing the required operands from the scalar register; The scalar destination register is used to receive the execution result of scalar expansion instructions; and The scalar extended instruction register is used to store the scalar extended instructions obtained by the instruction decoding unit.
5. The accelerator control system based on a RISC-V processor according to claim 2, characterized in that, The vector extension interface includes: A scalar source register, connected to the scalar register, capable of obtaining and storing the required operands from the scalar register; A vector source register, connected to the vector register, capable of obtaining and storing the required operands from the vector register; The vector destination register is used to receive the execution result of vector extension instructions; and The vector extension instruction register is used to store the vector extension instructions obtained by the instruction decoding unit.
6. The accelerator control system based on a RISC-V processor according to claim 3, characterized in that, The instruction distribution unit is configured to: when the operand is a scalar, broadcast the instruction and operand to each acceleration core of the activated accelerator group through the scalar extension interface, and each acceleration core selectively executes the instruction according to the state of the instruction mask register; when the operand is a vector, decompose the vector into a scalar set and distribute it to a designated acceleration core within the activated accelerator group through the vector extension interface.
7. The accelerator control system based on a RISC-V processor according to claim 3, characterized in that, The accelerator groups are grouped in such a way that the number of accelerator cores in each accelerator group does not exceed the bit width of the instruction mask register.
8. The RISC-V processor-based accelerator control system according to claim 3 is configured to include a fully parallel mode, in which the acceleration cores belong to the same accelerator group and simultaneously receive and execute instructions.
9. The accelerator control system based on a RISC-V processor according to claim 3, characterized in that, The interface of the acceleration core is a scalar interface. The instructions and operands received by the scalar interface are transmitted in scalar form. It can directly broadcast scalar extended instructions and distribute scalar quantum sets after decomposition of vector extended instructions.
10. The accelerator control system based on a RISC-V processor according to claim 2, characterized in that, The vector extension interface supports extracting operands from scalar source registers and vector source registers, enabling mixed execution of scalar and vector operations.