Asynchronous data access interface device and end-side device
By using rising and falling edge sampling sequences to process asynchronous data in the edge device, the data transmission bottleneck and energy consumption problems are solved, efficient asynchronous data access is achieved, and the performance and energy efficiency of large model inference are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WUXI MICRONANO CORE ELECTRONIC TECH CO LTD
- Filing Date
- 2025-07-18
- Publication Date
- 2026-07-24
AI Technical Summary
In edge devices, due to limited computing and storage resources, frequent memory access leads to data transmission bottlenecks and increased energy consumption. Existing asynchronous data access methods cannot effectively handle asynchronous data, affecting the performance and energy efficiency of large model inference.
The reading data valid signal is sampled based on the rising and falling edges of the clock to generate rising edge sampling sequence and falling edge sampling sequence. The first valid data is determined by the valid data judgment circuit and a trigger signal is generated to realize synchronous sampling of the reading data.
It enables continuous asynchronous data reading in scenarios without a clock data source, reduces power consumption, and improves the performance and energy efficiency of large model inference, making it suitable for edge devices such as AI mobile phones and AIPCs.
Smart Images
Figure CN224553773U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of artificial intelligence technology, specifically to an asynchronous data access interface device and an end-side device. Background Technology
[0002] With the rapid development of artificial intelligence (AI) technology, the application scenarios based on large pre-trained models are constantly expanding, such as natural language processing, image recognition, and multimodal interaction. Large models are widely used in both the cloud and edge devices due to their superior performance. However, with the continuous growth in the scale of model parameters, migrating large models from the cloud to edge devices (such as AI smartphones and AIPCs) faces many challenges.
[0003] like Figure 1 As shown, edge devices have relatively limited computing and storage resources compared to cloud servers due to limitations in power consumption, size, and real-time response requirements. In particular, during large model inference, frequent memory accesses lead to the transfer of large amounts of data between the processor and memory. Currently, the mainstream storage medium is DRAM, which, limited by data transfer bandwidth and access latency, has become a significant bottleneck restricting the performance of large model inference. Furthermore, frequent data transfers significantly increase system power consumption, negatively impacting the battery life of mobile devices.
[0004] To address the aforementioned issues, a common technical approach is to directly integrate computing units into the memory system, such as embedding processor units or computing engines within DRAM. This "near-memory computing" architecture effectively reduces the distance and frequency of data transmission, improving data processing efficiency. The core concept of in-memory computing is to execute computing tasks locally, that is, to complete computation directly at the data storage location. This, to a certain extent, breaks through the bottleneck of the traditional "storage-computing" separation architecture, significantly improving the performance and energy efficiency of edge devices running large models. The design and optimization of in-memory computing architectures for edge acceleration of large models has significant research value and application prospects.
[0005] Its end-side equipment, such as Figure 2As shown, DRAM chips and computing logic achieve high-bandwidth interconnection through a three-dimensional stacking configuration. Compared to Device 1, which decouples the computing logic's process platform from the DRAM memory chip platform, the computing logic can utilize more advanced CMOS logic processes to achieve large-scale computing power integration. In this device, the near-memory computing architecture, by integrating large-scale computing power, significantly reduces the SoC's computing load or allows the near-memory computing architecture to handle end-to-end applications of large models. This solves the performance bottleneck of large model inference caused by the low data transfer bandwidth of existing memory interfaces.
[0006] like Figure 3 As shown, an interface needs to be designed in the computing logic chip to achieve efficient access to data in the DRAM chip. Inside the DRAM chip, communication is typically achieved through clockless asynchronous circuits; therefore, the data signal paths between the logic chip and the DRAM chip are not synchronized by a clock. Furthermore, the circuit delays introduced by three-dimensional bonding cannot be incorporated into current EDA tools, making it difficult to synchronize the two using the same clock. Based on this consideration, an asynchronous data interface needs to be designed on the logic die to enable the reception and transmission of asynchronous data.
[0007] like Figure 4 , 5 As shown, to fully utilize the bandwidth of DRAM chips, the chips typically use the Burst read / write method to achieve continuous reading and writing of multiple data entries. This means that multiple data entries are continuously processed by sending data addresses consecutively. Data operations can be divided into write data timing and read data timing. In the write timing, the DRAM chip only acts as an input, while the Logic chip generates the write indicator signal line, the address, and the data line to be written. Therefore, these signals generated by the Logic chip can be synchronized with the Logic chip's own clock, and these digital timing signals can be generated using synchronous circuit design methods.
[0008] like Figure 5As shown, similarly, the Logic chip generates continuous read signal indicator lines and addresses through a synchronous circuit, which are then sent to the DRAM chip. After a certain delay (read delay), the DRAM chip returns valid read data and the corresponding address data. In Burst reads and writes, regardless of whether it's a read or write sequence, the address increases uniformly. The read sequence has the following characteristics: 1) the rate of change of read data is consistent with the rate of change of address; 2) the read delay is an asynchronous signal for the Logic chip due to chip differences and variations. Simply using the rising edge of the clock for sampling may not meet the setup time, leading to sampling metastability. Traditionally, asynchronous data processing typically uses two methods to sample the valid signal using a sampling clock: two-stage pipelined timing or asynchronous FIFO. Asynchronous FIFOs, with sufficient depth, can solve most cross-clock domain data interaction problems, but they require not only a sampling clock but also the asynchronous clock of the sampled data. In this scenario, there is no asynchronous clock for the data, so this method is not suitable for handling this situation. Two-stage pipelined timing is suitable for processing single-bit signals across clock domains. However, in the scenario discussed in this paper, although the valid read data signal remains unchanged for a long period after it goes high, the read data itself changes every cycle. If the read data is sampled based on the signal after two-stage pipeline timing, previous data will inevitably be lost. Furthermore, using this synchronization method to sample multi-bit signals significantly increases the probability of sampling metastable states.
[0009] Therefore, it is necessary to improve existing asynchronous data access methods and end-side devices. Utility Model Content
[0010] To address the above problems, this utility model provides an asynchronous data access method, including:
[0011] The valid data signal is sampled based on the rising and falling edges of the clock to generate rising edge sampling sequences and falling edge sampling sequences.
[0012] The first valid data is determined based on the rising edge sampling sequence and the falling edge sampling sequence, and a trigger signal is generated; and
[0013] Based on the trigger signal, the read data signal is sampled to obtain stable data synchronized with the clock.
[0014] The asynchronous data access method provided in this application enables continuous asynchronous data reading in clockless data source scenarios. Furthermore, it achieves asynchronous data reading without the need for pre-sampling of multi-bit read data, effectively reducing power consumption. This device is particularly suitable for near-memory computing architectures in edge devices, significantly improving the performance and energy efficiency of large model inference, and is applicable to edge devices such as AI smartphones and AIPCs.
[0015] Optionally, the step of "determining the first valid data based on the rising edge sampling sequence and the falling edge sampling sequence, and generating a trigger signal" includes:
[0016] If metastable data appears in the sampling results of the rising edge sampling sequence, it is determined whether stable data appears based on the falling edge sampling sequence; and
[0017] If metastable data appears in the sampling results of the falling edge sampling sequence, it is determined whether stable data appears based on the rising edge sampling sequence.
[0018] In this application, by determining the valid data for both the rising and falling edge sampling sequences, metastable data in the sampling results can be avoided.
[0019] Optionally, the step of "sampling the input data based on the rising and falling edges of the clock to generate a rising edge sampling sequence and a falling edge sampling sequence" includes:
[0020] Generate multiple clock signals clk_p0, clk_p1, ..., clk_pn with different phases; and
[0021] Based on the multiple clock signals with different phases, the input data is sampled to obtain multiple sets of rising edge sampling sequences and falling edge sampling sequences p0, p1, ..., pn.
[0022] Optionally, the step of "determining the first valid data based on the rising edge sampling sequence and the falling edge sampling sequence, and generating a trigger signal" further includes:
[0023] In response to the detection of metastable data in a certain set of rising edge sampling sequences and falling edge sampling sequences, the next set of rising edge sampling sequences and falling edge sampling sequences are detected to determine whether the metastable data occurs at a rising edge or a falling edge; and
[0024] If the metastable data is determined to appear on the rising edge, the data reading sampling time is the first falling edge of clk_pn after the sampling interval; if the metastable data is determined to appear on the falling edge, the data reading sampling time is the first rising edge of clk_pn after the sampling interval.
[0025] Optionally, the subsequent synchronization circuit acquires data on the next rising edge of the data sampling time.
[0026] To achieve the aforementioned utility model objectives, this application provides an asynchronous data access interface device comprising:
[0027] The rising and falling edge clock sampling circuit samples the read data based on the rising and falling edges of the clock, respectively, to generate rising edge sampling sequences and falling edge sampling sequences.
[0028] A valid data determination circuit, connected to the rising and falling edge clock sampling circuit, determines the first valid data based on the rising edge sampling sequence and the falling edge sampling sequence, and generates a trigger signal; and
[0029] A data sampling circuit, connected to the valid data judgment circuit, samples the read data based on the trigger signal to obtain stable data synchronized with the clock.
[0030] The asynchronous data access interface device provided in this application enables continuous asynchronous data reading in clockless data source scenarios. Furthermore, it achieves asynchronous data reading without the need for pre-sampling of multi-bit read data, effectively reducing power consumption. This device is particularly suitable for near-memory computing architectures on edge devices, significantly improving the performance and energy efficiency of large model inference, and is applicable to edge devices such as AI smartphones and AIPCs.
[0031] Optionally, the rising and falling edge clock sampling circuit includes:
[0032] The top edge sampling clock includes multiple delay chains with increasing delay time. The input of each delay chain is connected to the clock clk, and the output generates multiple clock signals clk_p1, clk_p2, ..., clk_pn with different phases.
[0033] The lower-edge sampling clock includes an inverter and a multi-path delay chain with increasing delay times. The input of the inverter is connected to the clock clk, and the input of each multi-path delay chain is connected to the output of the inverter. The outputs generate multiple clock signals clk_inv_p1, clk_inv_p2, ..., clk_inv_pn with different phases.
[0034] A multi-channel sampling circuit, each sampling circuit including a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop. The input terminals of the first and second flip-flops are configured to receive a valid read data signal. The clock terminals of the first and third flip-flops are configured to be connected to clk_p1, clk_p2, ..., clk_pn, respectively. The clock terminals of the second and fourth flip-flops are configured to be connected to clk_inv_p1, clk_inv_p2, ..., clk_inv_pn, respectively. The output terminals of the first and third flip-flops form upper edge sequences 1 to N, respectively. The output terminals of the second and fourth flip-flops form lower edge sequences 1 to N, respectively.
[0035] Optionally, the valid data judgment circuit includes a multi-stage detection circuit connected in sequence, namely a first-stage detection circuit, a second-stage detection circuit, ..., an Nth-stage detection circuit. The input terminals of the first-stage detection circuit are respectively connected to the upper edge sequence 1 and the lower edge sequence 1; the input terminals of the second-stage detection circuit are respectively connected to the upper edge sequence 2 and the lower edge sequence 2; ...; the input terminals of the Nth-stage detection circuit are respectively connected to the upper edge sequence N and the lower edge sequence N.
[0036] In order to achieve the above-mentioned utility model objectives, this application provides an end-side device that applies the asynchronous data access method or the asynchronous data access interface device described above.
[0037] Optionally, the edge device is an AI mobile phone or an AI PC. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of the structure of a mid-side device in the prior art;
[0039] Figure 2 This is a schematic diagram of the structure of the other end device in the prior art;
[0040] Figure 3 This is a schematic diagram illustrating the transmission of asynchronous data signals in an architecture where a logic chip is equipped with a clock module, as described in the prior art.
[0041] Figure 4 A timing logic diagram for writing data in existing technologies;
[0042] Figure 5 This is a timing logic diagram for reading data in existing technologies;
[0043] Figure 6 A schematic diagram of the structure of the asynchronous data access interface device provided for the embodiments of this application;
[0044] Figure 7 This is a schematic diagram of the circuit structure of the upper edge sampling clock and the lower edge sampling clock in the upper and lower edge clock sampling circuit provided in the embodiments of this application.
[0045] Figure 8 This is a schematic diagram of the circuit structure of the multi-channel sampling circuit in the rising and falling edge clock sampling circuit provided in the embodiments of this application;
[0046] Figure 9 This is a schematic diagram of the circuit structure of the effective data judgment circuit provided in the embodiments of this application;
[0047] Figure 10 This is a timing logic diagram of the data sampling circuit provided in an embodiment of this application;
[0048] Figure 11 This is a schematic diagram illustrating the steps of the asynchronous data access method provided in the embodiments of this application. Detailed Implementation
[0049] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0050] This embodiment provides an asynchronous data access interface device 100, such as... Figure 6 As shown, it includes:
[0051] The rising and falling edge clock sampling circuit 10 samples the valid data signal based on the rising and falling edges of the clock, respectively, to generate rising edge sampling sequence and falling edge sampling sequence.
[0052] The valid data determination circuit 20, connected to the rising and falling edge clock sampling circuit 10, determines the first valid data based on the rising edge sampling sequence and the falling edge sampling sequence, and generates a trigger signal; and
[0053] The data sampling circuit 30 is connected to the valid data judgment circuit 20. Based on the trigger signal, it samples the read data signal to obtain stable data synchronized with the clock.
[0054] The asynchronous data access interface device 100 provided in this embodiment can realize continuous asynchronous data reading in clockless data source scenarios. Moreover, it achieves asynchronous data reading without the need for pre-sampling of multi-bit read data, effectively reducing power consumption. This device is particularly suitable for near-memory computing architectures of edge devices, and can significantly improve the performance and energy efficiency of large model inference. It is applicable to edge devices such as AI mobile phones and AIPCs.
[0055] Optionally, such as Figure 7 and Figure 8 As shown, the rising and falling edge clock sampling circuit 10 includes:
[0056] The top edge sampling clock 11 includes a multi-path delay chain with increasing delay time. The input of the multi-path delay chain is connected to the clock clk, and the output generates multiple clock signals clk_p1, clk_p2, ..., clk_pn with different phases.
[0057] The lower-edge sampling clock 12 includes an inverter and a multi-path delay chain with increasing delay time. The input of the inverter is connected to the clock clk, and the input of the multi-path delay chain is connected to the output of the inverter. The output generates multiple clock signals clk_inv_p1, clk_inv_p2, ..., clk_inv_pn with different phases.
[0058] The multi-channel sampling circuit 13 includes a first flip-flop D1, a second flip-flop D2, a third flip-flop D3, and a fourth flip-flop D4. The input terminals of the first flip-flop D1 and the second flip-flop D2 are configured to receive a valid read data signal. The clock terminals of the first flip-flop D1 and the third flip-flop D3 are configured to be connected to clk_p1, clk_p2, ..., clk_pn, respectively. The clock terminals of the second flip-flop D2 and the fourth flip-flop D3 are configured to be connected to clk_inv_p1, clk_inv_p2, ..., clk_inv_pn, respectively. The output terminals of the first flip-flop D1 and the third flip-flop D3 form the upper edge sequence 1 to the upper edge sequence N, respectively. The output terminals of the second flip-flop D2 and the fourth flip-flop D4 form the lower edge sequence 1 to the lower edge sequence N, respectively.
[0059] The clk signal is processed through a multi-delay chain to generate a series of clock signals with gradually shifting phases, namely clk_p1, clk_p2, ..., clk_pn. These clock signals are characterized by being based on the rising edge of clk, but each having a different delay, thus providing multiple "windows" for sampling data at different time points.
[0060] The clk signal first passes through an inverter to generate clk_inv (i.e., the falling edge of clk). Then, clk_inv passes through a multiplexed delay chain to generate a series of clock signals with progressively shifting phases, namely clk_inv_p1, clk_inv_p2, ..., clk_inv_pn. These clock signals, based on the falling edge of clk, provide another set of "windows" for sampling data at different time points.
[0061] The function of the multi-sampling circuit is to perform intensive sampling near the rising and falling edges of the valid read data signal using a multi-phase clock signal. This is done to capture the precise transition points of the valid read data signal, as the valid signal of asynchronous data may not be perfectly aligned with the edges of the local clock. By using multiple sampling points, the stable and transition regions of the signal can be identified more accurately.
[0062] The valid data judgment circuit 20 is connected to the output terminal of the multiplexing circuit 13, such as... Figure 9As shown, specifically, it includes a series of detection circuits connected in sequence, namely, the first-stage detection circuit, whose input terminals are connected to the upper edge sequence 1 and the lower edge sequence 1 respectively; the second-stage detection circuit, whose input terminals are connected to the upper edge sequence 2 and the lower edge sequence 2 respectively; and so on, the Nth-stage detection circuit, whose input terminals are connected to the upper edge sequence N and the lower edge sequence N respectively.
[0063] Since metastable sampling results can be either 0 or 1, sampling results from only one phase's rising or falling edge cannot distinguish whether stable data is in the rising or falling edge. Therefore, to differentiate this situation, it is necessary to use a combination of rising and falling edge sampling sequences of different phases for comprehensive judgment. Thus, as shown in the valid data judgment circuit diagram, a hierarchical circuit is used to detect rising and falling edge sequence pairs separately. When the first-stage detection circuit detects a change from 0 to 1, it enables subsequent stages of detection circuits to determine whether stable data is in the rising or falling edge. Finally, an enable signal is generated to drive the data sampling circuit 30 to continuously sample the read data.
[0064] A comprehensive judgment is made by using sampling sequences of rising and falling edges with different phases. By using multiple sampling points (i.e., multiple phases) that are closely arranged in time, the transition process of the signal can be "captured" and stable levels / data can be identified.
[0065] Specifically, the first-stage detection circuit detects the upper edge sequence 1 and the lower edge sequence 1. If a change of "0,1" in the level signal is detected, it may mean that the valid data read signal has transitioned from low to high.
[0066] Therefore, the first-stage detection circuit enables the second-stage detection circuit to perform detection, and so on. Once subsequent stages are enabled, they continue to detect the sampling sequence of their respective phases. Since these sequences are sampled by clocks of different phases, they provide a more detailed view of the signal on the time axis. By comparing the sampling results of adjacent or multiple phases, the valid data determination circuit can determine whether stable data is in the rising or falling edge. Finally, an enable signal is generated to drive the data sampling circuit 30 to continuously sample the read data.
[0067] The generated enable signal drives the data sampling circuit 30 to continuously sample the read data. This means that sampling of the actual data will only begin after the valid data judgment circuit 20 confirms that the data is stable and reliable, thereby avoiding sampling uncertain or invalid data and ensuring the integrity and accuracy of the data.
[0068] This hierarchical detection and comprehensive judgment method enables asynchronous data access interface devices to:
[0069] Robust handling of metastability: Improves the robustness of handling metastability in asynchronous interfaces, ensuring the reliability of data synchronization.
[0070] Accurately identify the effective data window: Through multi-phase sampling and step-by-step judgment, it is possible to more accurately find the moment when the data is stable and effective.
[0071] Optimized power consumption: The data sampling circuit 30 is only triggered when valid data is identified, avoiding invalid sampling operations and thus reducing system power consumption.
[0072] The timing of the data sampling circuit 30 is as follows: Figure 10 As shown, when the rising edge sampling detects the 0,1 sequence first, the data reading sampling time is the first falling edge after the clk_pn distance from the sampling interval; when the falling edge sampling detects the 0,1 sequence first, the data reading sampling time is the first rising edge after the clk_pn distance from the sampling interval. Regardless of the timing, the clock edge from which the subsequent synchronization circuit obtains the data is the next rising edge after the data reading sampling time.
[0073] This implementation provides an asynchronous data access method, such as... Figure 11 As shown, it includes:
[0074] The valid data signal is sampled based on the rising and falling edges of the clock to generate rising edge sampling sequences and falling edge sampling sequences.
[0075] The first valid data is determined based on the rising edge sampling sequence and the falling edge sampling sequence, and a trigger signal is generated; and
[0076] Based on the trigger signal, the read data signal is sampled to obtain stable data synchronized with the clock.
[0077] It should be noted that in this embodiment, the rising edge is also called the upper edge, and the falling edge is also called the lower edge.
[0078] This asynchronous data access method enables continuous asynchronous data reading in clockless data source scenarios. Furthermore, it achieves asynchronous data reading without the need for pre-sampling of multi-bit read data, effectively reducing power consumption. This method is particularly suitable for near-memory computing architectures on edge devices, significantly improving the performance and energy efficiency of large model inference, and is applicable to edge devices such as AI smartphones and AIPCs.
[0079] Optionally, in this embodiment, determining the first valid data based on the rising edge sampling sequence and the falling edge sampling sequence, and generating a trigger signal, includes:
[0080] If metastable data appears in the sampling results of the rising edge sampling sequence, determine whether stable data appears based on the falling edge sampling sequence; and
[0081] If metastable data appears in the sampling results of the falling edge sampling sequence, determine whether stable data appears based on the rising edge sampling sequence.
[0082] Optionally, valid data is sampled based on the rising and falling edges of the clock to generate rising edge sampling sequences and falling edge sampling sequences, including:
[0083] Generate multiple clock signals clk_p0, clk_p1, ..., clk_pn with different phases; and
[0084] Based on the multiple clock signals with different phases, the input data is sampled to obtain multiple sets of rising edge sampling sequences and falling edge sampling sequences p0, p1, ..., pn.
[0085] Optionally, determining the first valid data based on the rising edge sampling sequence and the falling edge sampling sequence, and generating a trigger signal, further includes:
[0086] In response to the detection of metastable data in a set of rising-edge and falling-edge sampling sequences, the next set of rising-edge and falling-edge sampling sequences is detected to determine whether the metastable data appears at the rising or falling edge; and
[0087] If the metastable data is determined to appear on the rising edge, the data reading sampling time is the first falling edge of clk_pn after the sampling interval. If the metastable data is determined to appear on the falling edge, the data reading sampling time is the first rising edge of clk_pn after the sampling interval.
[0088] Optionally, the data sampling circuit 30 is connected to the subsequent synchronization circuit 200, which acquires data at the next rising edge of the data sampling time.
[0089] Optionally, this embodiment provides an end-side device that applies the asynchronous data access method described above, or the asynchronous data access interface device 100 described above.
[0090] Optionally, the end-side device provided in this embodiment is specifically an AI mobile phone or an AI PC.
[0091] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.
Claims
1. An asynchronous data access interface device, characterized in that, include: The rising and falling edge clock sampling circuit samples the read data based on the rising and falling edges of the clock, respectively, to generate rising edge sampling sequences and falling edge sampling sequences. A valid data determination circuit is connected to the rising and falling edge clock sampling circuit. Based on the rising edge sampling sequence and the falling edge sampling sequence, it determines the first valid data and generates a trigger signal. as well as A data sampling circuit, connected to the valid data judgment circuit, samples the read data based on the trigger signal to obtain stable data synchronized with the clock.
2. The asynchronous data access interface device according to claim 1, characterized in that, The rising and falling edge clock sampling circuit includes: The top edge sampling clock includes multiple delay chains with increasing delay time. The input of each delay chain is connected to the clock clk, and the output generates multiple clock signals clk_p1, clk_p2, ..., clk_pn with different phases. The lower-edge sampling clock includes an inverter and a multi-path delay chain with increasing delay times. The input of the inverter is connected to the clock clk, and the input of each multi-path delay chain is connected to the output of the inverter. The outputs generate multiple clock signals clk_inv_p1, clk_inv_p2, ..., clk_inv_pn with different phases. A multi-channel sampling circuit, each sampling circuit including a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop. The input terminals of the first and second flip-flops are configured to receive a valid read data signal. The clock terminals of the first and third flip-flops are configured to be connected to clk_p1, clk_p2, ..., clk_pn, respectively. The clock terminals of the second and fourth flip-flops are configured to be connected to clk_inv_p1, clk_inv_p2, ..., clk_inv_pn, respectively. The output terminals of the first and third flip-flops form upper edge sequences 1 to N, respectively. The output terminals of the second and fourth flip-flops form lower edge sequences 1 to N, respectively.
3. The asynchronous data access interface device according to claim 1, characterized in that, The valid data judgment circuit includes a multi-stage detection circuit connected in sequence, namely a first-stage detection circuit, a second-stage detection circuit, ..., an Nth-stage detection circuit. The input terminals of the first-stage detection circuit are respectively connected to the upper edge sequence 1 and the lower edge sequence 1; the input terminals of the second-stage detection circuit are respectively connected to the upper edge sequence 2 and the lower edge sequence 2; ...; the input terminals of the Nth-stage detection circuit are respectively connected to the upper edge sequence N and the lower edge sequence N.
4. An end-side device, characterized in that, The asynchronous data access interface device according to any one of claims 1-3.
5. The end-side device according to claim 4, characterized in that, The terminal device is an AI mobile phone or an AI PC.