High speed communication device

Abstract

The embodiment of the application discloses a high-speed communication device, comprising: a communication coupler module, comprising a first MCU module, a first FPGA chip and a first backplane communication interface, the first MCU module and the first FPGA chip being connected through a parallel bus; at least one IO submodule, each IO submodule comprising a second MCU module, a second FPGA chip and a second backplane communication interface, the second MCU module and the second FPGA chip being connected through a parallel bus; and a high-speed serial backplane, connected with the first backplane communication interface and the second backplane communication interface of each IO submodule through differential signal lines.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a high-speed communication device. Background Technology

[0002] In current industrial communication systems, the interconnection between the main control equipment and field equipment mainly adopts dedicated couplers or protocol conversion gateways, but both of these methods have obvious technical limitations.

[0003] Dedicated coupler solutions typically only support a single vendor's specific communication protocol, preventing direct interconnection between master control devices and field devices from different vendors. When the communication device needs to be expanded, multiple couplers supporting different protocols must be configured, which not only significantly increases hardware costs but also complicates the overall architecture of the communication device.

[0004] While protocol conversion gateway solutions can achieve the conversion between different protocols, their reliance on software processing inevitably introduces significant communication latency, making it difficult to meet the needs of industrial automation scenarios with stringent real-time requirements, such as motion control. Utility Model Content

[0005] This application discloses a high-speed communication device that effectively improves the data transmission rate and stability of the high-speed communication device by adopting a standardized high-speed serial backplane and an FPGA-based hardware-accelerated communication structure.

[0006] This application provides a high-speed communication device, including: a communication coupler module, comprising a first MCU module, a first FPGA chip, and a first backplane communication interface, wherein the first MCU module and the first FPGA chip are connected via a parallel bus; at least one I / O submodule, each I / O submodule comprising a second MCU module, a second FPGA chip, and a second backplane communication interface, wherein the second MCU module and the second FPGA chip are connected via a parallel bus; and a high-speed serial backplane, which is connected to the first backplane communication interface and the second backplane communication interface of each I / O submodule via differential signal lines.

[0007] In one possible implementation, the first FPGA chip includes:

[0008] The instruction generation module is used to generate coupler instructions, which include broadcast instructions or unicast instructions.

[0009] The physical layer transceiver module integrates a high-speed serial communication IP core, and the output of the instruction generation module is connected to the input of the physical layer transceiver module.

[0010] The first backplane communication interface includes:

[0011] The instruction sending port is connected to the output of the physical layer transceiver module. The instruction sending port is used to send the coupler instruction to the second backplane communication interface of the at least one IO submodule through the high-speed serial backplane.

[0012] In one possible implementation, the first FPGA chip includes a first interrupt signal generation circuit;

[0013] The input terminal of the first interrupt signal generation circuit is connected to the data receiving terminal of the physical layer transceiver module, and the output terminal of the first interrupt signal generation circuit is connected to the interrupt pin of the first MCU module.

[0014] The first interrupt signal generation circuit generates an electrical signal when it receives response data from the at least one IO submodule to the coupler instruction.

[0015] In one possible implementation, the second FPGA chip includes a second interrupt signal generation circuit;

[0016] The input terminal of the second interrupt signal generation circuit is connected to the instruction receiving port of the second backplane communication interface, and the output terminal of the second interrupt signal generation circuit is connected to the interrupt pin of the second MCU module.

[0017] The second interrupt signal generation circuit generates an electrical signal when it receives the coupler command.

[0018] In one possible implementation, the first FPGA chip includes:

[0019] A CRC check module, wherein the input of the CRC check module is connected to the data receiving end of the physical layer transceiver module;

[0020] The output terminal of the CRC verification module is connected to the verification pin of the first MCU module, and the data output terminal of the CRC verification module is connected to the parallel bus of the first MCU module.

[0021] In one possible implementation, the first FPGA chip includes:

[0022] A data filtering module, wherein the input of the data filtering module is connected to the data receiving end of the physical layer transceiver module, and the output of the data filtering module is connected to the input of the CRC check module.

[0023] In one possible implementation, the second FPGA chip includes:

[0024] The input data buffer module is connected to the data output interface of the second MCU module;

[0025] The instruction parsing module is connected to the instruction receiving port of the second backplane communication interface;

[0026] A data response module is provided, which is used to output response data to the coupler command. The data response module includes a first input terminal and a second input terminal. The first input terminal is connected to the command parsing module, the second input terminal is connected to the input data buffer module, and the output terminal of the data response module is connected to the data transmission port of the second backplane communication interface.

[0027] In one possible implementation, the second FPGA chip includes:

[0028] A parameter configuration cache module, wherein the input end of the parameter configuration cache module is connected to the configuration receiving port of the second backplane communication interface;

[0029] The parameter output terminal of the parameter configuration cache module is connected to the parallel bus of the second MCU module, and the flag output terminal of the parameter configuration cache module is connected to the interrupt pin of the second MCU module.

[0030] In one possible implementation, the second FPGA chip includes:

[0031] An output data buffer module, wherein the input end of the output data buffer module is connected to the output command port of the second backplane communication interface;

[0032] The data output terminal of the output data buffer module is connected to the input bus of the second MCU module, and the synchronization trigger terminal of the output data buffer module is connected to the interrupt pin of the second MCU module.

[0033] In one possible implementation, the second FPGA chip includes:

[0034] A status register module is provided, which is used to update the operating status of the IO module. The status update terminal of the status register module is connected to the status update interface of the second MCU module.

[0035] The status feedback terminal of the status register module is connected to the status transmission port of the second backplane communication interface, and the exception flag terminal of the status register module is connected to the status interrupt pin of the second MCU module.

[0036] In one possible implementation, the input data cache module is used to cache ID information. When the IO module is powered on, the second MCU module writes the ID information into the parameter configuration cache module via a parallel bus. The second MCU module can also write the ID information into the output data cache module via an output instruction.

[0037] Compared with the prior art, the beneficial effects of this application are:

[0038] The high-speed communication device provided in this application embodiment configures FPGA chips in the communication coupler module and the IO submodule respectively, and connects the communication coupler module and the IO submodule through a high-speed serial backplane. This enables high-speed data transmission between the communication coupler module (such as PLCs or industrial control computers from different manufacturers) and between the IO submodules (such as sensors, actuators, and other terminal devices from different manufacturers). The introduction of FPGA chips not only improves the speed of internal communication on the parallel bus, but also enables complex protocol processing, data caching, and state management logic. This improves the high-speed communication device's performance in handling large amounts of data and high-speed communication, while ensuring low latency in data processing and real-time communication. This fully meets the stringent real-time requirements of different controlled objects (such as motion control). By increasing the number of IO submodules, the number of IO points and functions of the high-speed communication device can be easily expanded to adapt to application scenarios of different scales and complexities, giving the high-speed communication device good scalability. Simultaneously, the communication coupler module in the high-speed communication device supports multiple fieldbus and industrial Ethernet protocols, enabling smooth communication with upstream devices and IO submodules from different manufacturers, effectively solving the compatibility problem of interconnecting multiple manufacturers' devices in industrial settings.

[0039] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the structure of a high-speed communication device provided in an embodiment of this application;

[0042] Figure 2 This application provides a schematic diagram of the structure of a communication coupler module in a high-speed communication device.

[0043] Figure 3 This is a schematic diagram of the IO submodule structure in a high-speed communication device provided in an embodiment of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0046] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0047] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0048] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, elements, or components. Unless otherwise stated, "a plurality of" means two or more.

[0049] like Figure 1 As shown in the figure, this application provides a high-speed communication device, which includes: a communication coupler module, at least one IO submodule and a high-speed serial backplane.

[0050] The communication coupler module serves as the control and communication core of the entire high-speed communication device, acting as the main control device (or host) to connect to the next level of equipment (such as a PLC or industrial computer). Figure 2 As shown, the communication coupler module integrates a first MCU module, a first FPGA chip, and a first backplane communication interface. The first MCU module may include an MCU chip (Microcontroller Unit), and the first FPGA chip may be a Field-Programmable Gate Array (FPGA) integrated circuit chip. The first FPGA chip may integrate a high-speed serial communication IP core to implement data filtering, physical layer transmit / receive control, and CRC check functions.

[0051] The first MCU module and the first FPGA chip communicate via a parallel bus. The first MCU module is responsible for handling the fieldbus communication protocol with the upstream device, such as parsing and generating data packets and managing connection status. The first MCU module is also used for operational control of the first FPGA chip.

[0052] The first MCU module and the first FPGA chip are linked via a parallel bus. This means that the parallel bus allows the first MCU module to transmit multiple bits of data to the first FPGA chip simultaneously. Compared to serial transmission, the parallel data transmission method between the first MCU module and the first FPGA chip can achieve a higher data transmission rate at the same clock frequency. The high-speed parallel bus communication capability enables the communication coupler module to quickly respond to its instructions and efficiently generate and distribute control instructions to various IO submodules.

[0053] The first backplane communication interface is the physical connection interface between the communication coupler module and the high-speed serial backplane, enabling high-speed data transmission between the communication coupler module and the IO submodule. The first backplane communication interface includes a command sending port and a data receiving port, which are respectively connected to the differential signal line groups on the high-speed serial backplane used for downlink and uplink communication.

[0054] High-speed communication devices can be configured with multiple I / O submodules. I / O submodules can be considered as slave devices (e.g., sensors, actuators, instruments, or other terminal devices that require data acquisition or control via I / O submodules). Figure 3As shown, each IO submodule includes a second MCU module, a second FPGA chip, and a second backplane communication interface. The second MCU module may include an MCU chip (Microcontroller Unit), which is mainly responsible for acquiring sensor data connected to the IO submodule. The second FPGA chip can be a Field-Programmable Gate Array (FPGA) integrated circuit chip. The second FPGA chip may include functional modules such as an input data buffer module, an instruction parsing module, and a data response module.

[0055] The second MCU module and the second FPGA chip communicate via a parallel bus. The second MCU module controls the operating logic of the I / O submodule. Simultaneously, the second MCU module also controls the operation of the second FPGA chip.

[0056] The second backplane communication interface is the physical connection interface between a single I / O module and the high-speed serial backplane. It includes an instruction receive port and a data transmit port, used to realize high-speed data transmission between the communication coupler module and the I / O sub-module. The second MCU module communicates with the second FPGA chip at high speed via a parallel bus, enabling the I / O sub-module to quickly acquire data and rapidly respond to control commands from the communication coupler module, executing corresponding control actions.

[0057] The high-speed serial backplane serves as the physical connection foundation for the communication coupler module and various I / O submodules. To achieve high-speed and reliable data transmission, the high-speed serial backplane employs differential signal transmission technology. In its implementation, the high-speed serial backplane includes at least two pairs of differential signal lines for downlink communication and at least two pairs of differential signal lines for uplink communication.

[0058] For downlink communication, the high-speed serial backplane completes data transmission through a first set of differential signal pairs. One end of the differential signal line in the first set of differential signal pairs is connected to the transmitting end of the first backplane communication interface of the communication coupler module. The other end of the differential signal line in the first set of differential signal pairs is connected to the receiving end of the second backplane communication interface of each IO submodule. The communication coupler module can transmit downlink commands or data packets (e.g., coupler commands, configuration parameters) to each IO submodule simultaneously or on demand through the first FPGA chip. Downlink commands and data packets arrive at the second backplane communication interface of each IO submodule via the first FPGA chip, the first backplane communication interface, and the first set of differential signal pairs, and are then parsed and executed by the second FPGA chip.

[0059] For uplink communication, the high-speed serial backplane completes data transmission through a second set of differential signal pairs. One end of the differential signal lines in the second set of differential signal pairs is connected to the receiving end of the first backplane communication interface of the communication coupler module. The other end of the differential signal lines in the second set of differential signal pairs is connected to the transmitting end of the second backplane communication interface of each IO submodule. Each IO submodule can upload the collected data, operating status information, or response data to downlink commands back to the communication coupler module through the second set of differential signal pairs. The data and status information from the IO submodules are processed by the second FPGA chip, the second backplane communication interface, and the second set of differential signal pairs, and then converged to the first backplane communication interface of the communication coupler module, where they are further processed by the first FPGA chip and the first MCU module.

[0060] By configuring the downlink and uplink differential signal lines of the high-speed serial backplane, the high-speed serial backplane provides bidirectional, high-speed, and interference-resistant data transmission capabilities between the communication coupler module and multiple IO sub-modules, enabling the high-speed communication device to meet the requirements of high-speed communication and real-time performance in industrial settings.

[0061] Thus, the high-speed communication device provided in this application embodiment, by configuring FPGA chips in the communication coupler module and the IO submodule respectively, and connecting the communication coupler module and the IO submodule through a high-speed serial backplane, enables high-speed data transmission between communication coupler modules (such as PLCs or industrial control computers from different manufacturers) and between IO submodules (such as sensors, actuators, and other terminal devices from different manufacturers). The introduction of FPGA chips not only improves the speed of internal communication on the parallel bus, but also enables complex protocol processing, data caching, and state management logic, thereby improving the high-speed communication device's performance in handling large amounts of data and high-speed communication, while ensuring low latency in data processing and real-time communication, fully meeting the stringent real-time requirements of different controlled objects (such as motion control). By increasing the number of IO submodules, the number of IO points and functions of the high-speed communication device can be easily expanded to adapt to application scenarios of different scales and complexities, giving the high-speed communication device good scalability. Meanwhile, the communication coupler module in the high-speed communication device supports multiple fieldbus and industrial Ethernet protocols, enabling it to communicate smoothly with upstream devices and IO submodules from different manufacturers, effectively solving the compatibility problem of interconnecting multiple manufacturers' devices in the industrial field.

[0062] like Figure 2As shown, in some embodiments, the first FPGA chip includes an instruction generation module and a physical layer transceiver module. The first FPGA chip also includes a first backplane communication interface. The instruction generation module is responsible for generating coupler instructions to be sent to the IO submodule. The generation of coupler instructions is based on the control logic of the first MCU module or the internal state of the first FPGA chip itself. The instruction generation module can generate various types of coupler instructions to adapt to different control requirements.

[0063] Coupler commands can specifically include broadcast commands. Broadcast commands are simultaneously sent by the communication coupler module to all I / O submodules connected to the high-speed serial backplane. For example, broadcast commands can be used to notify all submodules to periodically report data, enter a preset operating mode, or can be synchronous execution commands. Synchronous execution commands are used by the communication coupler module to require all I / O submodules connected to the high-speed serial backplane to execute the synchronous execution command simultaneously according to a preset timing or logic after receiving it. For example, in applications requiring multiple actuators to coordinate their actions to complete precise motion control, the communication coupler module can issue synchronous execution commands to ensure that the actuators controlled by all relevant I / O submodules start and stop according to precise timing relationships, thereby guaranteeing the coordination and accuracy of the actions.

[0064] Coupler commands can specifically include unicast commands. Unicast commands are sent to a specific I / O submodule connected to a high-speed serial backplane. For example, when it is necessary to read real-time data from a specific sensor (connected to a specific I / O submodule), or to control the action of only a specific actuator (connected to a specific I / O submodule), the communication coupler module will issue a unicast command.

[0065] like Figure 2 As shown, in order to achieve high-speed and stable data transmission between the first FPGA chip and the high-speed serial backplane, in some embodiments, a physical layer transceiver module may be integrated within the first FPGA chip.

[0066] The physical layer transceiver module integrates a high-speed serial communication IP core, which is a proven functional module specifically designed for handling high-speed serial data transmission and reception. The high-speed serial communication IP core can efficiently complete the conversion between parallel data and serial data, and handle related physical layer protocols such as clock recovery and data encoding and decoding.

[0067] Specifically, the transmitting end of the physical layer transceiver module is connected to the instruction generation module. When the first FPGA chip needs to send a coupler instruction to the I / O submodule, the coupler instruction is transmitted to the physical layer transceiver module through the instruction generation module. Then, the IP core inside the physical layer transceiver module performs serialization processing and sends it to the I / O submodule through a high-speed serial backplane.

[0068] Meanwhile, the receiving end of the physical layer transceiver module is connected to the data receiving port of the first backplane communication interface. Thus, response data (e.g., sensor readings, status information, etc.) uploaded from the IO submodule via the high-speed serial backplane is received by the physical layer transceiver module. After serial-to-parallel conversion and clock synchronization processing by the IP core of the physical layer transceiver module, the data is output to the data receiving port of the first backplane communication interface. The processed data can then follow the path described above, passing through the data filtering module and the CRC check module, before being output to the first MCU module.

[0069] Thus, the instruction generation module of the first FPGA chip can send unicast or broadcast instructions, giving the communication coupler module control flexibility to meet the complex and ever-changing control needs of industrial sites. By integrating a physical layer transceiver module, the first FPGA chip can reliably utilize a high-speed serial backplane for data transmission. Whether sending coupler instructions to the IO submodule or receiving response data from the IO submodule, it features high bandwidth and low latency data transmission, thereby ensuring the data transmission performance of the entire high-speed communication device.

[0070] To ensure that the communication coupler module can respond promptly to feedback information from the IO submodule, in some embodiments, such as Figure 2 As shown, the first FPGA chip includes a first interrupt signal generation circuit. The first interrupt signal generation circuit is used to improve the response speed and real-time performance of the high-speed communication device.

[0071] The input of the first interrupt signal generation circuit is connected to the data receiving end of the physical layer transceiver module. The data receiving end of the physical layer transceiver module is used to receive response data uploaded from each IO submodule via the high-speed serial backplane. The response data is the IO submodule's response to the coupler command sent by the communication coupler module, and may contain the IO submodule's status information, command execution results, or other feedback.

[0072] The output of the first interrupt signal generation circuit is connected to the interrupt pin of the first MCU module. The interrupt pin of the first MCU module is a dedicated interface for receiving notifications.

[0073] When the first interrupt signal generation circuit detects that it has received response data from at least one IO submodule, the first interrupt signal generation circuit can quickly generate an electrical signal with a changing level (i.e., an interrupt signal) and send the signal to the interrupt pin of the first MCU module.

[0074] When the interrupt pin of the first MCU module detects an interrupt signal, it pauses the currently executing main program flow and jumps to execute the pre-set first interrupt routine. In the first interrupt routine, the first MCU module reads and parses the received response data, determines the status of the IO submodule, the execution result, or the uploaded sensor data based on the response data content, and then makes corresponding processing decisions.

[0075] Thus, by setting the first interrupt signal generation circuit in the first FPGA chip, the first MCU module does not need to constantly poll the data receiving port to see if new data has arrived, which improves the efficiency of the high-speed communication device and ensures a fast response to the IO submodule's response data.

[0076] In order for at least one IO submodule to respond promptly to instructions from the communication coupler module, in some embodiments, such as Figure 2 As shown, the second FPGA chip includes a second interrupt signal generation circuit. The input of the second interrupt signal generation circuit is connected to the instruction receiving port of the second backplane communication interface. The instruction receiving port of the second backplane communication interface is used to receive coupler instructions transmitted via a high-speed serial backplane. The coupler instructions may be broadcast instructions or unicast instructions, used to control the IO submodules to execute the operations corresponding to the coupler instructions.

[0077] The output of the second interrupt signal generation circuit is connected to the interrupt pin of the second MCU module. The interrupt pin of the second MCU module is the interface through which the second MCU module receives notification events (such as the event that the second interrupt signal generation circuit receives a coupler command).

[0078] Once the interrupt pin of the second MCU module detects the interrupt signal, it pauses the currently executing main program flow and jumps to execute the pre-set second interrupt routine. During the execution of the second interrupt routine, the second MCU module reads and parses the received coupler instructions, and executes specific application code according to the instruction type and content of the coupler instructions to complete the operations required by the coupler instructions, such as updating the output port status, acquiring sensor data, or performing internal state switching.

[0079] In this way, by setting up a second interrupt signal generation circuit, the second FPGA chip eliminates the need for the second MCU module to constantly poll the instruction receiving port for new instructions, thereby improving the response efficiency of the IO submodule to coupler instructions and ensuring that the high-speed communication device can execute coupler instructions quickly and accurately. This is especially important for industrial automation scenarios with high real-time requirements.

[0080] To ensure the integrity and reliability of the response data received from each IO submodule, in some embodiments, such as Figure 2As shown, the first FPGA chip integrates a CRC (Cyclic Redundancy Check) module. The CRC module is used to ensure the accuracy of data transmission in high-speed communication devices.

[0081] The input of the CRC check module is connected to the data receiver of the physical layer transceiver module. When the IO submodule uploads response data to the data receiver of the physical layer transceiver module through the high-speed serial backplane, the response data can be synchronously sent to the CRC check module for verification.

[0082] The CRC check module calculates the check result based on the received response data. This check result is sent to the check pin of the first MCU module through the check result output terminal of the CRC check module. The first MCU module can read the check result through the check pin to determine whether the received response data was erroneous or corrupted during transmission.

[0083] Meanwhile, valid data verified by the CRC check module is transmitted to the parallel bus of the first MCU module through the data output terminal of the CRC check module. The first MCU module can obtain the verified response data through the parallel bus, determine the status and execution result of the IO submodule based on the content of the response data, and make corresponding processing decisions.

[0084] Thus, by setting a CRC check module in the first FPGA chip and combining it with the first interrupt signal generation circuit, the first MCU module can not only respond quickly to the response data of the IO submodule, but also ensure the accuracy of the response data, thereby improving the communication reliability and stability of the high-speed communication device.

[0085] To further optimize the data processing flow and reduce the data processing burden on the CRC check module and the first MCU module, in some embodiments, such as Figure 2 As shown, the first FPGA chip also integrates a data filtering module. The data filtering module is used to perform preliminary screening of the response data received from the IO submodule.

[0086] The input of the data filtering module is also connected to the data receiving end of the physical layer transceiver module to receive response data. The output of the data filtering module is connected to the input of the CRC check module. All response data entering through the data receiving end of the physical layer transceiver module is processed by the data filtering module before being sent to the CRC check module for integrity verification.

[0087] The data filtering module's data filtering function can be configured according to the system design requirements. For example, the data filtering module can implement one or more of the following filtering logics:

[0088] Protocol frame filtering: Identifies and discards data frames that do not conform to the predetermined communication protocol format, and only passes valid frames that conform to the format to the CRC check module.

[0089] Address filtering: If the response data of the IO submodule contains source address information, the data filtering module can allow only response data from specific addresses or address ranges to pass through, blocking irrelevant or incorrect address source data.

[0090] Preliminary identification of erroneous data: Based on rules such as abnormal data length and missing key fields, the data filtering module can quickly identify obviously erroneous response data and discard it.

[0091] Thus, by configuring a data filtering module on the first FPGA chip, the amount of data that the subsequent CRC check module and the first MCU module need to process can be effectively reduced. The data filtering module can filter out obviously invalid or erroneous data, improve the data processing efficiency of the high-speed communication device, reduce the resource consumption of the high-speed communication device, and further improve the overall performance and stability of the high-speed communication device.

[0092] The second FPGA chip, as the core processing unit of the I / O submodule, is used to receive coupler commands, process data, and generate response data. The second FPGA chip integrates multiple cooperating functional modules. In some embodiments, such as... Figure 3 As shown, the second FPGA chip integrates an input data buffer module, an instruction parsing module, and a data response module.

[0093] The input data buffer module is connected to the data output interface of the second MCU module. The input data buffer module is used to buffer configuration parameters, operating status and ID information, or IO data acquired by the second MCU module (e.g., sensor readings). Through the buffering operation of the input data buffer module, the differences between the data output rate of the second MCU module, the processing rate of the second FPGA chip, and the subsequent high-speed serial backplane transmission rate can be smoothed out, ensuring the continuity and stability of data transmission.

[0094] The instruction parsing module is connected to the instruction receive port of the second backplane communication interface. The instruction parsing module receives coupler instructions sent by the first FPGA chip from the high-speed serial backplane. The module parses the received instructions, identifying the instruction type, target address, and specific operation content of the coupler instruction.

[0095] The data response module executes corresponding operations (e.g., reading local sensor values, updating configuration parameters, etc.) based on the instructions parsed by the instruction parsing module, and generates corresponding response data. The data response module has two input terminals: the first input terminal is connected to the instruction parsing module to receive the parsed instruction information and guide the generation of response data; the second input terminal is connected to the input data buffer module to read configuration or reference data pre-stored by the second MCU module to assist in correcting the response data.

[0096] The response data generated by the data response module is ultimately sent to the data transmission port of the second backplane communication interface through the output of the data response module, so that the response data can be transmitted back to the first FPGA chip through the high-speed serial backplane.

[0097] Thus, through the above modular design, the second FPGA chip can respond to the coupler commands of the communication coupler module efficiently and accurately, realizing reliable data interaction between the IO submodule and the high-speed serial backplane and the communication coupler module.

[0098] In some embodiments, such as Figure 3 As shown, the second FPGA chip also includes a parameter configuration cache module. This module receives and processes configuration data from the high-speed serial backplane. The configuration data can be generated by the configuration generation module in the first FPGA chip and sent to the high-speed serial backplane via the configuration distribution module in the first backplane communication interface.

[0099] Specifically, the input of the parameter configuration cache module is connected to the configuration receiving port of the second backplane communication interface. When the first FPGA chip needs to update the configuration parameters of the IO submodule, it sends configuration data through the high-speed serial backplane. The configuration data is received by the second backplane communication interface and passed to the parameter configuration cache module.

[0100] After receiving the configuration data, the parameter configuration cache module temporarily stores it. Then, the parameter configuration cache module sends the configuration data to the parallel bus of the second MCU module through its parameter output terminal. The MCU determines whether to use the configuration parameters by querying the flag bit of the parameter configuration cache module. Furthermore, when the IO module powers on, the second MCU module writes the ID information into the parameter configuration cache module via the parallel bus.

[0101] The parameter configuration cache module also generates a flag bit, which is connected to the interrupt pin of the second MCU module through its flag bit output. When a new configuration parameter is successfully received and ready for the second MCU module to read, the flag bit output of the parameter configuration cache module will trigger an interrupt signal to the second MCU module, ensuring that the second MCU module can promptly know that the configuration parameter has been updated and take corresponding actions.

[0102] Thus, by introducing a parameter configuration cache module into the second FPGA chip, the reception and processing of configuration data are centrally managed, and the transmission of configuration data is logically separated from the normal data interaction of the IO submodule (such as sensor data reading and coupler instruction execution). This improves the reliability and efficiency of the configuration process, while also reducing the potential interference of configuration updates to other data processing processes of the IO submodule.

[0103] In some embodiments, such as Figure 3 As shown, the second FPGA chip also includes an output data buffer module. This module receives and processes specific control commands from the high-speed serial backplane. These commands are used to trigger or configure the output behavior of the I / O submodules.

[0104] Specifically, the input of the output data buffer module is connected to the output command port of the second backplane communication interface. When the first FPGA chip needs to send a specific control command to the IO submodule, it sends the corresponding specific control command through the high-speed serial backplane. The specific control command is received by the second backplane communication interface and passed to the output data buffer module.

[0105] Upon receiving a specific control command, the output data buffer module temporarily stores it. Subsequently, the output data buffer module sends the specific control command to the parallel bus of the second MCU module through its data output terminal. This allows the second MCU module to read and parse the specific control command, enabling it to perform corresponding control operations to adjust the output behavior. The second MCU module can write ID information into the output data buffer module via output commands and use the output data buffer module for related operations during the I / O module's power-on initialization.

[0106] To ensure the second MCU module can respond promptly to new specific control commands, the output data buffer module is equipped with a synchronization trigger terminal, which is connected to the interrupt pin of the second MCU module. When a new specific control command is successfully received and ready for processing by the second MCU module, the synchronization trigger terminal of the output data buffer module will trigger an interrupt signal to the second MCU module. This ensures the second MCU's rapid response to output operations from the I / O submodule.

[0107] Thus, by introducing an output data buffer module into the second FPGA chip, the reception and processing of specific control commands are centrally managed, and the transmission of specific control commands is logically separated from other data interactions of the IO submodule (such as status feedback and sensor data acquisition). This improves the reliability and efficiency of specific control command processing, while also reducing the potential interference of specific control command updates to other real-time functions of the IO submodule.

[0108] In some embodiments, such as Figure 3As shown, the second FPGA chip includes: a status register module, which is used to update the operating status of the IO module; the status update terminal of the status register module is connected to the status update interface of the second MCU module; the status feedback terminal of the status register module is connected to the status transmission port of the second backplane communication interface; and the exception flag terminal of the status register module is connected to the status interrupt pin of the second MCU module.

[0109] In this embodiment, the second FPGA chip receives specific control instructions from the first FPGA chip and controls the output behavior of the I / O submodule according to the specific control instructions, such as driving relays or switching outputs. Simultaneously, the second FPGA chip is also responsible for acquiring the input signals of the I / O submodule.

[0110] When it is necessary to feed back the acquired input signal or the current status of the I / O submodule to the communication coupler module, the status register module inside the second FPGA chip within the I / O submodule is activated. The status register module receives a status update signal from the second MCU module via a status update terminal. This status update signal contains the latest data processed or collected by the second MCU module, or the operating status information of the I / O submodule. Subsequently, the status register module performs an internal status update.

[0111] After the status register module completes its update, its status feedback terminal sends the updated status information to the status transmission port of the second backplane communication interface for real-time response to the status query of the communication coupler module. The second backplane communication interface then transmits the status information to the status receiving port in the first backplane communication interface via a high-speed serial backplane.

[0112] If an anomaly is detected during the status update process (e.g., data overflow, timeout), the status register module will send an interrupt signal to the second MCU module via the anomaly flag terminal, so that the second MCU module can perform corresponding error handling or status reporting. If an anomaly is detected during the status update or I / O submodule operation (e.g., input signal exceeding limits, output failure), the status register module will send an interrupt signal to the status interrupt pin of the second MCU module via its anomaly flag terminal. After receiving the interrupt signal, the second MCU module can execute the corresponding anomaly handling program, such as logging errors or notifying the communication coupler module to take protective measures.

[0113] Specific control commands are generated by the first FPGA chip of the communication coupler module and sent to the high-speed serial backplane via the first backplane communication interface. These commands are then transmitted through the high-speed serial backplane to the second backplane communication interface of the IO submodule, where they are finally received and processed by the second FPGA chip, ensuring timely execution. Status feedback data is fed back via a different path: it is generated or collected internally by the IO submodule (e.g., processed by the second MCU module), updated by the status register module, and then sent to the high-speed serial backplane via the second backplane communication interface of the IO submodule. From there, it is transmitted to the first backplane communication interface of the communication coupler module and finally received by the first FPGA chip. These two processes operate independently in terms of physical path and logical processing, ensuring the stability and reliability of data transmission throughout the high-speed communication device.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A high-speed communication device, characterized in that, include: The communication coupler module includes a first MCU module, a first FPGA chip, and a first backplane communication interface, wherein the first MCU module and the first FPGA chip are connected via a parallel bus. At least one IO submodule, each IO submodule including a second MCU module, a second FPGA chip and a second backplane communication interface, wherein the second MCU module and the second FPGA chip are connected via a parallel bus; A high-speed serial backplane is connected to the first backplane communication interface and the second backplane communication interface of each of the IO submodules via differential signal lines.

2. The high-speed communication device according to claim 1, characterized in that, The first FPGA chip includes: The instruction generation module is used to generate coupler instructions, which include broadcast instructions or unicast instructions. The physical layer transceiver module integrates a high-speed serial communication IP core, and the output of the instruction generation module is connected to the physical layer transceiver module. The first backplane communication interface includes: The instruction sending port is connected to the output of the physical layer transceiver module. The instruction sending port is used to send the coupler instruction to the second backplane communication interface of the at least one IO submodule through the high-speed serial backplane.

3. The high-speed communication device according to claim 2, characterized in that, The first FPGA chip includes a first interrupt signal generation circuit; The input terminal of the first interrupt signal generation circuit is connected to the data receiving terminal of the physical layer transceiver module, and the output terminal of the first interrupt signal generation circuit is connected to the interrupt pin of the first MCU module.

4. The high-speed communication device according to claim 2, characterized in that, The second FPGA chip includes a second interrupt signal generation circuit; The input terminal of the second interrupt signal generation circuit is connected to the instruction receiving port of the second backplane communication interface, and the output terminal of the second interrupt signal generation circuit is connected to the interrupt pin of the second MCU module.

5. The high-speed communication device according to claim 2, characterized in that, The first FPGA chip includes: A CRC check module, wherein the input of the CRC check module is connected to the data receiving end of the physical layer transceiver module; The output terminal of the CRC verification module is connected to the verification pin of the first MCU module, and the data output terminal of the CRC verification module is connected to the parallel bus of the first MCU module.

6. The high-speed communication device according to claim 5, characterized in that, The first FPGA chip includes: A data filtering module, wherein the input end of the data filtering module is connected to the data receiving end of the physical layer transceiver module, and the output end of the data filtering module is connected to the input end of the CRC verification module and the instruction generation module.

7. The high-speed communication device according to any one of claims 2 to 6, characterized in that, The second FPGA chip includes: The input data buffer module is connected to the data output interface of the second MCU module; The instruction parsing module is connected to the instruction receiving port of the second backplane communication interface; A data response module is provided, which is used to output response data to the coupler command. The data response module includes a first input terminal and a second input terminal. The first input terminal is connected to the command parsing module, the second input terminal is connected to the input data buffer module, and the output terminal of the data response module is connected to the data transmission port of the second backplane communication interface.

8. The high-speed communication device according to any one of claims 1 to 6, characterized in that, The second FPGA chip includes: A parameter configuration cache module, wherein the input end of the parameter configuration cache module is connected to the configuration receiving port of the second backplane communication interface; The parameter output terminal of the parameter configuration cache module is connected to the parallel bus of the second MCU module, and the flag output terminal of the parameter configuration cache module is connected to the interrupt pin of the second MCU module.

9. The high-speed communication device according to any one of claims 1 to 6, characterized in that, The second FPGA chip includes: An output data buffer module, wherein the input end of the output data buffer module is connected to the output command port of the second backplane communication interface; The data output terminal of the output data buffer module is connected to the input bus of the second MCU module, and the synchronization trigger terminal of the output data buffer module is connected to the interrupt pin of the second MCU module.

10. The high-speed communication device according to any one of claims 1 to 6, characterized in that, The second FPGA chip includes: A status register module is provided, which is used to update the running status of the IO submodule. The status update terminal of the status register module is connected to the status update interface of the second MCU module. The status feedback terminal of the status register module is connected to the status transmission port of the second backplane communication interface, and the exception flag terminal of the status register module is connected to the status interrupt pin of the second MCU module.

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