A low VF PIN rectifier diode

Abstract

The utility model discloses a low VF PIN rectifier diode, including from below and above set gradually back metal layer, N+ substrate, N-epitaxial layer, P+ injection area, ohm contact area and front metal layer, N-epitaxial layer and P+ injection area side part are equipped with groove respectively, be equipped with on the groove: insulating polycrystal, from P+ injection area top surface along the groove and extend to N-epitaxial layer, SiO2 protection layer, from the insulating polycrystal top surface and extend after falling to N-epitaxial layer side portion to with Insulating polycrystal is connected, glass passivation layer is set between SiO2 protection layer and insulating polycrystal. The utility model has improved the reliability and stability of product, makes it in the application scene of low power consumption, high efficiency and shows outstanding performance.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a low VF PIN rectifier diode. Background Technology

[0002] A diode is a two-terminal semiconductor device with a PN junction, containing an anode and a cathode. It exhibits unidirectional conductivity, allowing current to flow only from the anode to the cathode while preventing reverse flow. Its main functions include rectifying alternating current (AC) to direct current (DC), achieving unidirectional signal conversion, and serving as a switching element in circuits.

[0003] A PIN rectifier diode is a special type of semiconductor diode, named for its three-layer structure: a P-type layer, an intrinsic semiconductor layer (I-layer), and an N-type layer. It achieves unique electrical characteristics by introducing a lightly doped intrinsic semiconductor layer (I-layer) and is primarily used in high-frequency rectification, radio frequency switching, and signal control.

[0004] With the continuous development of electronic technology, the application of PIN rectifier diodes is becoming increasingly widespread. Currently, however, significant issues remain regarding the voltage drop (VF) of PIN rectifier diodes. Conventional PIN rectifier diode designs exhibit high forward voltage drops, leading to high operating losses and low efficiency. In applications with stringent low-power requirements, the increased temperature rise of these traditional designs severely impacts equipment performance and lifespan, demonstrating significant drawbacks.

[0005] Therefore, how to effectively reduce the forward voltage drop of PIN rectifier diodes and improve their working efficiency while maintaining high reliability is a technical challenge that the industry urgently needs to solve. Utility Model Content

[0006] To address the above problems, this invention provides a low-VF PIN rectifier diode that effectively reduces the forward voltage drop and improves the working efficiency of the PIN rectifier diode while maintaining high reliability.

[0007] The technical solution of this utility model is: A low VF PIN rectifier diode includes, from bottom to top, a back metal layer, an N+ substrate, an N- epitaxial layer, a P+ implantation region, an ohmic contact region, and a front metal layer; The N-epilithographic layer and the P+ implantation region are respectively provided with trenches; the trenches are provided with: Insulating polycrystalline silicon extends downward from the top surface of the P+ implantation region along the trench to the N- epitaxial layer; The SiO2 protective layer extends upward from the top surface of the insulating polycrystalline silicon and falls to the side of the N-epitaxial layer, where it connects with the insulating polycrystalline silicon. A glass passivation layer is disposed between the SiO2 protective layer and the insulating polycrystalline silicon.

[0008] Specifically, the resistivity of the N+ substrate is 3-10 Ω·cm, and the thickness is 10-30 μm.

[0009] Specifically, the thickness of the insulating polycrystalline silicon is 3000-8000 angstroms.

[0010] Specifically, the glass passivation layer extends downward from the top of the insulating polycrystalline silicon to the side region of the N-epitaxial layer.

[0011] Specifically, the thickness of the glass passivation layer is 50-80 μm.

[0012] Specifically, the thickness of the SiO2 protective layer is 3000-9000 angstroms.

[0013] Specifically, the insulating polycrystalline silicon is connected to the front metal layer, the ohmic contact region, the P+ implantation region, and the N- epitaxial layer, respectively.

[0014] Specifically, the top surface of the front metal layer is located below the top of the SiO2 protective layer.

[0015] This invention forms a stable ohmic contact region between the front metal layer and the P+ implantation region, significantly reducing the forward voltage drop (VF) of the device, thereby effectively reducing operating losses and improving operating efficiency. Furthermore, the N-epitaxial layer and the P+ implantation region are sequentially connected with insulating polysilicon, a glass passivation layer, and a SiO2 protective layer, which significantly improves the reliability and stability of the product, enabling it to perform excellently in low-power, high-efficiency applications. This invention achieves a VF of 0.875V with a 140mil size, representing a 15.1% reduction in size and superior performance. In terms of cost, the size reduction increases the number of chips per wafer by 40%, and the cost of aluminum is only 1 / 20th that of gold and silver, resulting in a significant reduction in unit cost. Attached Figure Description

[0016] Figure 1 This is a structural schematic diagram of step one of this utility model; Figure 2 This is a structural schematic diagram of step two of this utility model; Figure 3 This is a structural schematic diagram of step three of this utility model; Figure 4 This is a structural schematic diagram of step four of this utility model; Figure 5 This is a structural schematic diagram of step five of this utility model; Figure 6 This is a structural schematic diagram of step six of this utility model; Figure 7This is a structural schematic diagram of step seven of this utility model; Figure 8 This is a structural schematic diagram of step eight of this utility model; Figure 9 This is a structural schematic diagram of step nine of this utility model; Figure 10 This is a structural schematic diagram of step ten of this utility model; Figure 11 This is a structural schematic diagram of step eleven of this utility model; In the figure, 1 is insulating polycrystalline silicon, 2 is glass passivation layer, 3 is SiO2 protective layer, 4 is ohmic contact region, 5 is front metal layer, 6 is P+ implantation region, 7 is N- epitaxial layer, 8 is N+ substrate, and 9 is back metal layer. Detailed Implementation

[0017] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0018] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0019] The following is for reference. Figure 1-11 Describe this utility model; A method for fabricating a low-VF PIN rectifier diode includes the following steps: Step 1, oxidation before ion implantation: like Figure 1 As shown, a dense oxide film with a thickness of 300-900 angstroms is grown on the surface of the N-epitaxial layer; Step 2, Oxidation Propulsion: P-type impurities (B13+) are implanted into the N-epitaxial layer via ion implantation, and high-temperature oxidation is performed to further form the P+ implantation region, such as... Figure 2 As shown; the junction depth formed after oxidation must not be less than 13 μm.

[0020] Compared to diffusion-formed P+ regions, ion implantation creates deeper P+ junctions, resulting in high-concentration, steeply distributed P⁺ regions that balance low contact resistance and clear PIN interfaces. Furthermore, it offers higher doping uniformity and depth controllability, leading to better device parameter consistency. It also causes less damage to the intermediate I-region, ensuring the reverse breakdown voltage and leakage current characteristics of the PIN diode.

[0021] Step 3, selective lithography: Selective photolithography is performed on the top surface of the P+ implantation region to regionalize the wafer into grains. The areas to be etched are exposed on the surface of the grains, while the remaining areas are protected with photoresist. Figure 3 As shown; Step 4, trench etching: The silicon region exposed by the P+ implantation region is etched to form trenches extending into the N- epitaxial layer, such as... Figure 4 As shown; The etched PN junction has a depth of 90-110um and a width of 330-380um.

[0022] Step 5: Deposit insulating polycrystalline silicon thin film: Insulating polycrystalline silicon (SiPOS) is deposited on the upper surface using LPCVD, such as Figure 5 As shown; the thickness of the grown semi-insulating polycrystalline silicon (SiPOS) is 3000-8000 angstroms.

[0023] Step Six: Selective Photolithography and Sintering of the Glass Melt: like Figure 6 As shown, selective photolithography is performed on the wafer using photoresist glass, followed by sintering and glass fusion to form a glass passivation layer on silicon insulated polycrystalline silicon (SiPOS). The glass passivation layer extends downwards from the top of the silicon insulated polycrystalline silicon to the side region of the N-epitaxial layer, i.e. Figure 6 The area between the center line and the insulating polycrystalline silicon; the thickness of the glass passivation layer grown in this case is 50-80um.

[0024] Step 7, Deposit LTO thin film: like Figure 7 As shown, a SiO2 protective layer (LTO) is deposited on the wafer surface and the glass passivation layer using LPCVD. The thickness of the SiO2 protective layer is 3000-9000 angstroms.

[0025] The three-layer passivation structure (SIPOS + glass + LTO) of the mesa process solves reliability problems such as surface states, electric field concentration, and contamination erosion of semiconductor mesa from the inside out through the synergistic effect of defect passivation, physical isolation, ion trapping, stress buffering and sealing protection. Ultimately, it achieves the stability and resistance to environmental interference of the device in long-term use, thus significantly improving reliability.

[0026] Step 8, selective photolithography and electrode oxide film: The passivation layer within the grain trenches is protected with photoresist, exposing the passivation film on the mesa and dicing surfaces. The passivation film on the mesa and dicing surfaces is then removed to prepare for PVD sputtering. Figure 8 As shown; Step 9, PVD thin film sputtering: A layer of Al metal is sputtered using PVD, and a high-temperature alloy is then formed to create an ohmic contact region, such as... Figure 9 As shown, the thickness of the sputtered metal layer is 200-500 angstroms.

[0027] The ohmic contact formed between aluminum and the P⁺ implanted region eliminates the contact barrier through the tunneling effect, reduces interface defects through alloying, and accelerates carrier transport through high conductivity, significantly reducing the resistance and voltage loss of current passing through the metal-semiconductor interface, ultimately achieving a reduction in on-state voltage drop (V_F). This mechanism is one of the key processes for optimizing the forward characteristics of devices such as power diodes and rectifiers. The test data for unsputtered aluminum and aluminum-formed aluminum are 0.92V and 0.875V, respectively.

[0028] Step 10, Metallization: Metal is deposited on the front and back sides of the chip using a vapor deposition station to form a front metal layer and a back metal layer, respectively, and the processing is complete.

[0029] In this case, the front metal layer is connected to the ohmic contact area, and the back metal layer is connected to the bottom surface of the N+ substrate. The front metal layer includes Ti, Al, Ti, and Ni layers, and the back metal layer includes Ti, Ni, and Ag layers.

[0030] A low-VF PIN rectifier diode is fabricated by a method for fabricating a low-VF PIN rectifier diode, comprising, from bottom to top, a back metal layer 9, an N+ substrate 8, an N- epitaxial layer 7, a P+ implantation region 6, an ohmic contact region 4, and a front metal layer 5. The cross-sectional lengths of the ohmic contact area 4 and the front metal layer 5 (assuming...) Figure 11 The horizontal section length is less than the section length of the P+ injection zone 6; Trenches are provided on the sides of the N-epitaxy layer 7 and the P+ implantation region 6, respectively; the trenches are provided with: Insulating polycrystalline silicon 1 extends downward from the top surface of P+ implantation region 6 along the trench to N- epitaxial layer 7; The SiO2 protective layer 3 extends upward from the top surface of the insulating polysilicon 1 and falls to the side of the N-epitaxial layer 7, and is connected to the insulating polysilicon 1. The SiO2 protective layer 3 in this case includes a projectile portion and an adhesive portion connected in sequence; The ejection section extends upward from the top surface of the insulating polycrystalline silicon 1 and then falls to the side of the N-epitaxial layer 7; The bonding portion is located on the side of the N-epipolar layer 7 and is connected to the insulating polysilicon 1.

[0031] Traditional PIN diodes exhibit electric field distortion at the PN junction edge, leading to increased reverse leakage current (up to 50-100 nA) and decreased breakdown voltage. This invention addresses this by creating a bonding portion on the N-epitaxial layer 7 side, reducing the edge electric field strength by 30%. Through the electric field shielding effect of the dielectric materials (SiO2 and glass), the electric field peak is transferred from the junction edge to the interior of the passivation layer, effectively suppressing avalanche breakdown.

[0032] Meanwhile, traditional planar passivation layers are prone to ion migration due to etching damage or material defects, resulting in a significant increase in leakage current during high-temperature reverse bias testing. The bonding design in this case creates a three-dimensional encapsulation structure between the glass passivation layer and the insulating polycrystalline silicon. Combined with a 3000-9000 Å SiO2 protective layer deposited by LPCVD, a dual ion-blocking barrier is constructed, extending the migration distance of mobile ions from <1 μm in traditional designs to >5 μm.

[0033] A glass passivation layer 2 is disposed between the SiO2 protective layer 3 and the insulating polycrystalline silicon 1.

[0034] In this case, the glass passivation layer 2 is disposed on the top corner of the insulating polycrystalline silicon 1.

[0035] The small radius of curvature (typically <1μm) at the top corner of insulating polycrystalline silicon leads to dense electric field lines. In traditional designs, the electric field strength in this region can reach over 1.2 MV / cm, easily causing avalanche breakdown and increased leakage current. This design utilizes the field plate effect of the glass passivation layer to transfer the peak electric field from the silicon surface to the interior of the passivation layer, reducing the electric field strength at the corner by more than 30%. The stepped extension of the glass passivation layer at the corner (from the top of the insulating polycrystalline silicon to the side of the N-epitaxial layer) forms a stress buffer zone.

[0036] In this case, the resistivity of the N+ substrate 8 is 3-10 Ω·cm, and the thickness is 10-30 μm.

[0037] The resistivity of the N-epitaxial layer 7 is 25-50 Ω·cm, and the thickness is 30-80 μm.

[0038] The doping concentration of P+ implantation region 6 is 10. 15 -10 18 cm -3 The thickness is 8-16um. The thickness of the insulating polycrystalline silicon 1 is 3000-8000 angstroms, the thickness of the glass passivation layer 2 is 50-80 μm, and the thickness of the LTO (SiO2 protective layer 3) film is 3000-9000 angstroms.

[0039] This invention utilizes ion implantation to form the P+ implantation region 6. Before metal evaporation, a layer of aluminum is deposited using thin-film sputtering. An alloy is then applied to create a stable ohmic contact region 4 between this metal layer and the P+ implantation region 6. This innovative design significantly reduces the forward voltage drop (VF) of the device, thereby effectively reducing operating losses and improving efficiency. Furthermore, this invention combines a SiPOS film, a glass passivation layer 2, and an LTO three-layer passivation process, significantly enhancing the product's reliability and stability, enabling it to perform exceptionally well in low-power, high-efficiency applications.

[0040] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A low-VF PIN rectifier diode, characterized in that, It includes, from bottom to top, a back metal layer (9), an N+ substrate (8), an N- epitaxial layer (7), a P+ implantation region (6), an ohmic contact region (4), and a front metal layer (5). The N-epilithographic layer (7) and the P+ implantation region (6) are respectively provided with trenches; the trenches are provided with: Insulating polycrystalline silicon (1) extends downward from the top surface of the P+ implantation region (6) along the trench to the N- epitaxial layer (7); The SiO2 protective layer (3) extends upward from the top surface of the insulating polycrystalline silicon (1) and falls to the side of the N-epitaxial layer (7), and is connected to the insulating polycrystalline silicon (1); A glass passivation layer (2) is disposed between the SiO2 protective layer (3) and the insulating polycrystalline silicon (1).

2. A low-VF PIN rectifier diode according to claim 1, characterized in that, The resistivity of the N+ substrate (8) is 3-10 Ω·cm and the thickness is 10-30 μm.

3. A low-VF PIN rectifier diode according to claim 1, characterized in that, The insulating polycrystalline silicon (1) has a thickness of 3000-8000 angstroms.

4. A low-VF PIN rectifier diode according to claim 1, characterized in that, The glass passivation layer (2) extends downward from the top of the insulating polycrystalline silicon (1) to the side region of the N-epitaxial layer (7).

5. A low-VF PIN rectifier diode according to claim 1, characterized in that, The thickness of the glass passivation layer (2) is 50-80 μm.

6. A low-VF PIN rectifier diode according to claim 1, characterized in that, The thickness of the SiO2 protective layer (3) is 3000-9000 angstroms.

7. A low-VF PIN rectifier diode according to claim 1, characterized in that, The insulating polycrystalline silicon (1) is connected to the front metal layer (5), the ohmic contact region (4), the P+ implantation region (6) and the N- epitaxial layer (7), respectively.

8. A low-VF PIN rectifier diode according to claim 1, characterized in that, The top surface of the front metal layer (5) is located below the top of the SiO2 protective layer (3).

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