A structure for reducing gate charge of SiC-MOSFET

Abstract

The utility model discloses a structure of reducing SiC-MOSFET grid charge relates to the technical field of semiconductor discrete device, including n+ substrate and P - body diffusion window, the n+ substrate top is provided with n - epitaxial layer, and the left and right sides of n - epitaxial layer are provided with two unicellular main knots of device, the N+JFET window top is provided with P - body diffusion window, through twice etching to grid polycrystal silicon, the diffusion window of P - body is formed to the first etching, and the diffusion window of shallow P+ is formed to the second etching, etching grid polycrystal silicon into four sections simultaneously, and this structure effectively reduces the area of grid leakage capacitor Cgd. Grid leakage capacitor Cgd is closely related to grid charge, and the size of Cgd reduces to make the size of Cgd, and further significantly reduces the grid charge.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor discrete device technology, specifically to a structure and manufacturing method for reducing the gate charge of a SiC-MOSFET. Background Technology

[0002] Advantages of SiC-MOSFETs: (1) Excellent high-temperature characteristics: They can still operate normally at high temperatures, exhibiting higher thermal stability and suitable for harsh environments with high temperatures and high pressures. (2) Excellent high-frequency characteristics: Due to the high electron mobility and low losses of SiC transistors, they offer better performance in high-frequency applications. (3) Fast switching speed: The small gate capacitance of SiC transistors enables faster switching speeds, resulting in higher efficiency. (4) Low on-resistance: The on-resistance of SiC transistors is much lower than that of silicon transistors, resulting in lower conduction losses. (5) Small size and light weight: SiC transistors utilize smaller chips, resulting in smaller device sizes and lighter weights for the same power consumption, allowing for higher integration of power devices.

[0003] Disadvantages of SiC-MOSFETs: The manufacturing process is difficult, requiring more complex materials and processes, resulting in higher manufacturing costs. The main issue is that the implantation process is incompatible with that of silicon transistors.

[0004] With the increasing demand for high-frequency, high-efficiency power supplies, there is a growing need for SiC power MOSFETs that offer faster speeds, lower power consumption, and lower on-resistance. Circuit designers, aiming to improve circuit efficiency, primarily focus on the device's figure of merit (FOM) = (RDS(on) × Qgd). The gate-drain charge Qgd reflects the device's switching losses; a smaller Qgd indicates lower switching losses, while a larger Qgd indicates higher switching losses. The on-resistance RDS(on) reflects the device's conduction losses; a smaller RDS(on) indicates lower conduction losses, while a smaller RDS(on) indicates higher conduction losses. Therefore, the design must comprehensively consider the effects of both on-resistance and gate charge. Utility Model Content

[0005] To address the shortcomings of existing technologies, this invention provides a structure and manufacturing method for reducing the gate charge of SiC-MOSFETs, solving the problem of how to minimize the gate charge as much as possible while ensuring that the on-resistance meets the requirements, thereby achieving high-frequency applications and improving the figure of merit (FOM).

[0006] To achieve the above objectives, this utility model is implemented through the following technical solution: It includes an n+ substrate and a P-body diffusion window. An n-epitaxial layer is disposed above the n+ substrate, and two main junctions of the device are disposed on the left and right sides of the n-epitaxial layer. A P-body diffusion window is disposed above the N+JFET window. The N+JFET window and the P-body diffusion window are implanted to form a vertical contact surface. An N+JFET window is disposed between the two P-body diffusion windows. A gate POLY window is disposed on the P-body diffusion window, and a gate dielectric layer is vertically disposed on the P-body diffusion window. The device structure is a strip structure or a cell structure. The gate polysilicon is etched twice: the first etching forms the P-body diffusion window, and the second etching forms a shallow P+ diffusion window. Simultaneously, the gate polysilicon in the figure is etched into four segments, which can effectively reduce the area of ​​the gate-drain capacitance Cgd, thereby reducing the size of Cgd.

[0007] Preferably, a gate POLY window and an isolation layer are sequentially disposed on the gate dielectric layer. A source metal layer is disposed on the isolation layer. A source N+ diffusion window and a source P+ window are laterally disposed on the isolation layer. Source lead vias are disposed on both the source N+ diffusion window and the source P+ window. The source N+ diffusion window and the source P+ window are connected to the source metal layer through the source lead vias to form the source. A POLY window and lead vias are disposed in the vertical direction of the N+ JFET window. A shallow P+ injection window and a P+ injection window are disposed in the horizontal direction of the N+ JFET window. The isolation layer is etched to form the P+ injection window. The P+ injection window and the shallow P+ diffusion window can effectively increase the width of the space charge depletion layer, thereby reducing the gate drain capacitance Cgd.

[0008] Preferably, a source metal layer is disposed above the POLY window, and the POLY window is connected to the source metal layer through a lead hole. A gate metal layer is disposed above the gate POLY window, and the gate POLY window is connected to the gate metal through an opening to form a gate. The source N+ diffusion window and the source P+ diffusion window and the source lead hole form a ladder-shaped new structure connected to the source metal layer. The ladder-shaped new structure eliminates the overlap area between the source n+ diffusion window and the gate dielectric layer and the gate POLY window. At the same time, the lead hole can be made smaller, and more cells can be connected in parallel per unit area. This can effectively reduce the on-resistance RDSon of the device and contribute to the FOM of the MOSFET.

[0009] Preferably, the isolation layer and the source metal layer are connected to each other, and the opening on the gate metal is connected to the gate POLY window.

[0010] Preferably, a junction termination region field limiting ring is provided on the outer side of the source metal layer, the source metal layer is not connected to the junction termination region field limiting ring, the junction termination region field limiting ring is a composite structure of junction termination region field limiting ring + composite field plate + cutoff ring, and a scribe line is provided on the outer side of the junction termination region field limiting ring.

[0011] The structure for reducing gate charge in SiC-MOSFETs provided by this invention has the following beneficial effects: 1. From a structural design perspective, by performing two etching processes on the gate polysilicon—the first etching forming a P-body diffusion window and the second etching forming a shallow P+ diffusion window—and simultaneously etching the gate polysilicon into four segments, this structure effectively reduces the area of ​​the gate-drain capacitance Cgd. The gate-drain capacitance Cgd is closely related to the gate charge; reducing the Cgd area decreases the size of Cgd, thereby significantly reducing the gate charge. In practical applications, this structure can reduce the MOSFET gate charge by 17.6%-25.8%, which is of great significance for reducing device switching losses and improving circuit efficiency.

[0012] 2. A novel ladder-shaped structure is formed by the source N+ diffusion window, the source P+ diffusion window, and the source via, and is connected to the source metal layer. This unique structure eliminates the overlap between the source N+ diffusion window and the gate dielectric layer and the gate POLY window, avoiding the resistance increase caused by overlap. Simultaneously, due to structural optimization, the via can be made smaller, allowing more cells to be connected in parallel per unit area. According to electrical principles, more cells connected in parallel reduce the overall resistance; therefore, this structure effectively reduces the device's on-resistance RDS(on). Practical verification shows that the on-resistance can be reduced by 15.5%-27.9%, thereby reducing the device's conduction losses.

[0013] 3. Structurally, the isolation layer is etched to form a P+ injection window and a shallow P+ diffusion window. This design effectively increases the width of the depletion layer in the space charge region. According to the principles of capacitance, increasing the depletion layer width reduces the gate-drain capacitance Cgd. By optimizing the depletion layer structure, the gate charge is further reduced, improving device performance.

[0014] 4. A junction termination field limiting ring is provided on the outer side of the source metal layer. This junction termination field limiting ring adopts a composite structure of junction termination field limiting ring + composite field plate + stop ring. This composite structure can effectively limit the electric field distribution and prevent electric field concentration at the edge of the device, thereby improving the stability and reliability of the device and ensuring that the device can operate normally under various operating conditions. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall structure of this utility model; Figure 2This is a schematic diagram of the layout of this utility model; Figure 3 This is a schematic diagram of the parasitic capacitance of a conventional MOSFET structure according to this utility model.

[0016] In the figure: 1. n+ substrate; 2. n- epitaxial layer; 3. N+ JFET window; 4. Gate dielectric layer; 5. Gate POLY window; 6. P-body diffusion window; 7. Source N+ diffusion window; 8. POLY window; 9. Shallow P+ implantation; 10. Source P+ window; 11. Through-hole window; 12. P+ implantation window; 13. Isolation layer; 14. Through-hole of POLY window; 15. Source metal layer; 16. Gate metal; 17. Junction termination field confinement ring; 18. Die-etching track. Detailed Implementation

[0017] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0018] Please see Figure 1-3This utility model provides a technical solution including an n+ substrate 1 and a P-body diffusion window 6. An n-epitaxial layer 2 is disposed above the n+ substrate 1. Two main junctions of the device are disposed on the left and right sides of the n-epitaxial layer 2. A P-body diffusion window 6 is disposed above an N+JFET window 3. The N+JFET window 3 and the P-body diffusion window 6 are implanted to form a vertical contact surface. An N+JFET window 3 is disposed between the two P-body diffusion windows 6. A gate POLY window 5 is disposed on the P-body diffusion window 6. A gate dielectric layer 4 is vertically disposed on the P-body diffusion window 6. A gate POLY window 5 and an isolation layer 13 are sequentially disposed on the gate dielectric layer 4. A source metal layer 15 is disposed on the isolation layer 13. A source N+ diffusion window 7 and a source P+ window 10 are laterally disposed on the isolation layer 13. Source lead holes 11 are disposed on both the source N+ diffusion window 7 and the source P+ window 10. The source N+ diffusion window 7 and the source P+ window 10 are connected to the source metal layer 15 through the source lead holes 11 to form the source. A POLY window 8 and a lead hole 14 are disposed in the vertical direction of the N+ JFET window 3. A shallow P+ injection window 9 and a P+ injection window 12 are disposed in the horizontal direction of the N+ JFET window 3. A source metal layer 15 is disposed above the POLY window 8. The POLY window 8 is connected to the source metal layer 15 through the lead hole 14. A gate metal 16 is disposed above the gate POLY window 5. The gate POLY window 5 is connected to the gate metal 16 through an opening to form the gate. The isolation layer 13 and the source metal layer 15 are connected to each other. An opening on the gate metal 16 is connected to the gate POLY window 5. A junction termination region field limiting ring 17 is provided outside the source metal layer 15. The source metal layer 15 is not connected to the junction termination region field limiting ring 17. The junction termination region field limiting ring 17 is a composite structure of junction termination region field limiting ring + composite field plate + cutoff ring. A scribe line 18 is provided outside the junction termination region field limiting ring 17.

[0019] In terms of working principle, reducing the gate charge of a MOSFET is mainly achieved by reducing the intrinsic capacitance and parasitic capacitance of the device. The capacitance of a MOSFET mainly consists of three parts: the gate-source capacitance Cgs, the gate-drain capacitance Cgd, and the source-drain capacitance Cds.

[0020] The gate-source capacitance Cgs = Cgs(N+) + Cgs(metal) + Cgs(p-body), where Cgs(N+) is the gate-source overlap capacitance, Cgs(metal) is the capacitance between the gate and source metals, and Cgs(p-body) is the capacitance between the gate and the P-body. The magnitude of these three capacitances depends on the design parameters of the MOSFET itself, and most importantly, on the thickness of the USG / BPSG.

[0021] Gate-drain capacitance Cgd = Cgd(ox)Cgd(dep) / 〔Cgd(ox)+Cgd(dep)〕 When the gate voltage does not reach the threshold voltage, the depletion layer formed by the epitaxial N-epi and P-body is connected together (e.g. Figure 3 As shown by the dashed line, a large depletion layer capacitance is formed. The gate poly contains the gate dielectric layer capacitance Cgd(ox) and the space charge region depletion layer capacitance Cgd(dep). At this point, the depletion layer width is at its maximum, and the depletion layer capacitance is at its minimum. When the gate voltage reaches the threshold voltage, the device turns on, the drain potential decreases, the depletion layer width decreases, and the space charge region depletion layer capacitance Cgd(dep) increases rapidly. The magnitude of Cgd(ox) depends on the thickness of the gate dielectric layer OX, but primarily on the magnitude of Cgd(dep).

[0022] The gate-source capacitance Cgs is the PN junction capacitance, and its size depends on the magnitude of the voltage VDS applied between the drain and source.

[0023] By etching the POLY window 8 in the second polysilicon etching process, the overlap area between the polysilicon and the epitaxial region can be reduced, which can greatly reduce Qgd.

[0024] By shallow P+ injection 9 and P+ injection 12, the shape of the depletion region under the gate is changed, increasing the width of the depletion region and thus reducing Qgd. The source N+ diffusion window 7, the source P+ diffusion window 10, and the source lead hole 11 form a ladder-shaped new structure connected to the source metal layer 15. The ladder-shaped new structure eliminates the overlap between the source n+ diffusion window 7 and the gate dielectric layer 4 and the gate POLY window 5. At the same time, the lead hole 11 can be made smaller, and more cells can be connected in parallel per unit area, which can effectively reduce the on-resistance RDS(on) of the device.

[0025] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0026] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A structure for reducing the gate charge of a SiC-MOSFET, comprising an n+ substrate (1) and a P-body diffusion window (6), characterized in that: An n-epitaxial layer (2) is disposed above the n+ substrate (1). Two main junctions of the device are disposed on the left and right sides of the n-epitaxial layer (2). A P-body diffusion window (6) is disposed above the N+JFET window (3). The N+JFET window (3) and the P-body diffusion window (6) are injected to form a vertical contact surface. An N+JFET window (3) is disposed between the two P-body diffusion windows (6). A gate POLY window (5) is disposed on the P-body diffusion window (6). A gate dielectric layer (4) is disposed vertically on the P-body diffusion window (6).

2. The structure for reducing the gate charge of a SiC-MOSFET according to claim 1, characterized in that: A gate POLY window (5) and an isolation layer (13) are sequentially disposed on the gate dielectric layer (4). A source metal layer (15) is disposed on the isolation layer (13). A source N+ diffusion window (7) and a source P+ window (10) are disposed laterally on the isolation layer (13). A source lead hole (11) is disposed on both the source N+ diffusion window (7) and the source P+ window (10). The source N+ diffusion window (7) and the source P+ window (10) are connected to the source metal layer (15) through the source lead hole (11) to form a source. A POLY window (8) and a lead hole (14) are disposed in the vertical direction of the N+ JFET window (3). A shallow P+ injection window (9) and a P+ injection window (12) are disposed in the horizontal direction of the N+ JFET window (3).

3. The structure for reducing the gate charge of a SiC-MOSFET according to claim 2, characterized in that: A source metal layer (15) is disposed above the POLY window (8). The POLY window (8) is connected to the source metal layer (15) through a lead hole (14). A gate metal (16) is disposed above the gate POLY window (5). The gate POLY window (5) is connected to the gate metal (16) through an opening to form a gate.

4. The structure for reducing the gate charge of a SiC-MOSFET according to claim 3, characterized in that: The isolation layer (13) and the source metal layer (15) are connected to each other, and the opening on the gate metal (16) is connected to the gate POLY window (5).

5. The structure for reducing the gate charge of a SiC-MOSFET according to claim 4, characterized in that: A junction terminal field limiting ring (17) is provided on the outside of the source metal layer (15). The source metal layer (15) is not connected to the junction terminal field limiting ring (17). The junction terminal field limiting ring (17) is a composite structure of junction terminal field limiting ring + composite field plate + stop ring. A scribing channel (18) is provided on the outside of the junction terminal field limiting ring (17).

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